habanalabs: make last_mask an MMU property
Currently LAST_MASK is a global, but really it is an MMU implementation specific. We need this change for future ASICs. Signed-off-by: Yuri Nudelman <ynudelman@habana.ai> Reviewed-by: Oded Gabbay <ogabbay@kernel.org> Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
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@ -382,6 +382,7 @@ enum hl_device_hw_state {
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* @hop3_mask: mask to get the PTE address in hop 3.
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* @hop3_mask: mask to get the PTE address in hop 3.
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* @hop4_mask: mask to get the PTE address in hop 4.
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* @hop4_mask: mask to get the PTE address in hop 4.
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* @hop5_mask: mask to get the PTE address in hop 5.
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* @hop5_mask: mask to get the PTE address in hop 5.
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* @last_mask: mask to get the bit indicating this is the last hop.
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* @page_size: default page size used to allocate memory.
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* @page_size: default page size used to allocate memory.
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* @num_hops: The amount of hops supported by the translation table.
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* @num_hops: The amount of hops supported by the translation table.
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* @host_resident: Should the MMU page table reside in host memory or in the
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* @host_resident: Should the MMU page table reside in host memory or in the
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@ -402,6 +403,7 @@ struct hl_mmu_properties {
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u64 hop3_mask;
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u64 hop3_mask;
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u64 hop4_mask;
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u64 hop4_mask;
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u64 hop5_mask;
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u64 hop5_mask;
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u64 last_mask;
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u32 page_size;
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u32 page_size;
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u32 num_hops;
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u32 num_hops;
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u8 host_resident;
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u8 host_resident;
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@ -573,7 +573,7 @@ static int _hl_mmu_v1_unmap(struct hl_ctx *ctx,
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curr_pte = *(u64 *) (uintptr_t) hop3_pte_addr;
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curr_pte = *(u64 *) (uintptr_t) hop3_pte_addr;
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is_huge = curr_pte & LAST_MASK;
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is_huge = curr_pte & mmu_prop->last_mask;
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if (is_dram_addr && !is_huge) {
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if (is_dram_addr && !is_huge) {
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dev_err(hdev->dev,
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dev_err(hdev->dev,
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@ -597,7 +597,7 @@ static int _hl_mmu_v1_unmap(struct hl_ctx *ctx,
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if (hdev->dram_default_page_mapping && is_dram_addr) {
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if (hdev->dram_default_page_mapping && is_dram_addr) {
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u64 default_pte = (prop->mmu_dram_default_page_addr &
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u64 default_pte = (prop->mmu_dram_default_page_addr &
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HOP_PHYS_ADDR_MASK) | LAST_MASK |
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HOP_PHYS_ADDR_MASK) | mmu_prop->last_mask |
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PAGE_PRESENT_MASK;
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PAGE_PRESENT_MASK;
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if (curr_pte == default_pte) {
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if (curr_pte == default_pte) {
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dev_err(hdev->dev,
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dev_err(hdev->dev,
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@ -729,7 +729,7 @@ static int _hl_mmu_v1_map(struct hl_ctx *ctx, u64 virt_addr, u64 phys_addr,
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if (hdev->dram_default_page_mapping && is_dram_addr) {
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if (hdev->dram_default_page_mapping && is_dram_addr) {
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u64 default_pte = (prop->mmu_dram_default_page_addr &
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u64 default_pte = (prop->mmu_dram_default_page_addr &
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HOP_PHYS_ADDR_MASK) | LAST_MASK |
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HOP_PHYS_ADDR_MASK) | mmu_prop->last_mask |
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PAGE_PRESENT_MASK;
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PAGE_PRESENT_MASK;
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if (curr_pte != default_pte) {
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if (curr_pte != default_pte) {
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@ -769,7 +769,7 @@ static int _hl_mmu_v1_map(struct hl_ctx *ctx, u64 virt_addr, u64 phys_addr,
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goto err;
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goto err;
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}
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}
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curr_pte = (phys_addr & HOP_PHYS_ADDR_MASK) | LAST_MASK
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curr_pte = (phys_addr & HOP_PHYS_ADDR_MASK) | mmu_prop->last_mask
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| PAGE_PRESENT_MASK;
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| PAGE_PRESENT_MASK;
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if (is_huge)
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if (is_huge)
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@ -930,7 +930,7 @@ static int hl_mmu_v1_get_tlb_info(struct hl_ctx *ctx, u64 virt_addr,
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if (!(hops->hop_info[i].hop_pte_val & PAGE_PRESENT_MASK))
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if (!(hops->hop_info[i].hop_pte_val & PAGE_PRESENT_MASK))
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return -EFAULT;
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return -EFAULT;
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if (hops->hop_info[i].hop_pte_val & LAST_MASK)
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if (hops->hop_info[i].hop_pte_val & mmu_prop->last_mask)
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break;
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break;
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}
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}
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@ -613,6 +613,7 @@ static int gaudi_set_fixed_properties(struct hl_device *hdev)
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(VA_HOST_SPACE_START + VA_HOST_SPACE_SIZE / 2) - 1;
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(VA_HOST_SPACE_START + VA_HOST_SPACE_SIZE / 2) - 1;
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prop->pmmu.page_size = PAGE_SIZE_4KB;
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prop->pmmu.page_size = PAGE_SIZE_4KB;
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prop->pmmu.num_hops = MMU_ARCH_5_HOPS;
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prop->pmmu.num_hops = MMU_ARCH_5_HOPS;
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prop->pmmu.last_mask = LAST_MASK;
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/* PMMU and HPMMU are the same except of page size */
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/* PMMU and HPMMU are the same except of page size */
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memcpy(&prop->pmmu_huge, &prop->pmmu, sizeof(prop->pmmu));
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memcpy(&prop->pmmu_huge, &prop->pmmu, sizeof(prop->pmmu));
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@ -429,6 +429,7 @@ int goya_set_fixed_properties(struct hl_device *hdev)
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prop->dmmu.end_addr = VA_DDR_SPACE_END;
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prop->dmmu.end_addr = VA_DDR_SPACE_END;
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prop->dmmu.page_size = PAGE_SIZE_2MB;
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prop->dmmu.page_size = PAGE_SIZE_2MB;
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prop->dmmu.num_hops = MMU_ARCH_5_HOPS;
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prop->dmmu.num_hops = MMU_ARCH_5_HOPS;
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prop->dmmu.last_mask = LAST_MASK;
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/* shifts and masks are the same in PMMU and DMMU */
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/* shifts and masks are the same in PMMU and DMMU */
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memcpy(&prop->pmmu, &prop->dmmu, sizeof(prop->dmmu));
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memcpy(&prop->pmmu, &prop->dmmu, sizeof(prop->dmmu));
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@ -436,6 +437,7 @@ int goya_set_fixed_properties(struct hl_device *hdev)
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prop->pmmu.end_addr = VA_HOST_SPACE_END;
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prop->pmmu.end_addr = VA_HOST_SPACE_END;
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prop->pmmu.page_size = PAGE_SIZE_4KB;
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prop->pmmu.page_size = PAGE_SIZE_4KB;
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prop->pmmu.num_hops = MMU_ARCH_5_HOPS;
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prop->pmmu.num_hops = MMU_ARCH_5_HOPS;
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prop->pmmu.last_mask = LAST_MASK;
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/* PMMU and HPMMU are the same except of page size */
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/* PMMU and HPMMU are the same except of page size */
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memcpy(&prop->pmmu_huge, &prop->pmmu, sizeof(prop->pmmu));
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memcpy(&prop->pmmu_huge, &prop->pmmu, sizeof(prop->pmmu));
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