mfd: stmpe: Rework registers access
this update allows to use registers map as following : regs[reg_index + offset] instead of regs[reg_index] + offset This makes code clearer and will facilitate the addition of STMPE1600 on which LSB and MSB registers are respectively located at addr and addr + 1. Despite for all others STMPE variant, LSB and MSB registers are respectively located in reverse order at addr + 1 and addr. For variant which have 3 registers's bank, we use LSB,CSB and MSB indexes which contains respectively LSB (or LOW), CSB (or MID) and MSB (or HIGH) register addresses (STMPE1801/STMPE24xx). For variant which have 2 registers's bank, we use LSB and CSB indexes only. In this case the CSB index contains the MSB regs address (STMPE 1601). Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
This commit is contained in:
Patrice Chotard
Lee Jones
parent
c16bee7897
commit
897ac6674c
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@ -483,7 +483,7 @@ static const u8 stmpe811_regs[] = {
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[STMPE_IDX_GPAFR_U_MSB] = STMPE811_REG_GPIO_AF,
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[STMPE_IDX_IEGPIOR_LSB] = STMPE811_REG_GPIO_INT_EN,
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[STMPE_IDX_ISGPIOR_MSB] = STMPE811_REG_GPIO_INT_STA,
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[STMPE_IDX_GPEDR_MSB] = STMPE811_REG_GPIO_ED,
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[STMPE_IDX_GPEDR_LSB] = STMPE811_REG_GPIO_ED,
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};
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static struct stmpe_variant_block stmpe811_blocks[] = {
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@ -561,19 +561,28 @@ static const u8 stmpe1601_regs[] = {
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[STMPE_IDX_SYS_CTRL] = STMPE1601_REG_SYS_CTRL,
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[STMPE_IDX_SYS_CTRL2] = STMPE1601_REG_SYS_CTRL2,
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[STMPE_IDX_ICR_LSB] = STMPE1601_REG_ICR_LSB,
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[STMPE_IDX_IER_MSB] = STMPE1601_REG_IER_MSB,
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[STMPE_IDX_IER_LSB] = STMPE1601_REG_IER_LSB,
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[STMPE_IDX_ISR_MSB] = STMPE1601_REG_ISR_MSB,
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[STMPE_IDX_GPMR_LSB] = STMPE1601_REG_GPIO_MP_LSB,
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[STMPE_IDX_GPMR_CSB] = STMPE1601_REG_GPIO_MP_MSB,
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[STMPE_IDX_GPSR_LSB] = STMPE1601_REG_GPIO_SET_LSB,
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[STMPE_IDX_GPSR_CSB] = STMPE1601_REG_GPIO_SET_MSB,
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[STMPE_IDX_GPCR_LSB] = STMPE1601_REG_GPIO_CLR_LSB,
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[STMPE_IDX_GPCR_CSB] = STMPE1601_REG_GPIO_CLR_MSB,
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[STMPE_IDX_GPDR_LSB] = STMPE1601_REG_GPIO_SET_DIR_LSB,
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[STMPE_IDX_GPDR_CSB] = STMPE1601_REG_GPIO_SET_DIR_MSB,
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[STMPE_IDX_GPEDR_LSB] = STMPE1601_REG_GPIO_ED_LSB,
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[STMPE_IDX_GPEDR_CSB] = STMPE1601_REG_GPIO_ED_MSB,
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[STMPE_IDX_GPRER_LSB] = STMPE1601_REG_GPIO_RE_LSB,
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[STMPE_IDX_GPRER_CSB] = STMPE1601_REG_GPIO_RE_MSB,
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[STMPE_IDX_GPFER_LSB] = STMPE1601_REG_GPIO_FE_LSB,
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[STMPE_IDX_GPFER_CSB] = STMPE1601_REG_GPIO_FE_MSB,
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[STMPE_IDX_GPPUR_LSB] = STMPE1601_REG_GPIO_PU_LSB,
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[STMPE_IDX_GPAFR_U_MSB] = STMPE1601_REG_GPIO_AF_U_MSB,
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[STMPE_IDX_IEGPIOR_LSB] = STMPE1601_REG_INT_EN_GPIO_MASK_LSB,
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[STMPE_IDX_IEGPIOR_CSB] = STMPE1601_REG_INT_EN_GPIO_MASK_MSB,
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[STMPE_IDX_ISGPIOR_MSB] = STMPE1601_REG_INT_STA_GPIO_MSB,
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[STMPE_IDX_GPEDR_MSB] = STMPE1601_REG_GPIO_ED_MSB,
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};
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static struct stmpe_variant_block stmpe1601_blocks[] = {
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@ -719,14 +728,28 @@ static const u8 stmpe1801_regs[] = {
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[STMPE_IDX_IER_LSB] = STMPE1801_REG_INT_EN_MASK_LOW,
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[STMPE_IDX_ISR_LSB] = STMPE1801_REG_INT_STA_LOW,
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[STMPE_IDX_GPMR_LSB] = STMPE1801_REG_GPIO_MP_LOW,
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[STMPE_IDX_GPMR_CSB] = STMPE1801_REG_GPIO_MP_MID,
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[STMPE_IDX_GPMR_MSB] = STMPE1801_REG_GPIO_MP_HIGH,
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[STMPE_IDX_GPSR_LSB] = STMPE1801_REG_GPIO_SET_LOW,
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[STMPE_IDX_GPSR_CSB] = STMPE1801_REG_GPIO_SET_MID,
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[STMPE_IDX_GPSR_MSB] = STMPE1801_REG_GPIO_SET_HIGH,
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[STMPE_IDX_GPCR_LSB] = STMPE1801_REG_GPIO_CLR_LOW,
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[STMPE_IDX_GPCR_CSB] = STMPE1801_REG_GPIO_CLR_MID,
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[STMPE_IDX_GPCR_MSB] = STMPE1801_REG_GPIO_CLR_HIGH,
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[STMPE_IDX_GPDR_LSB] = STMPE1801_REG_GPIO_SET_DIR_LOW,
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[STMPE_IDX_GPDR_CSB] = STMPE1801_REG_GPIO_SET_DIR_MID,
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[STMPE_IDX_GPDR_MSB] = STMPE1801_REG_GPIO_SET_DIR_HIGH,
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[STMPE_IDX_GPRER_LSB] = STMPE1801_REG_GPIO_RE_LOW,
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[STMPE_IDX_GPRER_CSB] = STMPE1801_REG_GPIO_RE_MID,
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[STMPE_IDX_GPRER_MSB] = STMPE1801_REG_GPIO_RE_HIGH,
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[STMPE_IDX_GPFER_LSB] = STMPE1801_REG_GPIO_FE_LOW,
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[STMPE_IDX_GPFER_CSB] = STMPE1801_REG_GPIO_FE_MID,
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[STMPE_IDX_GPFER_MSB] = STMPE1801_REG_GPIO_FE_HIGH,
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[STMPE_IDX_GPPUR_LSB] = STMPE1801_REG_GPIO_PULL_UP_LOW,
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[STMPE_IDX_IEGPIOR_LSB] = STMPE1801_REG_INT_EN_GPIO_MASK_LOW,
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[STMPE_IDX_ISGPIOR_LSB] = STMPE1801_REG_INT_STA_GPIO_LOW,
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[STMPE_IDX_IEGPIOR_CSB] = STMPE1801_REG_INT_EN_GPIO_MASK_MID,
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[STMPE_IDX_IEGPIOR_MSB] = STMPE1801_REG_INT_EN_GPIO_MASK_HIGH,
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[STMPE_IDX_ISGPIOR_MSB] = STMPE1801_REG_INT_STA_GPIO_HIGH,
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};
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static struct stmpe_variant_block stmpe1801_blocks[] = {
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@ -811,19 +834,36 @@ static const u8 stmpe24xx_regs[] = {
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[STMPE_IDX_SYS_CTRL] = STMPE24XX_REG_SYS_CTRL,
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[STMPE_IDX_SYS_CTRL2] = STMPE24XX_REG_SYS_CTRL2,
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[STMPE_IDX_ICR_LSB] = STMPE24XX_REG_ICR_LSB,
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[STMPE_IDX_IER_MSB] = STMPE24XX_REG_IER_MSB,
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[STMPE_IDX_IER_LSB] = STMPE24XX_REG_IER_LSB,
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[STMPE_IDX_ISR_MSB] = STMPE24XX_REG_ISR_MSB,
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[STMPE_IDX_GPMR_LSB] = STMPE24XX_REG_GPMR_LSB,
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[STMPE_IDX_GPMR_CSB] = STMPE24XX_REG_GPMR_CSB,
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[STMPE_IDX_GPMR_MSB] = STMPE24XX_REG_GPMR_MSB,
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[STMPE_IDX_GPSR_LSB] = STMPE24XX_REG_GPSR_LSB,
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[STMPE_IDX_GPSR_CSB] = STMPE24XX_REG_GPSR_CSB,
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[STMPE_IDX_GPSR_MSB] = STMPE24XX_REG_GPSR_MSB,
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[STMPE_IDX_GPCR_LSB] = STMPE24XX_REG_GPCR_LSB,
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[STMPE_IDX_GPCR_CSB] = STMPE24XX_REG_GPCR_CSB,
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[STMPE_IDX_GPCR_MSB] = STMPE24XX_REG_GPCR_MSB,
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[STMPE_IDX_GPDR_LSB] = STMPE24XX_REG_GPDR_LSB,
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[STMPE_IDX_GPDR_CSB] = STMPE24XX_REG_GPDR_CSB,
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[STMPE_IDX_GPDR_MSB] = STMPE24XX_REG_GPDR_MSB,
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[STMPE_IDX_GPRER_LSB] = STMPE24XX_REG_GPRER_LSB,
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[STMPE_IDX_GPRER_CSB] = STMPE24XX_REG_GPRER_CSB,
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[STMPE_IDX_GPRER_MSB] = STMPE24XX_REG_GPRER_MSB,
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[STMPE_IDX_GPFER_LSB] = STMPE24XX_REG_GPFER_LSB,
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[STMPE_IDX_GPFER_CSB] = STMPE24XX_REG_GPFER_CSB,
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[STMPE_IDX_GPFER_MSB] = STMPE24XX_REG_GPFER_MSB,
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[STMPE_IDX_GPPUR_LSB] = STMPE24XX_REG_GPPUR_LSB,
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[STMPE_IDX_GPPDR_LSB] = STMPE24XX_REG_GPPDR_LSB,
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[STMPE_IDX_GPAFR_U_MSB] = STMPE24XX_REG_GPAFR_U_MSB,
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[STMPE_IDX_IEGPIOR_LSB] = STMPE24XX_REG_IEGPIOR_LSB,
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[STMPE_IDX_IEGPIOR_CSB] = STMPE24XX_REG_IEGPIOR_CSB,
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[STMPE_IDX_IEGPIOR_MSB] = STMPE24XX_REG_IEGPIOR_MSB,
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[STMPE_IDX_ISGPIOR_MSB] = STMPE24XX_REG_ISGPIOR_MSB,
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[STMPE_IDX_GPEDR_LSB] = STMPE24XX_REG_GPEDR_LSB,
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[STMPE_IDX_GPEDR_CSB] = STMPE24XX_REG_GPEDR_CSB,
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[STMPE_IDX_GPEDR_MSB] = STMPE24XX_REG_GPEDR_MSB,
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};
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@ -998,7 +1038,7 @@ static void stmpe_irq_sync_unlock(struct irq_data *data)
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continue;
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stmpe->oldier[i] = new;
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stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_IER_LSB] - i, new);
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stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_IER_LSB + i], new);
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}
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mutex_unlock(&stmpe->irq_lock);
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@ -179,19 +179,32 @@ int stmpe_remove(struct stmpe *stmpe);
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#define STMPE1601_REG_SYS_CTRL 0x02
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#define STMPE1601_REG_SYS_CTRL2 0x03
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#define STMPE1601_REG_ICR_MSB 0x10
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#define STMPE1601_REG_ICR_LSB 0x11
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#define STMPE1601_REG_IER_MSB 0x12
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#define STMPE1601_REG_IER_LSB 0x13
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#define STMPE1601_REG_ISR_MSB 0x14
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#define STMPE1601_REG_CHIP_ID 0x80
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#define STMPE1601_REG_ISR_LSB 0x15
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#define STMPE1601_REG_INT_EN_GPIO_MASK_MSB 0x16
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#define STMPE1601_REG_INT_EN_GPIO_MASK_LSB 0x17
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#define STMPE1601_REG_INT_STA_GPIO_MSB 0x18
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#define STMPE1601_REG_GPIO_MP_LSB 0x87
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#define STMPE1601_REG_INT_STA_GPIO_LSB 0x19
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#define STMPE1601_REG_CHIP_ID 0x80
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#define STMPE1601_REG_GPIO_SET_MSB 0x82
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#define STMPE1601_REG_GPIO_SET_LSB 0x83
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#define STMPE1601_REG_GPIO_CLR_MSB 0x84
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#define STMPE1601_REG_GPIO_CLR_LSB 0x85
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#define STMPE1601_REG_GPIO_MP_MSB 0x86
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#define STMPE1601_REG_GPIO_MP_LSB 0x87
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#define STMPE1601_REG_GPIO_SET_DIR_MSB 0x88
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#define STMPE1601_REG_GPIO_SET_DIR_LSB 0x89
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#define STMPE1601_REG_GPIO_ED_MSB 0x8A
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#define STMPE1601_REG_GPIO_ED_LSB 0x8B
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#define STMPE1601_REG_GPIO_RE_MSB 0x8C
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#define STMPE1601_REG_GPIO_RE_LSB 0x8D
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#define STMPE1601_REG_GPIO_FE_MSB 0x8E
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#define STMPE1601_REG_GPIO_FE_LSB 0x8F
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#define STMPE1601_REG_GPIO_PU_MSB 0x90
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#define STMPE1601_REG_GPIO_PU_LSB 0x91
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#define STMPE1601_REG_GPIO_AF_U_MSB 0x92
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@ -267,23 +280,47 @@ int stmpe_remove(struct stmpe *stmpe);
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#define STMPE24XX_REG_SYS_CTRL 0x02
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#define STMPE24XX_REG_SYS_CTRL2 0x03
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#define STMPE24XX_REG_ICR_MSB 0x10
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#define STMPE24XX_REG_ICR_LSB 0x11
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#define STMPE24XX_REG_IER_MSB 0x12
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#define STMPE24XX_REG_IER_LSB 0x13
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#define STMPE24XX_REG_ISR_MSB 0x14
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#define STMPE24XX_REG_CHIP_ID 0x80
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#define STMPE24XX_REG_ISR_LSB 0x15
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#define STMPE24XX_REG_IEGPIOR_MSB 0x16
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#define STMPE24XX_REG_IEGPIOR_CSB 0x17
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#define STMPE24XX_REG_IEGPIOR_LSB 0x18
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#define STMPE24XX_REG_ISGPIOR_MSB 0x19
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#define STMPE24XX_REG_GPMR_LSB 0xA4
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#define STMPE24XX_REG_ISGPIOR_CSB 0x1A
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#define STMPE24XX_REG_ISGPIOR_LSB 0x1B
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#define STMPE24XX_REG_CHIP_ID 0x80
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#define STMPE24XX_REG_GPSR_MSB 0x83
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#define STMPE24XX_REG_GPSR_CSB 0x84
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#define STMPE24XX_REG_GPSR_LSB 0x85
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#define STMPE24XX_REG_GPCR_MSB 0x86
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#define STMPE24XX_REG_GPCR_CSB 0x87
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#define STMPE24XX_REG_GPCR_LSB 0x88
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#define STMPE24XX_REG_GPDR_MSB 0x89
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#define STMPE24XX_REG_GPDR_CSB 0x8A
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#define STMPE24XX_REG_GPDR_LSB 0x8B
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#define STMPE24XX_REG_GPEDR_MSB 0x8C
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#define STMPE24XX_REG_GPEDR_CSB 0x8D
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#define STMPE24XX_REG_GPEDR_LSB 0x8E
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#define STMPE24XX_REG_GPRER_MSB 0x8F
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#define STMPE24XX_REG_GPRER_CSB 0x90
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#define STMPE24XX_REG_GPRER_LSB 0x91
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#define STMPE24XX_REG_GPFER_MSB 0x92
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#define STMPE24XX_REG_GPFER_CSB 0x93
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#define STMPE24XX_REG_GPFER_LSB 0x94
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#define STMPE24XX_REG_GPPUR_MSB 0x95
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#define STMPE24XX_REG_GPPUR_CSB 0x96
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#define STMPE24XX_REG_GPPUR_LSB 0x97
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#define STMPE24XX_REG_GPPDR_LSB 0x9a
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#define STMPE24XX_REG_GPPDR_MSB 0x98
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#define STMPE24XX_REG_GPPDR_CSB 0x99
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#define STMPE24XX_REG_GPPDR_LSB 0x9A
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#define STMPE24XX_REG_GPAFR_U_MSB 0x9B
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#define STMPE24XX_REG_GPMR_MSB 0xA2
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#define STMPE24XX_REG_GPMR_CSB 0xA3
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#define STMPE24XX_REG_GPMR_LSB 0xA4
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#define STMPE24XX_SYS_CTRL_ENABLE_GPIO (1 << 3)
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#define STMPE24XX_SYSCON_ENABLE_PWM (1 << 2)
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#define STMPE24XX_SYS_CTRL_ENABLE_KPC (1 << 1)
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@ -43,20 +43,38 @@ enum {
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STMPE_IDX_SYS_CTRL2,
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STMPE_IDX_ICR_LSB,
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STMPE_IDX_IER_LSB,
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STMPE_IDX_IER_MSB,
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STMPE_IDX_ISR_LSB,
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STMPE_IDX_ISR_MSB,
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STMPE_IDX_GPMR_LSB,
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STMPE_IDX_GPMR_CSB,
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STMPE_IDX_GPMR_MSB,
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STMPE_IDX_GPSR_LSB,
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STMPE_IDX_GPSR_CSB,
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STMPE_IDX_GPSR_MSB,
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STMPE_IDX_GPCR_LSB,
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STMPE_IDX_GPCR_CSB,
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STMPE_IDX_GPCR_MSB,
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STMPE_IDX_GPDR_LSB,
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STMPE_IDX_GPDR_CSB,
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STMPE_IDX_GPDR_MSB,
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STMPE_IDX_GPEDR_LSB,
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STMPE_IDX_GPEDR_CSB,
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STMPE_IDX_GPEDR_MSB,
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STMPE_IDX_GPRER_LSB,
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STMPE_IDX_GPRER_CSB,
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STMPE_IDX_GPRER_MSB,
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STMPE_IDX_GPFER_LSB,
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STMPE_IDX_GPFER_CSB,
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STMPE_IDX_GPFER_MSB,
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STMPE_IDX_GPPUR_LSB,
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STMPE_IDX_GPPDR_LSB,
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STMPE_IDX_GPAFR_U_MSB,
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STMPE_IDX_IEGPIOR_LSB,
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STMPE_IDX_IEGPIOR_CSB,
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STMPE_IDX_IEGPIOR_MSB,
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STMPE_IDX_ISGPIOR_LSB,
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STMPE_IDX_ISGPIOR_CSB,
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STMPE_IDX_ISGPIOR_MSB,
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STMPE_IDX_MAX,
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};
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