arm64: Delay initialisation of cpuinfo_arm64::reg_{zcr,smcr}
Even if we are now able to tell the kernel to avoid exposing SVE/SME from the command line, we still have a couple of places where we unconditionally access the ZCR_EL1 (resp. SMCR_EL1) registers. On systems with broken firmwares, this results in a crash even if arm64.nosve (resp. arm64.nosme) was passed on the command-line. To avoid this, only update cpuinfo_arm64::reg_{zcr,smcr} once we have computed the sanitised version for the corresponding feature registers (ID_AA64PFR0 for SVE, and ID_AA64PFR1 for SME). This results in some minor refactoring. Reviewed-by: Mark Brown <broonie@kernel.org> Reviewed-by: Peter Collingbourne <pcc@google.com> Tested-by: Peter Collingbourne <pcc@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220720105219.1755096-1-maz@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
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@ -1001,15 +1001,24 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info)
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if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0))
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init_32bit_cpu_features(&info->aarch32);
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if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
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if (IS_ENABLED(CONFIG_ARM64_SVE) &&
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id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) {
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info->reg_zcr = read_zcr_features();
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init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
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vec_init_vq_map(ARM64_VEC_SVE);
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}
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if (id_aa64pfr1_sme(info->reg_id_aa64pfr1)) {
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if (IS_ENABLED(CONFIG_ARM64_SME) &&
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id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) {
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info->reg_smcr = read_smcr_features();
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/*
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* We mask out SMPS since even if the hardware
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* supports priorities the kernel does not at present
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* and we block access to them.
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*/
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info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS;
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init_cpu_ftr_reg(SYS_SMCR_EL1, info->reg_smcr);
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if (IS_ENABLED(CONFIG_ARM64_SME))
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vec_init_vq_map(ARM64_VEC_SME);
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vec_init_vq_map(ARM64_VEC_SME);
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}
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if (id_aa64pfr1_mte(info->reg_id_aa64pfr1))
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@ -1241,23 +1250,31 @@ void update_cpu_features(int cpu,
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taint |= check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu,
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info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0);
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if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
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if (IS_ENABLED(CONFIG_ARM64_SVE) &&
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id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) {
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info->reg_zcr = read_zcr_features();
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taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
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info->reg_zcr, boot->reg_zcr);
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/* Probe vector lengths, unless we already gave up on SVE */
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if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
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!system_capabilities_finalized())
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/* Probe vector lengths */
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if (!system_capabilities_finalized())
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vec_update_vq_map(ARM64_VEC_SVE);
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}
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if (id_aa64pfr1_sme(info->reg_id_aa64pfr1)) {
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if (IS_ENABLED(CONFIG_ARM64_SME) &&
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id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) {
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info->reg_smcr = read_smcr_features();
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/*
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* We mask out SMPS since even if the hardware
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* supports priorities the kernel does not at present
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* and we block access to them.
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*/
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info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS;
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taint |= check_update_ftr_reg(SYS_SMCR_EL1, cpu,
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info->reg_smcr, boot->reg_smcr);
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/* Probe vector lengths, unless we already gave up on SME */
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if (id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1)) &&
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!system_capabilities_finalized())
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/* Probe vector lengths */
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if (!system_capabilities_finalized())
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vec_update_vq_map(ARM64_VEC_SME);
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}
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@ -439,22 +439,6 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
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if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0))
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__cpuinfo_store_cpu_32bit(&info->aarch32);
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if (IS_ENABLED(CONFIG_ARM64_SVE) &&
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id_aa64pfr0_sve(info->reg_id_aa64pfr0))
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info->reg_zcr = read_zcr_features();
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if (IS_ENABLED(CONFIG_ARM64_SME) &&
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id_aa64pfr1_sme(info->reg_id_aa64pfr1)) {
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info->reg_smcr = read_smcr_features();
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/*
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* We mask out SMPS since even if the hardware
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* supports priorities the kernel does not at present
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* and we block access to them.
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*/
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info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS;
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}
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cpuinfo_detect_icache_policy(info);
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}
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