ARM: OMAP2: hwmod: AM43XX: Add hwmod support for HDQ-1W
These adds hwmod data for hdq/1w driver on AM43xx. Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
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@ -20,6 +20,7 @@
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#include "omap_hwmod_33xx_43xx_common_data.h"
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#include "prcm43xx.h"
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#include "omap_hwmod_common_data.h"
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#include "hdq1w.h"
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/* IP blocks */
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@ -516,6 +517,33 @@ static struct omap_hwmod am43xx_dss_rfbi_hwmod = {
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.parent_hwmod = &am43xx_dss_core_hwmod,
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};
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/* HDQ1W */
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static struct omap_hwmod_class_sysconfig am43xx_hdq1w_sysc = {
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.rev_offs = 0x0000,
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.sysc_offs = 0x0014,
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.syss_offs = 0x0018,
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.sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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static struct omap_hwmod_class am43xx_hdq1w_hwmod_class = {
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.name = "hdq1w",
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.sysc = &am43xx_hdq1w_sysc,
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.reset = &omap_hdq1w_reset,
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};
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static struct omap_hwmod am43xx_hdq1w_hwmod = {
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.name = "hdq1w",
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.class = &am43xx_hdq1w_hwmod_class,
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.clkdm_name = "l4ls_clkdm",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM43XX_CM_PER_HDQ1W_CLKCTRL_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/* Interfaces */
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static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = {
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.master = &am33xx_l3_main_hwmod,
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@ -790,6 +818,13 @@ static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_rfbi = {
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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static struct omap_hwmod_ocp_if am43xx_l4_ls__hdq1w = {
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.master = &am33xx_l4_ls_hwmod,
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.slave = &am43xx_hdq1w_hwmod,
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.clk = "l4ls_gclk",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
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&am33xx_l4_wkup__synctimer,
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&am43xx_l4_ls__timer8,
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@ -889,6 +924,7 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
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&am43xx_l4_ls__dss,
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&am43xx_l4_ls__dss_dispc,
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&am43xx_l4_ls__dss_rfbi,
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&am43xx_l4_ls__hdq1w,
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NULL,
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};
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@ -143,5 +143,6 @@
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#define AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET 0x0268
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#define AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET 0x05C0
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#define AM43XX_CM_PER_DSS_CLKCTRL_OFFSET 0x0a20
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#define AM43XX_CM_PER_HDQ1W_CLKCTRL_OFFSET 0x04a0
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#endif
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