clk: qcom: dispcc-sdm845: Adjust internal GDSC wait times
[ Upstream commit 117e7dc697c2739d754db8fe0c1e2d4f1f5d5f82 ]
SDM845 downstream uses non-default values for GDSC internal waits.
Program them accordingly to avoid surprises.
Fixes: 81351776c9
("clk: qcom: Add display clock controller driver for SDM845")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Caleb Connolly <caleb.connolly@linaro.org> # OnePlus 6
Link: https://lore.kernel.org/r/20240103-topic-845gdsc-v1-1-368efbe1a61d@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -759,6 +759,8 @@ static struct clk_branch disp_cc_mdss_vsync_clk = {
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static struct gdsc mdss_gdsc = {
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static struct gdsc mdss_gdsc = {
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.gdscr = 0x3000,
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.gdscr = 0x3000,
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.en_few_wait_val = 0x6,
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.en_rest_wait_val = 0x5,
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.pd = {
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.pd = {
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.name = "mdss_gdsc",
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.name = "mdss_gdsc",
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},
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},
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