drm/amd/display: Raise dispclk value for dce11
[Why] The visual corruption due to low display clock value. Observed on Carrizo 4K@60Hz. [How] There was earlier patch for dce_update_clocks: Adding +15% workaround also to to dce11_update_clocks Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -662,6 +662,11 @@ static void dce11_update_clocks(struct clk_mgr *clk_mgr,
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{
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struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
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struct dm_pp_power_level_change_request level_change_req;
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int patched_disp_clk = context->bw.dce.dispclk_khz;
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/*TODO: W/A for dal3 linux, investigate why this works */
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if (!clk_mgr_dce->dfs_bypass_active)
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patched_disp_clk = patched_disp_clk * 115 / 100;
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level_change_req.power_level = dce_get_required_clocks_state(clk_mgr, context);
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/* get max clock state from PPLIB */
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@ -671,9 +676,9 @@ static void dce11_update_clocks(struct clk_mgr *clk_mgr,
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clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
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}
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if (should_set_clock(safe_to_lower, context->bw.dce.dispclk_khz, clk_mgr->clks.dispclk_khz)) {
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context->bw.dce.dispclk_khz = dce_set_clock(clk_mgr, context->bw.dce.dispclk_khz);
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clk_mgr->clks.dispclk_khz = context->bw.dce.dispclk_khz;
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if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) {
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context->bw.dce.dispclk_khz = dce_set_clock(clk_mgr, patched_disp_clk);
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clk_mgr->clks.dispclk_khz = patched_disp_clk;
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}
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dce11_pplib_apply_display_requirements(clk_mgr->ctx->dc, context);
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}
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