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drm/amdgpu: Remove some useless code 

Signed-off-by: Emily.Deng <Emily.Deng@amd.com>
Reviewed-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Emily.Deng 2020-09-23 16:36:35 +08:00 committed by Alex Deucher
parent 162b786f0f
commit 884dcf3c87
4 changed files with 0 additions and 30 deletions
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5
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
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@ -153,11 +153,6 @@ static void gfxhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev)
uint64_t value;
if (!amdgpu_sriov_vf(adev)) {
/*
* the new L1 policy will block SRIOV guest from writing
* these regs, and they will be programed at host.
* so skip programing these regs.
*/
/* Disable AGP. */
WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0);
WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, 0);

5
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
View File

@ -201,11 +201,6 @@ static void mmhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev)
WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BOT, 0x00FFFFFF);
if (!amdgpu_sriov_vf(adev)) {
/*
* the new L1 policy will block SRIOV guest from writing
* these regs, and they will be programed at host.
* so skip programing these regs.
*/
/* Program the system aperture low logical page number. */
WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
adev->gmc.vram_start >> 18);

13
drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
View File

@ -83,19 +83,6 @@ struct psp_gfx_ctrl
*/
#define GFX_FLAG_RESPONSE 0x80000000
/* Gbr IH registers ID */
enum ih_reg_id {
IH_RB = 0, // IH_RB_CNTL
IH_RB_RNG1 = 1, // IH_RB_CNTL_RING1
IH_RB_RNG2 = 2, // IH_RB_CNTL_RING2
};
/* Command to setup Gibraltar IH register */
struct psp_gfx_cmd_gbr_ih_reg {
uint32_t reg_value; /* Value to be set to the IH_RB_CNTL... register*/
enum ih_reg_id reg_id; /* ID of the register */
};
/* TEE Gfx Command IDs for the ring buffer interface. */
enum psp_gfx_cmd_id
{

7
drivers/gpu/drm/amd/pm/powerplay/smumgr/smu9_smumgr.c
View File

@ -61,9 +61,6 @@ static uint32_t smu9_wait_for_response(struct pp_hwmgr *hwmgr)
uint32_t reg;
uint32_t ret;
/* Due to the L1 policy problem under SRIOV, we have to use
* mmMP1_SMN_C2PMSG_103 as the driver response register
*/
if (hwmgr->pp_one_vf) {
reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_103);
@ -148,10 +145,6 @@ int smu9_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
smu9_wait_for_response(hwmgr);
/* Due to the L1 policy problem under SRIOV, we have to use
* mmMP1_SMN_C2PMSG_101 as the driver message register and
* mmMP1_SMN_C2PMSG_102 as the driver parameter register.
*/
if (hwmgr->pp_one_vf) {
WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_103, 0);
WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_102, parameter);