soc: fsl: qe: simplify qe_ic_init()
qe_ic_init() takes a flags parameter, but all callers (including the sole remaining one) have always passed 0. So remove that parameter and simplify the body accordingly. We still explicitly initialize the Interrupt Configuration Register (CICR) to its reset value of all-zeroes, just in case the bootloader has played funny games. Reviewed-by: Timur Tabi <timur@kernel.org> Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk> Signed-off-by: Li Yang <leoyang.li@nxp.com>
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@ -356,13 +356,13 @@ static void qe_ic_cascade_muxed_mpic(struct irq_desc *desc)
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chip->irq_eoi(&desc->irq_data);
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}
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static void __init qe_ic_init(struct device_node *node, unsigned int flags)
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static void __init qe_ic_init(struct device_node *node)
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{
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void (*low_handler)(struct irq_desc *desc);
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void (*high_handler)(struct irq_desc *desc);
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struct qe_ic *qe_ic;
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struct resource res;
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u32 temp = 0, ret;
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u32 ret;
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ret = of_address_to_resource(node, 0, &res);
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if (ret)
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@ -399,26 +399,7 @@ static void __init qe_ic_init(struct device_node *node, unsigned int flags)
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high_handler = NULL;
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}
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/* default priority scheme is grouped. If spread mode is */
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/* required, configure cicr accordingly. */
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if (flags & QE_IC_SPREADMODE_GRP_W)
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temp |= CICR_GWCC;
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if (flags & QE_IC_SPREADMODE_GRP_X)
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temp |= CICR_GXCC;
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if (flags & QE_IC_SPREADMODE_GRP_Y)
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temp |= CICR_GYCC;
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if (flags & QE_IC_SPREADMODE_GRP_Z)
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temp |= CICR_GZCC;
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if (flags & QE_IC_SPREADMODE_GRP_RISCA)
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temp |= CICR_GRTA;
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if (flags & QE_IC_SPREADMODE_GRP_RISCB)
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temp |= CICR_GRTB;
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/* choose destination signal for highest priority interrupt */
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if (flags & QE_IC_HIGH_SIGNAL)
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temp |= (SIGNAL_HIGH << CICR_HPIT_SHIFT);
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qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
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qe_ic_write(qe_ic->regs, QEIC_CICR, 0);
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irq_set_handler_data(qe_ic->virq_low, qe_ic);
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irq_set_chained_handler(qe_ic->virq_low, low_handler);
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@ -439,7 +420,7 @@ static int __init qe_ic_of_init(void)
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if (!np)
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return -ENODEV;
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}
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qe_ic_init(np, 0);
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qe_ic_init(np);
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of_node_put(np);
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return 0;
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}
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