drm/i915/guc: Stop using fence/status from CTB descriptor
Stop using fence/status from CTB descriptor as future GuC ABI will no longer support replies over CTB descriptor. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20210603051630.2635-8-matthew.brost@intel.com
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@ -71,8 +71,8 @@ struct guc_ct_buffer_desc {
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u32 head; /* offset updated by GuC*/
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u32 tail; /* offset updated by owner */
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u32 is_in_error; /* error indicator */
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u32 fence; /* fence updated by GuC */
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u32 status; /* status updated by GuC */
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u32 reserved1;
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u32 reserved2;
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u32 owner; /* id of the channel owner */
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u32 owner_sub_id; /* owner-defined field for extra tracking */
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u32 reserved[5];
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@ -90,13 +90,6 @@ static void guc_ct_buffer_desc_init(struct guc_ct_buffer_desc *desc,
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desc->owner = CTB_OWNER_HOST;
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}
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static void guc_ct_buffer_desc_reset(struct guc_ct_buffer_desc *desc)
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{
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desc->head = 0;
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desc->tail = 0;
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desc->is_in_error = 0;
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}
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static int guc_action_register_ct_buffer(struct intel_guc *guc,
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u32 desc_addr,
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u32 type)
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@ -315,8 +308,7 @@ static u32 ct_get_next_fence(struct intel_guc_ct *ct)
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static int ct_write(struct intel_guc_ct *ct,
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const u32 *action,
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u32 len /* in dwords */,
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u32 fence,
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bool want_response)
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u32 fence)
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{
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struct intel_guc_ct_buffer *ctb = &ct->ctbs[CTB_SEND];
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struct guc_ct_buffer_desc *desc = ctb->desc;
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@ -360,8 +352,7 @@ static int ct_write(struct intel_guc_ct *ct,
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* DW2+: action data
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*/
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header = (len << GUC_CT_MSG_LEN_SHIFT) |
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(GUC_CT_MSG_WRITE_FENCE_TO_DESC) |
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(want_response ? GUC_CT_MSG_SEND_STATUS : 0) |
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GUC_CT_MSG_SEND_STATUS |
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(action[0] << GUC_CT_MSG_ACTION_SHIFT);
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CT_DEBUG(ct, "writing %*ph %*ph %*ph\n",
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@ -390,56 +381,6 @@ corrupted:
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return -EPIPE;
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}
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/**
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* wait_for_ctb_desc_update - Wait for the CT buffer descriptor update.
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* @desc: buffer descriptor
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* @fence: response fence
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* @status: placeholder for status
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*
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* Guc will update CT buffer descriptor with new fence and status
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* after processing the command identified by the fence. Wait for
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* specified fence and then read from the descriptor status of the
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* command.
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*
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* Return:
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* * 0 response received (status is valid)
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* * -ETIMEDOUT no response within hardcoded timeout
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* * -EPROTO no response, CT buffer is in error
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*/
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static int wait_for_ctb_desc_update(struct guc_ct_buffer_desc *desc,
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u32 fence,
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u32 *status)
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{
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int err;
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/*
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* Fast commands should complete in less than 10us, so sample quickly
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* up to that length of time, then switch to a slower sleep-wait loop.
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* No GuC command should ever take longer than 10ms.
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*/
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#define done (READ_ONCE(desc->fence) == fence)
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err = wait_for_us(done, 10);
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if (err)
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err = wait_for(done, 10);
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#undef done
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if (unlikely(err)) {
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DRM_ERROR("CT: fence %u failed; reported fence=%u\n",
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fence, desc->fence);
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if (WARN_ON(desc->is_in_error)) {
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/* Something went wrong with the messaging, try to reset
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* the buffer and hope for the best
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*/
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guc_ct_buffer_desc_reset(desc);
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err = -EPROTO;
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}
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}
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*status = desc->status;
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return err;
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}
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/**
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* wait_for_ct_request_update - Wait for CT request state update.
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* @req: pointer to pending request
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@ -483,8 +424,6 @@ static int ct_send(struct intel_guc_ct *ct,
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u32 response_buf_size,
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u32 *status)
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{
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struct intel_guc_ct_buffer *ctb = &ct->ctbs[CTB_SEND];
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struct guc_ct_buffer_desc *desc = ctb->desc;
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struct ct_request request;
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unsigned long flags;
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u32 fence;
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@ -505,16 +444,13 @@ static int ct_send(struct intel_guc_ct *ct,
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list_add_tail(&request.link, &ct->requests.pending);
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spin_unlock_irqrestore(&ct->requests.lock, flags);
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err = ct_write(ct, action, len, fence, !!response_buf);
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err = ct_write(ct, action, len, fence);
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if (unlikely(err))
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goto unlink;
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intel_guc_notify(ct_to_guc(ct));
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if (response_buf)
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err = wait_for_ct_request_update(&request, status);
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else
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err = wait_for_ctb_desc_update(desc, fence, status);
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err = wait_for_ct_request_update(&request, status);
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if (unlikely(err))
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goto unlink;
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