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i.MX arm64 device tree update for 5.6: 

- New board support: i.MX8MQ based Thor96 board, Google i.MX8MQ Phanbell
    board, LX2160A based Solidrun Clearfog CX and Honeycomb boards.
  - Add eLCDIF controller and missing SAI nodes for i.MX8MQ SoC.
  - Add Crypto CAAM support for i.MX8MM and i.MX8MN.
  - Drop unneeded "simple-bus" from anatop node on i.MX8MM and i.MX8MN.
  - Drop unused/undocumented "fsl,aips-bus" and "fsl,imx8mq-aips-bus"
    compatibles from i.MX8M SoCs.
  - Add DDR controller nodes for i.MX8M devices.
  - Add EEPROM description for imx8mq-hummingboard-pulse and
    imx8mq-sr-som boards.
  - Enable USB1 and TypeC support for imx8mn-evk board.
  - Add FlexSPI and QSPI support for a few Layerscape SoCs and boards.
  - Add External MDIO1 node and the two RGMII PHYs connected on LX2160A.
  - Add missing SAI devices and set SAIs into async mode on LS1028A.
  - Other random device additions and enhancement for various platforms.
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Merge tag 'imx-dt64-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt

i.MX arm64 device tree update for 5.6:

 - New board support: i.MX8MQ based Thor96 board, Google i.MX8MQ Phanbell
   board, LX2160A based Solidrun Clearfog CX and Honeycomb boards.
 - Add eLCDIF controller and missing SAI nodes for i.MX8MQ SoC.
 - Add Crypto CAAM support for i.MX8MM and i.MX8MN.
 - Drop unneeded "simple-bus" from anatop node on i.MX8MM and i.MX8MN.
 - Drop unused/undocumented "fsl,aips-bus" and "fsl,imx8mq-aips-bus"
   compatibles from i.MX8M SoCs.
 - Add DDR controller nodes for i.MX8M devices.
 - Add EEPROM description for imx8mq-hummingboard-pulse and
   imx8mq-sr-som boards.
 - Enable USB1 and TypeC support for imx8mn-evk board.
 - Add FlexSPI and QSPI support for a few Layerscape SoCs and boards.
 - Add External MDIO1 node and the two RGMII PHYs connected on LX2160A.
 - Add missing SAI devices and set SAIs into async mode on LS1028A.
 - Other random device additions and enhancement for various platforms.

* tag 'imx-dt64-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (35 commits)
  arm64: dts: imx8mn: Memory node should be in board DT
  arm64: dts: imx8mm: Memory node should be in board DT
  arm64: dts: imx8mn: add crypto node
  arm64: dts: imx8mq-hummingboard-pulse: add eeprom description
  arm64: dts: imx8mq-sr-som: add eeprom description
  arm64: dts: ls208xa: Update qspi node properties for LS2088ARDB
  arm64: dts: freescale: Add devicetree support for Thor96 board
  arm64: dts: imx8mq-librem5-devkit: add accelerometer and gyro sensor
  arm64: dts: imx8mm: Add Crypto CAAM support
  arm64: dts: freescale: add initial support for Google i.MX 8MQ Phanbell
  arm64: dts: ls1028a-rdb: enable emmc hs400 mode
  arm64: dts: ls1028a: Update edma compatible to fit eDMA driver
  arm64: dts: imx8m: drop "fsl,aips-bus" and "fsl,imx8mq-aips-bus"
  arm64: dts: imx8mm: Add missing mux options for UART1 and UART2 signals
  arm64: dts: lx2160a: add dts for CEX7 platforms
  arm64: dts: lx2160a: add emdio2 node
  arm64: dts: ls1028a: put SAIs into async mode
  arm64: dts: ls1028a: add missing sai nodes
  arm64: dts: imx8mn-evk: enable usb1 and typec support
  arm64: dts: imx8mn: Remove setting for IMX8MN_CLK_USB_CORE_REF
  ...

Link: https://lore.kernel.org/r/20200113034006.17430-5-shawnguo@kernel.org
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2020-01-16 10:49:26 -08:00
parent 78c47feaff c16b4571bb
commit 87f846c773
33 changed files with 1787 additions and 55 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm64/boot/dts/freescale/Makefile
View File

@ -18,6 +18,8 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-clearfog-cx.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-honeycomb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
@ -28,7 +30,9 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-hummingboard-pulse.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-nitrogen.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-phanbell.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-pico-pi.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-thor96.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb

15
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
View File

@ -123,6 +123,21 @@
status = "okay";
};
&fspi {
status = "okay";
mt35xu02g0: flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <50000000>;
/* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
spi-rx-bus-width = <8>; /* 8 SPI Rx lines */
spi-tx-bus-width = <1>; /* 1 SPI Tx line */
reg = <0>;
};
};
&i2c0 {
status = "okay";

17
arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
View File

@ -93,9 +93,26 @@
&esdhc1 {
mmc-hs200-1_8v;
mmc-hs400-1_8v;
bus-width = <8>;
status = "okay";
};
&fspi {
status = "okay";
mt35xu02g0: flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <50000000>;
/* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
spi-rx-bus-width = <8>; /* 8 SPI Rx lines */
spi-tx-bus-width = <1>; /* 1 SPI Tx line */
reg = <0>;
};
};
&i2c0 {
status = "okay";

63
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
View File

@ -271,6 +271,19 @@
status = "disabled";
};
fspi: spi@20c0000 {
compatible = "nxp,lx2160a-fspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x20c0000 0x0 0x10000>,
<0x0 0x20000000 0x0 0x10000000>;
reg-names = "fspi_base", "fspi_mmap";
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
clock-names = "fspi_en", "fspi";
status = "disabled";
};
esdhc: mmc@2140000 {
compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
reg = <0x0 0x2140000 0x0 0x10000>;
@ -316,7 +329,7 @@
edma0: dma-controller@22c0000 {
#dma-cells = <2>;
compatible = "fsl,vf610-edma";
compatible = "fsl,ls1028a-edma";
reg = <0x0 0x22c0000 0x0 0x10000>,
<0x0 0x22d0000 0x0 0x10000>,
<0x0 0x22e0000 0x0 0x10000>;
@ -528,6 +541,7 @@
dma-names = "tx", "rx";
dmas = <&edma0 1 4>,
<&edma0 1 3>;
fsl,sai-asynchronous;
status = "disabled";
};
@ -542,6 +556,22 @@
dma-names = "tx", "rx";
dmas = <&edma0 1 6>,
<&edma0 1 5>;
fsl,sai-asynchronous;
status = "disabled";
};
sai3: audio-controller@f120000 {
#sound-dai-cells = <0>;
compatible = "fsl,vf610-sai";
reg = <0x0 0xf120000 0x0 0x10000>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>, <&clockgen 4 1>,
<&clockgen 4 1>, <&clockgen 4 1>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
dma-names = "tx", "rx";
dmas = <&edma0 1 8>,
<&edma0 1 7>;
fsl,sai-asynchronous;
status = "disabled";
};
@ -556,6 +586,37 @@
dma-names = "tx", "rx";
dmas = <&edma0 1 10>,
<&edma0 1 9>;
fsl,sai-asynchronous;
status = "disabled";
};
sai5: audio-controller@f140000 {
#sound-dai-cells = <0>;
compatible = "fsl,vf610-sai";
reg = <0x0 0xf140000 0x0 0x10000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>, <&clockgen 4 1>,
<&clockgen 4 1>, <&clockgen 4 1>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
dma-names = "tx", "rx";
dmas = <&edma0 1 12>,
<&edma0 1 11>;
fsl,sai-asynchronous;
status = "disabled";
};
sai6: audio-controller@f150000 {
#sound-dai-cells = <0>;
compatible = "fsl,vf610-sai";
reg = <0x0 0xf150000 0x0 0x10000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>, <&clockgen 4 1>,
<&clockgen 4 1>, <&clockgen 4 1>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
dma-names = "tx", "rx";
dmas = <&edma0 1 14>,
<&edma0 1 13>;
fsl,sai-asynchronous;
status = "disabled";
};

14
arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.dts
View File

@ -112,6 +112,20 @@
};
&qspi {
status = "okay";
mt25qu512a0: flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <50000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
reg = <0>;
};
};
#include "fsl-ls1046-post.dtsi"
&fman0 {

16
arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
View File

@ -101,23 +101,23 @@
&qspi {
status = "okay";
qflash0: flash@0 {
compatible = "spansion,m25p80";
s25fs512s0: flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <20000000>;
spi-max-frequency = <50000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
spi-tx-bus-width = <1>;
reg = <0>;
};
qflash1: flash@1 {
compatible = "spansion,m25p80";
s25fs512s1: flash@1 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <20000000>;
spi-max-frequency = <50000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
spi-tx-bus-width = <1>;
reg = <1>;
};
};

24
arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
View File

@ -143,6 +143,30 @@
status = "okay";
};
&qspi {
status = "okay";
s25fs512s0: flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <50000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
reg = <0>;
};
s25fs512s1: flash@1 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <50000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
reg = <1>;
};
};
&sata {
status = "okay";
};

24
arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
View File

@ -86,6 +86,30 @@
status = "okay";
};
&qspi {
status = "okay";
s25fs512s0: flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <50000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
reg = <0>;
};
s25fs512s1: flash@1 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <50000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
reg = <1>;
};
};
&sata {
status = "okay";
};

13
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
View File

@ -375,6 +375,19 @@
status = "disabled";
};
qspi: spi@20c0000 {
compatible = "fsl,ls2080a-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x20c0000 0x0 0x10000>,
<0x0 0x20000000 0x0 0x10000000>;
reg-names = "QuadSPI", "QuadSPI-memory";
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "qspi_en", "qspi";
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
status = "disabled";
};
esdhc: esdhc@2140000 {
compatible = "fsl,ls1088a-esdhc", "fsl,esdhc";
reg = <0x0 0x2140000 0x0 0x10000>;

10
arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
View File

@ -108,7 +108,15 @@
};
&qspi {
status = "disabled";
status = "okay";
s25fs512s0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <0>;
};
};
&sata0 {

6
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
View File

@ -618,16 +618,16 @@
};
qspi: spi@20c0000 {
status = "disabled";
compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
compatible = "fsl,ls2080a-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x20c0000 0x0 0x10000>,
<0x0 0x20000000 0x0 0x10000000>;
reg-names = "QuadSPI", "QuadSPI-memory";
interrupts = <0 25 0x4>; /* Level high type */
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
clock-names = "qspi_en", "qspi";
status = "disabled";
};
pcie1: pcie@3400000 {

127
arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi Normal file
View File

@ -0,0 +1,127 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Device Tree file for LX2160A-CEx7
//
// Copyright 2019 SolidRun Ltd.
/dts-v1/;
#include "fsl-lx2160a.dtsi"
/ {
model = "SolidRun LX2160A COM Express Type 7 module";
compatible = "solidrun,lx2160a-cex7", "fsl,lx2160a";
aliases {
crypto = &crypto;
};
sb_3v3: regulator-sb3v3 {
compatible = "regulator-fixed";
regulator-name = "RT7290";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
&crypto {
status = "okay";
};
&dpmac17 {
phy-handle = <&rgmii_phy1>;
phy-connection-type = "rgmii-id";
};
&emdio1 {
status = "okay";
rgmii_phy1: ethernet-phy@1 {
reg = <1>;
};
};
&esdhc1 {
mmc-hs200-1_8v;
mmc-hs400-1_8v;
bus-width = <8>;
status = "okay";
};
&i2c0 {
status = "okay";
i2c-switch@77 {
compatible = "nxp,pca9547";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x77>;
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
fan-temperature-ctrlr@18 {
compatible = "ti,amc6821";
reg = <0x18>;
cooling-min-state = <0>;
cooling-max-state = <9>;
#cooling-cells = <2>;
};
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
temperature-sensor@48 {
compatible = "nxp,sa56004";
reg = <0x48>;
vcc-supply = <&sb_3v3>;
};
};
};
};
&i2c2 {
status = "okay";
};
&i2c4 {
status = "okay";
rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
// IRQ10_B
interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
};
};
&fspi {
status = "okay";
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,m25p80";
m25p,fast-read;
spi-max-frequency = <50000000>;
reg = <0>;
/* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
spi-rx-bus-width = <8>;
spi-tx-bus-width = <1>;
};
};
&usb0 {
status = "okay";
};
&usb1 {
status = "okay";
};

15
arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-cx.dts Normal file
View File

@ -0,0 +1,15 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Device Tree file for LX2160A Clearfog CX board
//
// Copyright 2019 SolidRun Ltd.
/dts-v1/;
#include "fsl-lx2160a-clearfog-itx.dtsi"
/ {
model = "SolidRun LX2160A Clearfog CX";
compatible = "solidrun,clearfog-cx",
"solidrun,lx2160a-cex7", "fsl,lx2160a";
};

57
arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi Normal file
View File

@ -0,0 +1,57 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Device Tree file for LX2160A Clearfog ITX board; this contains the
// common parts shared between the Clearfog CX and Honeycomb builds.
//
// Copyright 2019 SolidRun Ltd.
/dts-v1/;
#include "fsl-lx2160a-cex7.dtsi"
/ {
aliases {
serial0 = &uart0;
serial1 = &uart1;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&emdio2 {
status = "okay";
};
&esdhc0 {
sd-uhs-sdr104;
sd-uhs-sdr50;
sd-uhs-sdr25;
sd-uhs-sdr12;
status = "okay";
};
&sata0 {
status = "okay";
};
&sata1 {
status = "okay";
};
&sata2 {
status = "okay";
};
&sata3 {
status = "okay";
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};

15
arch/arm64/boot/dts/freescale/fsl-lx2160a-honeycomb.dts Normal file
View File

@ -0,0 +1,15 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Device Tree file for LX2160A Honeycomb board
//
// Copyright 2019 SolidRun Ltd.
/dts-v1/;
#include "fsl-lx2160a-clearfog-itx.dtsi"
/ {
model = "SolidRun LX2160A Honeycomb";
compatible = "solidrun,honeycomb",
"solidrun,lx2160a-cex7", "fsl,lx2160a";
};

28
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
View File

@ -35,6 +35,34 @@
status = "okay";
};
&dpmac17 {
phy-handle = <&rgmii_phy1>;
phy-connection-type = "rgmii-id";
};
&dpmac18 {
phy-handle = <&rgmii_phy2>;
phy-connection-type = "rgmii-id";
};
&emdio1 {
status = "okay";
rgmii_phy1: ethernet-phy@1 {
/* AR8035 PHY */
compatible = "ethernet-phy-id004d.d072";
reg = <0x1>;
eee-broken-1000t;
};
rgmii_phy2: ethernet-phy@2 {
/* AR8035 PHY */
compatible = "ethernet-phy-id004d.d072";
reg = <0x2>;
eee-broken-1000t;
};
};
&esdhc0 {
sd-uhs-sdr104;
sd-uhs-sdr50;

21
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
View File

@ -939,6 +939,27 @@
fsl,extts-fifo;
};
/* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */
emdio1: mdio@8b96000 {
compatible = "fsl,fman-memac-mdio";
reg = <0x0 0x8b96000 0x0 0x1000>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
little-endian;
status = "disabled";
};
emdio2: mdio@8b97000 {
compatible = "fsl,fman-memac-mdio";
reg = <0x0 0x8b97000 0x0 0x1000>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
little-endian;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
fsl_mc: fsl-mc@80c000000 {
compatible = "fsl,qoriq-mc";
reg = <0x00000008 0x0c000000 0 0x40>,

25
arch/arm64/boot/dts/freescale/imx8mm-evk.dts
View File

@ -16,6 +16,11 @@
stdout-path = &uart2;
};
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0x80000000>;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@ -77,6 +82,26 @@
cpu-supply = <&buck2_reg>;
};
&ddrc {
operating-points-v2 = <&ddrc_opp_table>;
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-25M {
opp-hz = /bits/ 64 <25000000>;
};
opp-100M {
opp-hz = /bits/ 64 <100000000>;
};
opp-750M {
opp-hz = /bits/ 64 <750000000>;
};
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;

16
arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h
View File

@ -430,18 +430,26 @@
#define MX8MM_IOMUXC_SAI1_MCLK_SIM_M_HRESP 0x1AC 0x414 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x1B0 0x418 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x1B0 0x418 0x4EC 0x1 0x2
#define MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x1B0 0x418 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI2_RXFS_UART1_DTE_RX 0x1B0 0x418 0x4F4 0x4 0x2
#define MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x1B0 0x418 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0 0x1B0 0x418 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x1B4 0x41C 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x1B4 0x41C 0x4E8 0x1 0x2
#define MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x1B4 0x41C 0x4F4 0x4 0x3
#define MX8MM_IOMUXC_SAI2_RXC_UART1_DTE_TX 0x1B4 0x41C 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1B4 0x41C 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI2_RXC_SIM_M_HSIZE1 0x1B4 0x41C 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x1B8 0x420 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x1B8 0x420 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x1B8 0x420 0x4F0 0x4 0x2
#define MX8MM_IOMUXC_SAI2_RXD0_UART1_DTE_CTS_B 0x1B8 0x420 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x1B8 0x420 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2 0x1B8 0x420 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x1BC 0x424 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x1BC 0x424 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x1BC 0x424 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI2_TXFS_UART1_DTE_RTS_B 0x1BC 0x424 0x4F0 0x4 0x3
#define MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x1BC 0x424 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI2_TXFS_SIM_M_HWRITE 0x1BC 0x424 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x1C0 0x428 0x000 0x0 0x0
@ -464,21 +472,29 @@
#define MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI3_RXC_GPT1_CLK 0x1D0 0x438 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2
#define MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x1D0 0x438 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x1D0 0x438 0x4F8 0x4 0x2
#define MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI3_RXC_TPSMP_HTRANS1 0x1D0 0x438 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x1D4 0x43C 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x1D4 0x43C 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x1D4 0x43C 0x4D4 0x2 0x2
#define MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x1D4 0x43C 0x4F8 0x4 0x3
#define MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x1D4 0x43C 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI3_RXD_TPSMP_HDATA0 0x1D4 0x43C 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x1D8 0x440 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2
#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x1D8 0x440 0x4Fc 0x4 0x2
#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x1D8 0x440 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x1DC 0x444 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x2
#define MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x1DC 0x444 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x1DC 0x444 0x4Fc 0x4 0x3
#define MX8MM_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI3_TXC_TPSMP_HDATA2 0x1DC 0x444 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0

55
arch/arm64/boot/dts/freescale/imx8mm.dtsi
View File

@ -140,11 +140,6 @@
};
};
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0x80000000>;
};
osc_32k: clock-osc-32k {
compatible = "fixed-clock";
#clock-cells = <0>;
@ -232,7 +227,7 @@
ranges = <0x0 0x0 0x0 0x3e000000>;
aips1: bus@30000000 {
compatible = "fsl,aips-bus", "simple-bus";
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x30000000 0x30000000 0x400000>;
@ -438,7 +433,7 @@
};
anatop: anatop@30360000 {
compatible = "fsl,imx8mm-anatop", "syscon", "simple-bus";
compatible = "fsl,imx8mm-anatop", "syscon";
reg = <0x30360000 0x10000>;
};
@ -501,7 +496,7 @@
};
aips2: bus@30400000 {
compatible = "fsl,aips-bus", "simple-bus";
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x30400000 0x30400000 0x400000>;
@ -560,7 +555,7 @@
};
aips3: bus@30800000 {
compatible = "fsl,aips-bus", "simple-bus";
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x30800000 0x30800000 0x400000>;
@ -641,6 +636,36 @@
status = "disabled";
};
crypto: crypto@30900000 {
compatible = "fsl,sec-v4.0";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x30900000 0x40000>;
ranges = <0 0x30900000 0x40000>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_AHB>,
<&clk IMX8MM_CLK_IPG_ROOT>;
clock-names = "aclk", "ipg";
sec_jr0: jr@1000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr1: jr@2000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x2000 0x1000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr2: jr@3000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x3000 0x1000>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
};
};
i2c1: i2c@30a20000 {
compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
#address-cells = <1>;
@ -775,7 +800,7 @@
};
aips4: bus@32c00000 {
compatible = "fsl,aips-bus", "simple-bus";
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x32c00000 0x32c00000 0x400000>;
@ -858,6 +883,16 @@
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
ddrc: memory-controller@3d400000 {
compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
reg = <0x3d400000 0x400000>;
clock-names = "core", "pll", "alt", "apb";
clocks = <&clk IMX8MM_CLK_DRAM_CORE>,
<&clk IMX8MM_DRAM_PLL>,
<&clk IMX8MM_CLK_DRAM_ALT>,
<&clk IMX8MM_CLK_DRAM_APB>;
};
ddr-pmu@3d800000 {
compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu";
reg = <0x3d800000 0x400000>;

20
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
View File

@ -17,6 +17,26 @@
cpu-supply = <&buck2_reg>;
};
&ddrc {
operating-points-v2 = <&ddrc_opp_table>;
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-25M {
opp-hz = /bits/ 64 <25000000>;
};
opp-100M {
opp-hz = /bits/ 64 <100000000>;
};
opp-600M {
opp-hz = /bits/ 64 <600000000>;
};
};
};
&i2c1 {
pmic@4b {
compatible = "rohm,bd71847";

70
arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
View File

@ -3,6 +3,7 @@
* Copyright 2019 NXP
*/
#include <dt-bindings/usb/pd.h>
#include "imx8mn.dtsi"
/ {
@ -22,6 +23,11 @@
};
};
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0x80000000>;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
@ -60,6 +66,42 @@
status = "okay";
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
ptn5110: tcpc@50 {
compatible = "nxp,ptn5110";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec1>;
reg = <0x50>;
interrupt-parent = <&gpio2>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
status = "okay";
port {
typec1_dr_sw: endpoint {
remote-endpoint = <&usb1_drd_sw>;
};
};
typec1_con: connector {
compatible = "usb-c-connector";
label = "USB-C";
power-role = "dual";
data-role = "dual";
try-power-role = "sink";
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
PDO_VAR(5000, 20000, 3000)>;
op-sink-microwatt = <15000000>;
self-powered;
};
};
};
&snvs_pwrkey {
status = "okay";
};
@ -70,6 +112,21 @@
status = "okay";
};
&usbotg1 {
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
usb-role-switch;
status = "okay";
port {
usb1_drd_sw: endpoint {
remote-endpoint = <&typec1_dr_sw>;
};
};
};
&usdhc2 {
assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
assigned-clock-rates = <200000000>;
@ -138,12 +195,25 @@
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
fsl,pins = <
MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>;
};
pinctrl_typec1: typec1grp {
fsl,pins = <
MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140

61
arch/arm64/boot/dts/freescale/imx8mn.dtsi
View File

@ -139,11 +139,6 @@
};
};
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0x80000000>;
};
osc_32k: clock-osc-32k {
compatible = "fixed-clock";
#clock-cells = <0>;
@ -208,7 +203,7 @@
ranges = <0x0 0x0 0x0 0x3e000000>;
aips1: bus@30000000 {
compatible = "fsl,aips-bus", "simple-bus";
compatible = "simple-bus";
reg = <0x30000000 0x400000>;
#address-cells = <1>;
#size-cells = <1>;
@ -349,7 +344,7 @@
anatop: anatop@30360000 {
compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop",
"syscon", "simple-bus";
"syscon";
reg = <0x30360000 0x10000>;
};
@ -395,7 +390,7 @@
};
aips2: bus@30400000 {
compatible = "fsl,aips-bus", "simple-bus";
compatible = "simple-bus";
reg = <0x30400000 0x400000>;
#address-cells = <1>;
#size-cells = <1>;
@ -455,7 +450,7 @@
};
aips3: bus@30800000 {
compatible = "fsl,aips-bus", "simple-bus";
compatible = "simple-bus";
reg = <0x30800000 0x400000>;
#address-cells = <1>;
#size-cells = <1>;
@ -537,6 +532,36 @@
status = "disabled";
};
crypto: crypto@30900000 {
compatible = "fsl,sec-v4.0";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x30900000 0x40000>;
ranges = <0 0x30900000 0x40000>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_AHB>,
<&clk IMX8MN_CLK_IPG_ROOT>;
clock-names = "aclk", "ipg";
sec_jr0: jr0@1000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr1: jr1@2000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x2000 0x1000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr2: jr2@3000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x3000 0x1000>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
};
};
i2c1: i2c@30a20000 {
compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
#address-cells = <1>;
@ -671,7 +696,7 @@
};
aips4: bus@32c00000 {
compatible = "fsl,aips-bus", "simple-bus";
compatible = "simple-bus";
reg = <0x32c00000 0x400000>;
#address-cells = <1>;
#size-cells = <1>;
@ -683,10 +708,8 @@
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
clock-names = "usb1_ctrl_root_clk";
assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>,
<&clk IMX8MN_CLK_USB_CORE_REF>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>,
<&clk IMX8MN_SYS_PLL1_100M>;
assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
fsl,usbphy = <&usbphynop1>;
fsl,usbmisc = <&usbmisc1 0>;
status = "disabled";
@ -759,6 +782,16 @@
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
ddrc: memory-controller@3d400000 {
compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc";
reg = <0x3d400000 0x400000>;
clock-names = "core", "pll", "alt", "apb";
clocks = <&clk IMX8MN_CLK_DRAM_CORE>,
<&clk IMX8MN_DRAM_PLL>,
<&clk IMX8MN_CLK_DRAM_ALT>,
<&clk IMX8MN_CLK_DRAM_APB>;
};
ddr-pmu@3d800000 {
compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu";
reg = <0x3d800000 0x400000>;

27
arch/arm64/boot/dts/freescale/imx8mq-evk.dts
View File

@ -105,6 +105,33 @@
cpu-supply = <&buck2_reg>;
};
&ddrc {
operating-points-v2 = <&ddrc_opp_table>;
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-25M {
opp-hz = /bits/ 64 <25000000>;
};
opp-100M {
opp-hz = /bits/ 64 <100000000>;
};
/*
* On imx8mq B0 PLL can't be bypassed so low bus is 166M
*/
opp-166M {
opp-hz = /bits/ 64 <166935483>;
};
opp-800M {
opp-hz = /bits/ 64 <800000000>;
};
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;

6
arch/arm64/boot/dts/freescale/imx8mq-hummingboard-pulse.dts
View File

@ -84,6 +84,12 @@
clock-frequency = <100000>;
status = "okay";
eeprom@57 {
compatible = "atmel,24c02";
reg = <0x57>;
status = "okay";
};
rtc@69 {
compatible = "abracon,ab1805";
reg = <0x69>;

7
arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
View File

@ -440,6 +440,13 @@
AVDD28-supply = <&reg_2v8_p>;
VDDIO-supply = <&reg_1v8_p>;
};
accel-gyro@6a {
compatible = "st,lsm9ds1-imu";
reg = <0x6a>;
vdd-supply = <&reg_3v3_p>;
vddio-supply = <&reg_3v3_p>;
};
};
&iomuxc {

376
arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts Normal file
View File

@ -0,0 +1,376 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2017-2019 NXP
*/
/dts-v1/;
#include "imx8mq.dtsi"
/ {
model = "Google i.MX8MQ Phanbell";
compatible = "google,imx8mq-phanbell", "fsl,imx8mq";
chosen {
stdout-path = &uart1;
};
memory@40000000 {
device_type = "memory";
reg = <0x00000000 0x40000000 0 0x40000000>;
};
pmic_osc: clock-pmic {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "pmic_osc";
};
reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
compatible = "regulator-fixed";
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&A53_0 {
cpu-supply = <&buck2>;
};
&A53_1 {
cpu-supply = <&buck2>;
};
&A53_2 {
cpu-supply = <&buck2>;
};
&A53_3 {
cpu-supply = <&buck2>;
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic: pmic@4b {
compatible = "rohm,bd71837";
reg = <0x4b>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
#clock-cells = <0>;
clocks = <&pmic_osc>;
clock-output-names = "pmic_clk";
interrupt-parent = <&gpio1>;
interrupts = <3 GPIO_ACTIVE_LOW>;
regulators {
buck1: BUCK1 {
regulator-name = "buck1";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <1250>;
rohm,dvs-run-voltage = <900000>;
rohm,dvs-idle-voltage = <900000>;
rohm,dvs-suspend-voltage = <800000>;
};
buck2: BUCK2 {
regulator-name = "buck2";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1000000>;
regulator-boot-on;
regulator-always-on;
rohm,dvs-run-voltage = <1000000>;
rohm,dvs-idle-voltage = <900000>;
};
buck3: BUCK3 {
regulator-name = "buck3";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
rohm,dvs-run-voltage = <900000>;
};
buck4: BUCK4 {
regulator-name = "buck4";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-always-on;
rohm,dvs-run-voltage = <900000>;
};
buck5: BUCK5 {
regulator-name = "buck5";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1350000>;
regulator-boot-on;
regulator-always-on;
};
buck6: BUCK6 {
regulator-name = "buck6";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
buck7: BUCK7 {
regulator-name = "buck7";
regulator-min-microvolt = <1605000>;
regulator-max-microvolt = <1995000>;
regulator-boot-on;
regulator-always-on;
};
buck8: BUCK8 {
regulator-name = "buck8";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
regulator-boot-on;
regulator-always-on;
};
ldo1: LDO1 {
regulator-name = "ldo1";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo2: LDO2 {
regulator-name = "ldo2";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;
};
ldo3: LDO3 {
regulator-name = "ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo4: LDO4 {
regulator-name = "ldo4";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo5: LDO5 {
regulator-name = "ldo5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo6: LDO6 {
regulator-name = "ldo6";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo7: LDO7 {
regulator-name = "ldo7";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
bus-width = <4>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&usb3_phy0 {
status = "okay";
};
&usb_dwc3_0 {
dr_mode = "otg";
status = "okay";
};
&usb3_phy1 {
status = "okay";
};
&usb_dwc3_1 {
dr_mode = "host";
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
>;
};
pinctrl_pmic: pmicirq {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc2_gpio: usdhc2grpgpio {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};

6
arch/arm64/boot/dts/freescale/imx8mq-sr-som.dtsi
View File

@ -125,6 +125,12 @@
};
};
};
eeprom@50 {
compatible = "atmel,24c01";
reg = <0x50>;
status = "okay";
};
};
&pgc_gpu{

581
arch/arm64/boot/dts/freescale/imx8mq-thor96.dts Normal file
View File

@ -0,0 +1,581 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019 Einfochips
* Copyright 2019 Linaro Ltd.
*/
/dts-v1/;
#include "imx8mq.dtsi"
/ {
model = "Einfochips i.MX8MQ Thor96";
compatible = "einfochips,imx8mq-thor96", "fsl,imx8mq";
chosen {
stdout-path = &uart1;
};
memory@40000000 {
device_type = "memory";
reg = <0x00000000 0x40000000 0 0x80000000>;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_leds>;
user-led1 {
label = "green:user1";
gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
user-led2 {
label = "green:user2";
gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "none";
};
user-led3 {
label = "green:user3";
gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc1";
default-state = "off";
};
user-led4 {
label = "green:user4";
gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
panic-indicator;
linux,default-trigger = "none";
};
wlan-active-led {
label = "yellow:wlan";
gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0tx";
default-state = "off";
};
bt-active-led {
label = "blue:bt";
gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "hci0-power";
default-state = "off";
};
};
reg_usdhc1_vmmc: reg-usdhc1-vmmc {
compatible = "regulator-fixed";
regulator-name = "VDD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_usdhc1_vqmmc: reg-usdhc1-vqmmc {
compatible = "regulator-fixed";
regulator-name = "VCC_1V8_EXT";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
reg_usdhc2_vmmc: reg-usdhc2-vmmc {
compatible = "regulator-fixed";
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usdhc2_vqmmc: reg-usdhc2-vqmmc {
compatible = "regulator-fixed";
regulator-name = "NVCC_SD2";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wifi_reg_on>;
gpio = <&gpio3 3 GPIO_ACTIVE_HIGH>;
};
};
/* LS-SPI0 */
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
status = "okay";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
phy-handle = <&ethphy>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <3>;
};
};
};
/* LS-I2C0 */
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic@8 {
compatible = "fsl,pfuze100";
reg = <0x8>;
regulators {
sw1a_reg: sw1ab {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
};
sw1c_reg: sw1c {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
};
sw2_reg: sw2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
sw3a_reg: sw3ab {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-always-on;
};
sw4_reg: sw4 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
swbst_reg: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
};
snvs_reg: vsnvs {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
};
vref_reg: vrefddr {
regulator-always-on;
};
vgen1_reg: vgen1 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
vgen2_reg: vgen2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
regulator-always-on;
};
vgen3_reg: vgen3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen4_reg: vgen4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen5_reg: vgen5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen6_reg: vgen6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
};
};
};
/* LS-I2C1 */
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
eeprom: eeprom@50 {
compatible = "atmel,24c256";
reg = <0x50>;
};
};
/* HS-I2C2 */
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
/* HS-I2C3 */
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
};
&pgc_gpu {
power-supply = <&sw1a_reg>;
};
&pgc_vpu {
power-supply = <&sw1c_reg>;
};
&qspi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi0>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <100000000>;
reg = <0>;
};
};
/* Debug UART */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
status = "okay";
};
/* LS-UART0 */
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
device-wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_bt_gpios>;
};
};
/* LS-UART1 */
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
assigned-clocks = <&clk IMX8MQ_CLK_UART3>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
status = "okay";
};
&usb3_phy1 {
status = "okay";
};
&usb_dwc3_1 {
dr_mode = "host";
status = "okay";
};
/* SDIO */
&usdhc1 {
#address-cells = <0x1>;
#size-cells = <0x0>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
vmmc-supply = <&reg_usdhc1_vmmc>;
vqmmc-supply = <&reg_usdhc1_vqmmc>;
mmc-pwrseq = <&sdio_pwrseq>;
bus-width = <4>;
non-removable;
no-sd;
no-emmc;
status = "okay";
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
/* uSD */
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
vmmc-supply = <&reg_usdhc2_vmmc>;
vqmmc-supply = <&reg_usdhc2_vqmmc>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
bus-width = <4>;
no-sdio;
no-emmc;
disable-wp;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_bt_gpios: btgpiosgrp {
fsl,pins = <
MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19
MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x19
MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19
>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x16
MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x16
MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x16
MX8MQ_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x16
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x4
MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x24
MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1c
MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1c
MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1c
MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1c
MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1c
MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1c
MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f
MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f
MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f
>;
};
pinctrl_leds: ledsgrp {
fsl,pins = <
MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x19
MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19
MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19
MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19
MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x19
>;
};
pinctrl_qspi0: qspi0grp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
>;
};
pinctrl_reg_usdhc2: regusdhc2grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49
MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49
MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x85
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x85
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x85
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8c
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcc
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcc
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcc
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcc
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcc
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9c
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdc
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdc
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdc
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdc
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdc
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xcc
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
pinctrl_wifi_reg_on: wifiregongrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x17059
>;
};
};

2
arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts
View File

@ -8,7 +8,7 @@
#include "imx8mq-zii-ultra.dtsi"
/ {
model = "ZII i.MX8MQ Ultra RMB3 Board";
model = "ZII Ultra RMB3 Board";
compatible = "zii,imx8mq-ultra-rmb3", "zii,imx8mq-ultra", "fsl,imx8mq";
};

2
arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-zest.dts
View File

@ -8,7 +8,7 @@
#include "imx8mq-zii-ultra.dtsi"
/ {
model = "ZII i.MX8MQ Ultra Zest Board";
model = "ZII Ultra Zest Board";
compatible = "zii,imx8mq-ultra-zest", "zii,imx8mq-ultra", "fsl,imx8mq";
};

107
arch/arm64/boot/dts/freescale/imx8mq.dtsi
View File

@ -290,11 +290,67 @@
dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
bus@30000000 { /* AIPS1 */
compatible = "fsl,imx8mq-aips-bus", "simple-bus";
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x30000000 0x30000000 0x400000>;
sai1: sai@30010000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx8mq-sai";
reg = <0x30010000 0x10000>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_SAI1_IPG>,
<&clk IMX8MQ_CLK_SAI1_ROOT>,
<&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
dmas = <&sdma2 8 24 0>, <&sdma1 9 24 0>;
dma-names = "rx", "tx";
status = "disabled";
};
sai6: sai@30030000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx8mq-sai";
reg = <0x30030000 0x10000>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_SAI6_IPG>,
<&clk IMX8MQ_CLK_SAI6_ROOT>,
<&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
dmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>;
dma-names = "rx", "tx";
status = "disabled";
};
sai5: sai@30040000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx8mq-sai";
reg = <0x30040000 0x10000>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_SAI5_IPG>,
<&clk IMX8MQ_CLK_SAI5_ROOT>,
<&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
dmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>;
dma-names = "rx", "tx";
status = "disabled";
};
sai4: sai@30050000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx8mq-sai";
reg = <0x30050000 0x10000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_SAI4_IPG>,
<&clk IMX8MQ_CLK_SAI4_ROOT>,
<&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
dmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>;
dma-names = "rx", "tx";
status = "disabled";
};
gpio1: gpio@30200000 {
compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
reg = <0x30200000 0x10000>;
@ -448,6 +504,23 @@
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
};
lcdif: lcd-controller@30320000 {
compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif";
reg = <0x30320000 0x10000>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
clock-names = "pix";
assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
<&clk IMX8MQ_VIDEO_PLL1_BYPASS>,
<&clk IMX8MQ_CLK_LCDIF_PIXEL>,
<&clk IMX8MQ_VIDEO_PLL1>;
assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
<&clk IMX8MQ_VIDEO_PLL1>,
<&clk IMX8MQ_VIDEO_PLL1_OUT>;
assigned-clock-rates = <0>, <0>, <0>, <594000000>;
status = "disabled";
};
iomuxc: iomuxc@30330000 {
compatible = "fsl,imx8mq-iomuxc";
reg = <0x30330000 0x10000>;
@ -519,6 +592,8 @@
clock-names = "ckil", "osc_25m", "osc_27m",
"clk_ext1", "clk_ext2",
"clk_ext3", "clk_ext4";
assigned-clocks = <&clk IMX8MQ_CLK_NOC>;
assigned-clock-rates = <800000000>;
};
src: reset-controller@30390000 {
@ -617,7 +692,7 @@
};
bus@30400000 { /* AIPS2 */
compatible = "fsl,imx8mq-aips-bus", "simple-bus";
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x30400000 0x30400000 0x400000>;
@ -676,7 +751,7 @@
};
bus@30800000 { /* AIPS3 */
compatible = "fsl,imx8mq-aips-bus", "simple-bus";
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x30800000 0x30800000 0x400000>,
@ -765,6 +840,20 @@
status = "disabled";
};
sai3: sai@308c0000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx8mq-sai";
reg = <0x308c0000 0x10000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_SAI3_IPG>,
<&clk IMX8MQ_CLK_SAI3_ROOT>,
<&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
dmas = <&sdma1 12 24 0>, <&sdma1 13 24 0>;
dma-names = "rx", "tx";
status = "disabled";
};
crypto: crypto@30900000 {
compatible = "fsl,sec-v4.0";
#address-cells = <1>;
@ -934,7 +1023,7 @@
};
bus@32c00000 { /* AIPS4 */
compatible = "fsl,imx8mq-aips-bus", "simple-bus";
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x32c00000 0x32c00000 0x400000>;
@ -1113,6 +1202,16 @@
interrupt-parent = <&gic>;
};
ddrc: memory-controller@3d400000 {
compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc";
reg = <0x3d400000 0x400000>;
clock-names = "core", "pll", "alt", "apb";
clocks = <&clk IMX8MQ_CLK_DRAM_CORE>,
<&clk IMX8MQ_DRAM_PLL_OUT>,
<&clk IMX8MQ_CLK_DRAM_ALT>,
<&clk IMX8MQ_CLK_DRAM_APB>;
};
ddr-pmu@3d800000 {
compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu";
reg = <0x3d800000 0x400000>;

12
arch/arm64/boot/dts/freescale/imx8qxp.dtsi
View File

@ -250,7 +250,6 @@
compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
reg = <0x5a060000 0x1000>;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_IPG_CLK>,
<&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>;
clock-names = "ipg", "baud";
@ -262,7 +261,6 @@
compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
reg = <0x5a070000 0x1000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_IPG_CLK>,
<&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>;
clock-names = "ipg", "baud";
@ -274,7 +272,6 @@
compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
reg = <0x5a080000 0x1000>;
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_IPG_CLK>,
<&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>;
clock-names = "ipg", "baud";
@ -286,7 +283,6 @@
compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
reg = <0x5a090000 0x1000>;
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_IPG_CLK>,
<&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>;
clock-names = "ipg", "baud";
@ -298,7 +294,6 @@
compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x5a800000 0x4000>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>;
clock-names = "per";
assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>;
@ -311,7 +306,6 @@
compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x5a810000 0x4000>;
interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>;
clock-names = "per";
assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>;
@ -324,7 +318,6 @@
compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x5a820000 0x4000>;
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>;
clock-names = "per";
assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>;
@ -337,7 +330,6 @@
compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x5a830000 0x4000>;
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>;
clock-names = "per";
assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>;
@ -361,7 +353,6 @@
usdhc1: mmc@5b010000 {
compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b010000 0x10000>;
clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>,
@ -374,7 +365,6 @@
usdhc2: mmc@5b020000 {
compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b020000 0x10000>;
clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>,
@ -389,7 +379,6 @@
usdhc3: mmc@5b030000 {
compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b030000 0x10000>;
clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>,
@ -446,7 +435,6 @@
ddr-pmu@5c020000 {
compatible = "fsl,imx8-ddr-pmu";
reg = <0x5c020000 0x10000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
};
};