Qualcomm clock updates for v5.17
This introduces bindings and drivers for the global clock controllers found in SDX65, SM8450 and MSM8976, as well as RPMh clock support for SDX65 and SM8450. It cleans up the SMD RPM clock driver and it adds includes for clk-provider.h throughout the clock providers that was lacking this. -----BEGIN PGP SIGNATURE----- iQJPBAABCAA5FiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmHVvskbHGJqb3JuLmFu ZGVyc3NvbkBsaW5hcm8ub3JnAAoJEAsfOT8Nma3FMPEP+gKnbbQW0PevFRKfvLRX t/ev7sKgrJV0GsEjEC3aL/R6uZ1Uj3VHT7aUqJFYdv/Jjl5ZxH4yQ4SbBLCfmI7G cYGj3tul2r94h5HZTjvnGvWsDq0EQ2fIst8wBy+Zh96qr+uewuFv2XtPUtdd+e6w YCQW1AFIyYONz0MMlNKbIdVyVnuD5R5dYn0lNwev3bD2FhAeHVI6SKPBWlBLINns Sch+vBjyExfbl3kSkcrLZWR1Mt19sbnF2GCT0r6jKnl05pnMpRk6zC7qyLLgAaqx 7/yPgaRyQcWZsuvhP/sIxp171mjIbha//RVS+el1A3bdoFLXEddC2J23sdSG9NOF 7Suqp759uJLsEEY9emzhYElUcXYBhdJjpPzASN89DIPWBKt/FGSowYqS4jIvrD8A bwGQ0xWi4K4tqL4RNUcF1Vu77fI3FB21YEoDBSQvPv928L7VWEemvWC7OGCPbneu pc3ZYCLZuSn/K2DHCHrsuObFAEnySBxIswNxhtZF6lheqwR4PGhj9XUKiPfU/C5R ASs1LuNXOCd6LNWxgJ7TW+jFGhv/qa261ryYVOKW6iBUOU0Bsob7p6YZP0/0Enca o918FKXdmfdlXBJeyV74oeM5IIPeg/lMyfGzmGx7WOi+ntRUnf+k9PDybVDIGq6P Y55XVPKP4Twrxd0/IyZUZCTI =PGNc -----END PGP SIGNATURE----- Merge tag 'qcom-clk-for-5.17' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom Pull qcom clk driver updates from Bjorn Andersson: This introduces bindings and drivers for the global clock controllers found in SDX65, SM8450 and MSM8976, as well as RPMh clock support for SDX65 and SM8450. It cleans up the SMD RPM clock driver and it adds includes for clk-provider.h throughout the clock providers that was lacking this. * tag 'qcom-clk-for-5.17' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (23 commits) clk: qcom: turingcc-qcs404: explicitly include clk-provider.h clk: qcom: q6sstop-qcs404: explicitly include clk-provider.h clk: qcom: mmcc-apq8084: explicitly include clk-provider.h clk: qcom: lpasscc-sdm845: explicitly include clk-provider.h clk: qcom: lpasscc-sc7280: explicitly include clk-provider.h clk: qcom: gcc-sm6350: explicitly include clk-provider.h clk: qcom: gcc-msm8994: explicitly include clk-provider.h clk: qcom: gcc-sm8350: explicitly include clk-provider.h clk: qcom: Add MSM8976/56 Global Clock Controller (GCC) driver dt-bindings: clk: qcom: Document MSM8976 Global Clock Controller clk: qcom: Add clock driver for SM8450 clk: qcom: Add SDX65 GCC support clk: qcom: Add LUCID_EVO PLL type for SDX65 dt-bindings: clock: Add SM8450 GCC clock bindings dt-bindings: clock: Add SDX65 GCC clock bindings clk: qcom: rpmh: add support for SM8450 rpmh clocks dt-bindings: clock: Add RPMHCC bindings for SM8450 clk: qcom: smd-rpm: Drop binary value handling for buffered clock clk: qcom: smd-rpm: Drop the use of struct rpm_cc clk: qcom: smd-rpm: Drop MFD qcom-rpm reference ...
This commit is contained in:
Stephen Boyd
commit
87e55700f3
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@ -0,0 +1,97 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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||||
%YAML 1.2
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||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8976.yaml#
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||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
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||||
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title: Qualcomm Global Clock & Reset Controller Binding for MSM8976
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maintainers:
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||||
- Stephen Boyd <sboyd@kernel.org>
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- Taniya Das <tdas@codeaurora.org>
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description: |
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Qualcomm global clock control module which supports the clocks, resets and
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power domains on MSM8976.
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See also:
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- dt-bindings/clock/qcom,gcc-msm8976.h
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properties:
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compatible:
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enum:
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- qcom,gcc-msm8976
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- qcom,gcc-msm8976-v1.1
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clocks:
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items:
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- description: XO source
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- description: Always-on XO source
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- description: Pixel clock from DSI PHY0
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- description: Byte clock from DSI PHY0
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- description: Pixel clock from DSI PHY1
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- description: Byte clock from DSI PHY1
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clock-names:
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items:
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- const: xo
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- const: xo_a
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- const: dsi0pll
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- const: dsi0pllbyte
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- const: dsi1pll
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- const: dsi1pllbyte
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vdd_gfx-supply:
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description:
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Phandle to voltage regulator providing power to the GX domain.
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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reg:
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maxItems: 1
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|
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- vdd_gfx-supply
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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clock-controller@1800000 {
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compatible = "qcom,gcc-msm8976";
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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reg = <0x1800000 0x80000>;
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clocks = <&xo_board>,
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<&xo_board>,
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<&dsi0_phy 1>,
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<&dsi0_phy 0>,
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<&dsi1_phy 1>,
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<&dsi1_phy 0>;
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clock-names = "xo",
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"xo_a",
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"dsi0pll",
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"dsi0pllbyte",
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"dsi1pll",
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"dsi1pllbyte";
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vdd_gfx-supply = <&pm8004_s5>;
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};
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...
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@ -0,0 +1,80 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,gcc-sdx65.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Global Clock & Reset Controller Binding for SDX65
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maintainers:
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- Vamsi krishna Lanka <quic_vamslank@quicinc.com>
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|
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description: |
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Qualcomm global clock control module which supports the clocks, resets and
|
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power domains on SDX65
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|
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See also:
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- dt-bindings/clock/qcom,gcc-sdx65.h
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|
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properties:
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compatible:
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const: qcom,gcc-sdx65
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reg:
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maxItems: 1
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|
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clocks:
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items:
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- description: Board XO source
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- description: Board active XO source
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- description: Sleep clock source
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- description: PCIE Pipe clock source
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- description: USB3 phy wrapper pipe clock source
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- description: PLL test clock source (Optional clock)
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minItems: 5
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clock-names:
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items:
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- const: bi_tcxo
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- const: bi_tcxo_ao
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- const: sleep_clk
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- const: pcie_pipe_clk
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- const: usb3_phy_wrapper_gcc_usb30_pipe_clk
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- const: core_bi_pll_test_se # Optional clock
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minItems: 5
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|
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'#clock-cells':
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const: 1
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||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
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'#power-domain-cells':
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const: 1
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||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
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- '#clock-cells'
|
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- '#reset-cells'
|
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- '#power-domain-cells'
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|
||||
additionalProperties: false
|
||||
|
||||
examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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clock-controller@100000 {
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compatible = "qcom,gcc-sdx65";
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reg = <0x100000 0x1f7400>;
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clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
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<&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, <&pll_test_clk>;
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clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
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"pcie_pipe_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk", "core_bi_pll_test_se";
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...
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@ -0,0 +1,85 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8450.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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|
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title: Qualcomm Global Clock & Reset Controller Binding for SM8450
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|
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maintainers:
|
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- Vinod Koul <vkoul@kernel.org>
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|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on SM8450
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-sm8450.h
|
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|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-sm8450
|
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|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Sleep clock source
|
||||
- description: PCIE 0 Pipe clock source (Optional clock)
|
||||
- description: PCIE 1 Pipe clock source (Optional clock)
|
||||
- description: PCIE 1 Phy Auxillary clock source (Optional clock)
|
||||
- description: UFS Phy Rx symbol 0 clock source (Optional clock)
|
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- description: UFS Phy Rx symbol 1 clock source (Optional clock)
|
||||
- description: UFS Phy Tx symbol 0 clock source (Optional clock)
|
||||
- description: USB3 Phy wrapper pipe clock source (Optional clock)
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||||
minItems: 2
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||||
|
||||
clock-names:
|
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items:
|
||||
- const: bi_tcxo
|
||||
- const: sleep_clk
|
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- const: pcie_0_pipe_clk # Optional clock
|
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- const: pcie_1_pipe_clk # Optional clock
|
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- const: pcie_1_phy_aux_clk # Optional clock
|
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- const: ufs_phy_rx_symbol_0_clk # Optional clock
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- const: ufs_phy_rx_symbol_1_clk # Optional clock
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- const: ufs_phy_tx_symbol_0_clk # Optional clock
|
||||
- const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock
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minItems: 2
|
||||
|
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'#clock-cells':
|
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const: 1
|
||||
|
||||
'#reset-cells':
|
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const: 1
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|
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'#power-domain-cells':
|
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const: 1
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||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
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- '#reset-cells'
|
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- '#power-domain-cells'
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|
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additionalProperties: false
|
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|
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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clock-controller@100000 {
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compatible = "qcom,gcc-sm8450";
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reg = <0x00100000 0x001f4200>;
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clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
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clock-names = "bi_tcxo", "sleep_clk";
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...
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@ -22,10 +22,12 @@ properties:
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- qcom,sc8180x-rpmh-clk
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- qcom,sdm845-rpmh-clk
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- qcom,sdx55-rpmh-clk
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- qcom,sdx65-rpmh-clk
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- qcom,sm6350-rpmh-clk
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- qcom,sm8150-rpmh-clk
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- qcom,sm8250-rpmh-clk
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- qcom,sm8350-rpmh-clk
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- qcom,sm8450-rpmh-clk
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clocks:
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maxItems: 1
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|
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@ -15725,6 +15725,15 @@ F: Documentation/admin-guide/media/qcom_camss.rst
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F: Documentation/devicetree/bindings/media/*camss*
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F: drivers/media/platform/qcom/camss/
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QUALCOMM CLOCK DRIVERS
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||||
M: Bjorn Andersson <bjorn.andersson@linaro.org>
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L: linux-arm-msm@vger.kernel.org
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S: Supported
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git
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F: Documentation/devicetree/bindings/clock/qcom,*
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F: drivers/clk/qcom/
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F: include/dt-bindings/clock/qcom,*
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|
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QUALCOMM CORE POWER REDUCTION (CPR) AVS DRIVER
|
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M: Niklas Cassel <nks@flawful.org>
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L: linux-pm@vger.kernel.org
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|
|
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@ -265,6 +265,14 @@ config MSM_MMCC_8974
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Say Y if you want to support multimedia devices such as display,
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graphics, video encode/decode, camera, etc.
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config MSM_GCC_8976
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tristate "MSM8956/76 Global Clock Controller"
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select QCOM_GDSC
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help
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Support for the global clock controller on msm8956/76 devices.
|
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Say Y if you want to use peripheral devices such as UART, SPI,
|
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i2c, USB, SD/eMMC, SATA, PCIe, etc.
|
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||||
config MSM_MMCC_8994
|
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tristate "MSM8994 Multimedia Clock Controller"
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select MSM_GCC_8994
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@ -564,6 +572,14 @@ config SM_CAMCC_8250
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Support for the camera clock controller on SM8250 devices.
|
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Say Y if you want to support camera devices and camera functionality.
|
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|
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config SDX_GCC_65
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tristate "SDX65 Global Clock Controller"
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select QCOM_GDSC
|
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help
|
||||
Support for the global clock controller on SDX65 devices.
|
||||
Say Y if you want to use peripheral devices such as UART,
|
||||
SPI, I2C, USB, SD/UFS, PCIe etc.
|
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config SM_DISPCC_8250
|
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tristate "SM8150 and SM8250 Display Clock Controller"
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depends on SM_GCC_8150 || SM_GCC_8250
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|
|
@ -618,6 +634,14 @@ config SM_GCC_8350
|
|||
Say Y if you want to use peripheral devices such as UART,
|
||||
SPI, I2C, USB, SD/UFS, PCIe etc.
|
||||
|
||||
config SM_GCC_8450
|
||||
tristate "SM8450 Global Clock Controller"
|
||||
select QCOM_GDSC
|
||||
help
|
||||
Support for the global clock controller on SM8450 devices.
|
||||
Say Y if you want to use peripheral devices such as UART,
|
||||
SPI, I2C, USB, SD/UFS, PCIe etc.
|
||||
|
||||
config SM_GPUCC_8150
|
||||
tristate "SM8150 Graphics Clock Controller"
|
||||
select SM_GCC_8150
|
||||
|
|
|
|||
|
|
@ -36,6 +36,7 @@ obj-$(CONFIG_MSM_GCC_8939) += gcc-msm8939.o
|
|||
obj-$(CONFIG_MSM_GCC_8953) += gcc-msm8953.o
|
||||
obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o
|
||||
obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o
|
||||
obj-$(CONFIG_MSM_GCC_8976) += gcc-msm8976.o
|
||||
obj-$(CONFIG_MSM_GCC_8994) += gcc-msm8994.o
|
||||
obj-$(CONFIG_MSM_GCC_8996) += gcc-msm8996.o
|
||||
obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o
|
||||
|
|
@ -83,6 +84,7 @@ obj-$(CONFIG_SDM_LPASSCC_845) += lpasscc-sdm845.o
|
|||
obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
|
||||
obj-$(CONFIG_SDX_GCC_55) += gcc-sdx55.o
|
||||
obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o
|
||||
obj-$(CONFIG_SDX_GCC_65) += gcc-sdx65.o
|
||||
obj-$(CONFIG_SM_DISPCC_8250) += dispcc-sm8250.o
|
||||
obj-$(CONFIG_SM_GCC_6115) += gcc-sm6115.o
|
||||
obj-$(CONFIG_SM_GCC_6125) += gcc-sm6125.o
|
||||
|
|
@ -90,6 +92,7 @@ obj-$(CONFIG_SM_GCC_6350) += gcc-sm6350.o
|
|||
obj-$(CONFIG_SM_GCC_8150) += gcc-sm8150.o
|
||||
obj-$(CONFIG_SM_GCC_8250) += gcc-sm8250.o
|
||||
obj-$(CONFIG_SM_GCC_8350) += gcc-sm8350.o
|
||||
obj-$(CONFIG_SM_GCC_8450) += gcc-sm8450.o
|
||||
obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o
|
||||
obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o
|
||||
obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
|
|
@ -139,6 +140,20 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
|
|||
[PLL_OFF_OPMODE] = 0x28,
|
||||
[PLL_OFF_STATUS] = 0x38,
|
||||
},
|
||||
[CLK_ALPHA_PLL_TYPE_LUCID_EVO] = {
|
||||
[PLL_OFF_OPMODE] = 0x04,
|
||||
[PLL_OFF_STATUS] = 0x0c,
|
||||
[PLL_OFF_L_VAL] = 0x10,
|
||||
[PLL_OFF_ALPHA_VAL] = 0x14,
|
||||
[PLL_OFF_USER_CTL] = 0x18,
|
||||
[PLL_OFF_USER_CTL_U] = 0x1c,
|
||||
[PLL_OFF_CONFIG_CTL] = 0x20,
|
||||
[PLL_OFF_CONFIG_CTL_U] = 0x24,
|
||||
[PLL_OFF_CONFIG_CTL_U1] = 0x28,
|
||||
[PLL_OFF_TEST_CTL] = 0x2c,
|
||||
[PLL_OFF_TEST_CTL_U] = 0x30,
|
||||
[PLL_OFF_TEST_CTL_U1] = 0x34,
|
||||
},
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
|
||||
|
||||
|
|
@ -175,6 +190,10 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
|
|||
#define LUCID_5LPE_PLL_LATCH_INPUT BIT(14)
|
||||
#define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21)
|
||||
|
||||
/* LUCID EVO PLL specific settings and offsets */
|
||||
#define LUCID_EVO_ENABLE_VOTE_RUN BIT(25)
|
||||
#define LUCID_EVO_PLL_L_VAL_MASK GENMASK(15, 0)
|
||||
|
||||
/* ZONDA PLL specific */
|
||||
#define ZONDA_PLL_OUT_MASK 0xf
|
||||
#define ZONDA_STAY_IN_CFA BIT(16)
|
||||
|
|
@ -1741,24 +1760,32 @@ static int alpha_pll_lucid_5lpe_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
LUCID_5LPE_ALPHA_PLL_ACK_LATCH);
|
||||
}
|
||||
|
||||
static int clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
static int __clk_lucid_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate,
|
||||
unsigned long enable_vote_run)
|
||||
{
|
||||
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
|
||||
int i, val = 0, div, ret;
|
||||
struct regmap *regmap = pll->clkr.regmap;
|
||||
int i, val, div, ret;
|
||||
u32 mask;
|
||||
|
||||
/*
|
||||
* If the PLL is in FSM mode, then treat set_rate callback as a
|
||||
* no-operation.
|
||||
*/
|
||||
ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
|
||||
ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (val & LUCID_5LPE_ENABLE_VOTE_RUN)
|
||||
if (val & enable_vote_run)
|
||||
return 0;
|
||||
|
||||
if (!pll->post_div_table) {
|
||||
pr_err("Missing the post_div_table for the %s PLL\n",
|
||||
clk_hw_get_name(&pll->clkr.hw));
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
|
||||
for (i = 0; i < pll->num_post_div; i++) {
|
||||
if (pll->post_div_table[i].div == div) {
|
||||
|
|
@ -1772,6 +1799,12 @@ static int clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long
|
|||
mask, val << pll->post_div_shift);
|
||||
}
|
||||
|
||||
static int clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_5LPE_ENABLE_VOTE_RUN);
|
||||
}
|
||||
|
||||
const struct clk_ops clk_alpha_pll_lucid_5lpe_ops = {
|
||||
.prepare = alpha_pll_lucid_5lpe_prepare,
|
||||
.enable = alpha_pll_lucid_5lpe_enable,
|
||||
|
|
@ -1951,3 +1984,124 @@ const struct clk_ops clk_alpha_pll_zonda_ops = {
|
|||
.set_rate = clk_zonda_pll_set_rate,
|
||||
};
|
||||
EXPORT_SYMBOL(clk_alpha_pll_zonda_ops);
|
||||
|
||||
static int alpha_pll_lucid_evo_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
|
||||
struct regmap *regmap = pll->clkr.regmap;
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* If in FSM mode, just vote for it */
|
||||
if (val & LUCID_EVO_ENABLE_VOTE_RUN) {
|
||||
ret = clk_enable_regmap(hw);
|
||||
if (ret)
|
||||
return ret;
|
||||
return wait_for_pll_enable_lock(pll);
|
||||
}
|
||||
|
||||
/* Check if PLL is already enabled */
|
||||
ret = trion_pll_is_enabled(pll, regmap);
|
||||
if (ret < 0) {
|
||||
return ret;
|
||||
} else if (ret) {
|
||||
pr_warn("%s PLL is already enabled\n", clk_hw_get_name(&pll->clkr.hw));
|
||||
return 0;
|
||||
}
|
||||
|
||||
ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Set operation mode to RUN */
|
||||
regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
|
||||
|
||||
ret = wait_for_pll_enable_lock(pll);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Enable the PLL outputs */
|
||||
ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Enable the global PLL outputs */
|
||||
ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Ensure that the write above goes through before returning. */
|
||||
mb();
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void alpha_pll_lucid_evo_disable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
|
||||
struct regmap *regmap = pll->clkr.regmap;
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
|
||||
if (ret)
|
||||
return;
|
||||
|
||||
/* If in FSM mode, just unvote it */
|
||||
if (val & LUCID_EVO_ENABLE_VOTE_RUN) {
|
||||
clk_disable_regmap(hw);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Disable the global PLL output */
|
||||
ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
|
||||
if (ret)
|
||||
return;
|
||||
|
||||
/* Disable the PLL outputs */
|
||||
ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
|
||||
if (ret)
|
||||
return;
|
||||
|
||||
/* Place the PLL mode in STANDBY */
|
||||
regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
|
||||
}
|
||||
|
||||
static unsigned long alpha_pll_lucid_evo_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
|
||||
struct regmap *regmap = pll->clkr.regmap;
|
||||
u32 l, frac;
|
||||
|
||||
regmap_read(regmap, PLL_L_VAL(pll), &l);
|
||||
l &= LUCID_EVO_PLL_L_VAL_MASK;
|
||||
regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac);
|
||||
|
||||
return alpha_pll_calc_rate(parent_rate, l, frac, pll_alpha_width(pll));
|
||||
}
|
||||
|
||||
static int clk_lucid_evo_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_EVO_ENABLE_VOTE_RUN);
|
||||
}
|
||||
|
||||
const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops = {
|
||||
.enable = alpha_pll_lucid_evo_enable,
|
||||
.disable = alpha_pll_lucid_evo_disable,
|
||||
.is_enabled = clk_trion_pll_is_enabled,
|
||||
.recalc_rate = alpha_pll_lucid_evo_recalc_rate,
|
||||
.round_rate = clk_alpha_pll_round_rate,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_evo_ops);
|
||||
|
||||
const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops = {
|
||||
.recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
|
||||
.round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
|
||||
.set_rate = clk_lucid_evo_pll_postdiv_set_rate,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_evo_ops);
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@ enum {
|
|||
CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION,
|
||||
CLK_ALPHA_PLL_TYPE_AGERA,
|
||||
CLK_ALPHA_PLL_TYPE_ZONDA,
|
||||
CLK_ALPHA_PLL_TYPE_LUCID_EVO,
|
||||
CLK_ALPHA_PLL_TYPE_MAX,
|
||||
};
|
||||
|
||||
|
|
@ -151,6 +152,8 @@ extern const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops;
|
|||
|
||||
extern const struct clk_ops clk_alpha_pll_zonda_ops;
|
||||
#define clk_alpha_pll_postdiv_zonda_ops clk_alpha_pll_postdiv_fabia_ops
|
||||
extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops;
|
||||
extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops;
|
||||
|
||||
void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
|
||||
const struct alpha_pll_config *config);
|
||||
|
|
|
|||
|
|
@ -515,6 +515,32 @@ static const struct clk_rpmh_desc clk_rpmh_sm8350 = {
|
|||
/* Resource name must match resource id present in cmd-db */
|
||||
DEFINE_CLK_RPMH_ARC(sc7280, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 4);
|
||||
|
||||
DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 4);
|
||||
DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 4);
|
||||
|
||||
static struct clk_hw *sm8450_rpmh_clocks[] = {
|
||||
[RPMH_CXO_CLK] = &sc7280_bi_tcxo.hw,
|
||||
[RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_ao.hw,
|
||||
[RPMH_LN_BB_CLK1] = &sm8450_ln_bb_clk1.hw,
|
||||
[RPMH_LN_BB_CLK1_A] = &sm8450_ln_bb_clk1_ao.hw,
|
||||
[RPMH_LN_BB_CLK2] = &sm8450_ln_bb_clk2.hw,
|
||||
[RPMH_LN_BB_CLK2_A] = &sm8450_ln_bb_clk2_ao.hw,
|
||||
[RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
|
||||
[RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
|
||||
[RPMH_RF_CLK2] = &sdm845_rf_clk2.hw,
|
||||
[RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw,
|
||||
[RPMH_RF_CLK3] = &sdm845_rf_clk3.hw,
|
||||
[RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw,
|
||||
[RPMH_RF_CLK4] = &sm8350_rf_clk4.hw,
|
||||
[RPMH_RF_CLK4_A] = &sm8350_rf_clk4_ao.hw,
|
||||
[RPMH_IPA_CLK] = &sdm845_ipa.hw,
|
||||
};
|
||||
|
||||
static const struct clk_rpmh_desc clk_rpmh_sm8450 = {
|
||||
.clks = sm8450_rpmh_clocks,
|
||||
.num_clks = ARRAY_SIZE(sm8450_rpmh_clocks),
|
||||
};
|
||||
|
||||
static struct clk_hw *sc7280_rpmh_clocks[] = {
|
||||
[RPMH_CXO_CLK] = &sc7280_bi_tcxo.hw,
|
||||
[RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_ao.hw,
|
||||
|
|
@ -556,6 +582,30 @@ static const struct clk_rpmh_desc clk_rpmh_sm6350 = {
|
|||
.num_clks = ARRAY_SIZE(sm6350_rpmh_clocks),
|
||||
};
|
||||
|
||||
DEFINE_CLK_RPMH_VRM(sdx65, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 4);
|
||||
|
||||
static struct clk_hw *sdx65_rpmh_clocks[] = {
|
||||
[RPMH_CXO_CLK] = &sc7280_bi_tcxo.hw,
|
||||
[RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_ao.hw,
|
||||
[RPMH_LN_BB_CLK1] = &sdx65_ln_bb_clk1.hw,
|
||||
[RPMH_LN_BB_CLK1_A] = &sdx65_ln_bb_clk1_ao.hw,
|
||||
[RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
|
||||
[RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
|
||||
[RPMH_RF_CLK2] = &sdm845_rf_clk2.hw,
|
||||
[RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw,
|
||||
[RPMH_RF_CLK3] = &sdm845_rf_clk3.hw,
|
||||
[RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw,
|
||||
[RPMH_RF_CLK4] = &sm8350_rf_clk4.hw,
|
||||
[RPMH_RF_CLK4_A] = &sm8350_rf_clk4_ao.hw,
|
||||
[RPMH_IPA_CLK] = &sdm845_ipa.hw,
|
||||
[RPMH_QPIC_CLK] = &sdx55_qpic_clk.hw,
|
||||
};
|
||||
|
||||
static const struct clk_rpmh_desc clk_rpmh_sdx65 = {
|
||||
.clks = sdx65_rpmh_clocks,
|
||||
.num_clks = ARRAY_SIZE(sdx65_rpmh_clocks),
|
||||
};
|
||||
|
||||
static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
|
||||
void *data)
|
||||
{
|
||||
|
|
@ -643,10 +693,12 @@ static const struct of_device_id clk_rpmh_match_table[] = {
|
|||
{ .compatible = "qcom,sc8180x-rpmh-clk", .data = &clk_rpmh_sc8180x},
|
||||
{ .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845},
|
||||
{ .compatible = "qcom,sdx55-rpmh-clk", .data = &clk_rpmh_sdx55},
|
||||
{ .compatible = "qcom,sdx65-rpmh-clk", .data = &clk_rpmh_sdx65},
|
||||
{ .compatible = "qcom,sm6350-rpmh-clk", .data = &clk_rpmh_sm6350},
|
||||
{ .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150},
|
||||
{ .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250},
|
||||
{ .compatible = "qcom,sm8350-rpmh-clk", .data = &clk_rpmh_sm8350},
|
||||
{ .compatible = "qcom,sm8450-rpmh-clk", .data = &clk_rpmh_sm8450},
|
||||
{ .compatible = "qcom,sc7280-rpmh-clk", .data = &clk_rpmh_sc7280},
|
||||
{ }
|
||||
};
|
||||
|
|
|
|||
|
|
@ -17,7 +17,6 @@
|
|||
#include <linux/soc/qcom/smd-rpm.h>
|
||||
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
#include <dt-bindings/mfd/qcom-rpm.h>
|
||||
|
||||
#define QCOM_RPM_KEY_SOFTWARE_ENABLE 0x6e657773
|
||||
#define QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY 0x62636370
|
||||
|
|
@ -151,12 +150,6 @@ struct clk_smd_rpm_req {
|
|||
__le32 value;
|
||||
};
|
||||
|
||||
struct rpm_cc {
|
||||
struct qcom_rpm *rpm;
|
||||
struct clk_smd_rpm **clks;
|
||||
size_t num_clks;
|
||||
};
|
||||
|
||||
struct rpm_smd_clk_desc {
|
||||
struct clk_smd_rpm **clks;
|
||||
size_t num_clks;
|
||||
|
|
@ -196,10 +189,6 @@ static int clk_smd_rpm_set_rate_active(struct clk_smd_rpm *r,
|
|||
.value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */
|
||||
};
|
||||
|
||||
/* Buffered clock needs a binary value */
|
||||
if (r->rpm_res_type == QCOM_SMD_RPM_CLK_BUF_A)
|
||||
req.value = cpu_to_le32(!!req.value);
|
||||
|
||||
return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_ACTIVE_STATE,
|
||||
r->rpm_res_type, r->rpm_clk_id, &req,
|
||||
sizeof(req));
|
||||
|
|
@ -214,10 +203,6 @@ static int clk_smd_rpm_set_rate_sleep(struct clk_smd_rpm *r,
|
|||
.value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */
|
||||
};
|
||||
|
||||
/* Buffered clock needs a binary value */
|
||||
if (r->rpm_res_type == QCOM_SMD_RPM_CLK_BUF_A)
|
||||
req.value = cpu_to_le32(!!req.value);
|
||||
|
||||
return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_SLEEP_STATE,
|
||||
r->rpm_res_type, r->rpm_clk_id, &req,
|
||||
sizeof(req));
|
||||
|
|
@ -1159,20 +1144,19 @@ MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table);
|
|||
static struct clk_hw *qcom_smdrpm_clk_hw_get(struct of_phandle_args *clkspec,
|
||||
void *data)
|
||||
{
|
||||
struct rpm_cc *rcc = data;
|
||||
const struct rpm_smd_clk_desc *desc = data;
|
||||
unsigned int idx = clkspec->args[0];
|
||||
|
||||
if (idx >= rcc->num_clks) {
|
||||
if (idx >= desc->num_clks) {
|
||||
pr_err("%s: invalid index %u\n", __func__, idx);
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
return rcc->clks[idx] ? &rcc->clks[idx]->hw : ERR_PTR(-ENOENT);
|
||||
return desc->clks[idx] ? &desc->clks[idx]->hw : ERR_PTR(-ENOENT);
|
||||
}
|
||||
|
||||
static int rpm_smd_clk_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct rpm_cc *rcc;
|
||||
int ret;
|
||||
size_t num_clks, i;
|
||||
struct qcom_smd_rpm *rpm;
|
||||
|
|
@ -1192,13 +1176,6 @@ static int rpm_smd_clk_probe(struct platform_device *pdev)
|
|||
rpm_smd_clks = desc->clks;
|
||||
num_clks = desc->num_clks;
|
||||
|
||||
rcc = devm_kzalloc(&pdev->dev, sizeof(*rcc), GFP_KERNEL);
|
||||
if (!rcc)
|
||||
return -ENOMEM;
|
||||
|
||||
rcc->clks = rpm_smd_clks;
|
||||
rcc->num_clks = num_clks;
|
||||
|
||||
for (i = 0; i < num_clks; i++) {
|
||||
if (!rpm_smd_clks[i])
|
||||
continue;
|
||||
|
|
@ -1224,7 +1201,7 @@ static int rpm_smd_clk_probe(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
ret = devm_of_clk_add_hw_provider(&pdev->dev, qcom_smdrpm_clk_hw_get,
|
||||
rcc);
|
||||
(void *)desc);
|
||||
if (ret)
|
||||
goto err;
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -2,6 +2,7 @@
|
|||
/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/err.h>
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -4,6 +4,7 @@
|
|||
* Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/regmap.h>
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@
|
|||
* Copyright (c) 2020-2021, Linaro Limited
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/regmap.h>
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -3,6 +3,7 @@
|
|||
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_clock.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
|
|
|
|||
|
|
@ -3,6 +3,7 @@
|
|||
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_address.h>
|
||||
|
|
|
|||
|
|
@ -3,6 +3,7 @@
|
|||
* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/module.h>
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@
|
|||
*/
|
||||
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@
|
|||
*/
|
||||
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/module.h>
|
||||
|
|
|
|||
|
|
@ -0,0 +1,240 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (C) 2016, The Linux Foundation. All rights reserved.
|
||||
* Copyright (C) 2016-2021, AngeloGioacchino Del Regno
|
||||
* <angelogioacchino.delregno@somainline.org>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_MSM_GCC_8976_H
|
||||
#define _DT_BINDINGS_CLK_MSM_GCC_8976_H
|
||||
|
||||
#define GPLL0 0
|
||||
#define GPLL2 1
|
||||
#define GPLL3 2
|
||||
#define GPLL4 3
|
||||
#define GPLL6 4
|
||||
#define GPLL0_CLK_SRC 5
|
||||
#define GPLL2_CLK_SRC 6
|
||||
#define GPLL3_CLK_SRC 7
|
||||
#define GPLL4_CLK_SRC 8
|
||||
#define GPLL6_CLK_SRC 9
|
||||
#define GCC_BLSP1_QUP1_SPI_APPS_CLK 10
|
||||
#define GCC_BLSP1_QUP1_I2C_APPS_CLK 11
|
||||
#define GCC_BLSP1_QUP2_I2C_APPS_CLK 12
|
||||
#define GCC_BLSP1_QUP2_SPI_APPS_CLK 13
|
||||
#define GCC_BLSP1_QUP3_I2C_APPS_CLK 14
|
||||
#define GCC_BLSP1_QUP3_SPI_APPS_CLK 15
|
||||
#define GCC_BLSP1_QUP4_I2C_APPS_CLK 16
|
||||
#define GCC_BLSP1_QUP4_SPI_APPS_CLK 17
|
||||
#define GCC_BLSP1_UART1_APPS_CLK 18
|
||||
#define GCC_BLSP1_UART2_APPS_CLK 19
|
||||
#define GCC_BLSP2_QUP1_I2C_APPS_CLK 20
|
||||
#define GCC_BLSP2_QUP1_SPI_APPS_CLK 21
|
||||
#define GCC_BLSP2_QUP2_I2C_APPS_CLK 22
|
||||
#define GCC_BLSP2_QUP2_SPI_APPS_CLK 23
|
||||
#define GCC_BLSP2_QUP3_I2C_APPS_CLK 24
|
||||
#define GCC_BLSP2_QUP3_SPI_APPS_CLK 25
|
||||
#define GCC_BLSP2_QUP4_I2C_APPS_CLK 26
|
||||
#define GCC_BLSP2_QUP4_SPI_APPS_CLK 27
|
||||
#define GCC_BLSP2_UART1_APPS_CLK 28
|
||||
#define GCC_BLSP2_UART2_APPS_CLK 29
|
||||
#define GCC_CAMSS_CCI_AHB_CLK 30
|
||||
#define GCC_CAMSS_CCI_CLK 31
|
||||
#define GCC_CAMSS_CPP_AHB_CLK 32
|
||||
#define GCC_CAMSS_CPP_AXI_CLK 33
|
||||
#define GCC_CAMSS_CPP_CLK 34
|
||||
#define GCC_CAMSS_CSI0_AHB_CLK 35
|
||||
#define GCC_CAMSS_CSI0_CLK 36
|
||||
#define GCC_CAMSS_CSI0PHY_CLK 37
|
||||
#define GCC_CAMSS_CSI0PIX_CLK 38
|
||||
#define GCC_CAMSS_CSI0RDI_CLK 39
|
||||
#define GCC_CAMSS_CSI1_AHB_CLK 40
|
||||
#define GCC_CAMSS_CSI1_CLK 41
|
||||
#define GCC_CAMSS_CSI1PHY_CLK 42
|
||||
#define GCC_CAMSS_CSI1PIX_CLK 43
|
||||
#define GCC_CAMSS_CSI1RDI_CLK 44
|
||||
#define GCC_CAMSS_CSI2_AHB_CLK 45
|
||||
#define GCC_CAMSS_CSI2_CLK 46
|
||||
#define GCC_CAMSS_CSI2PHY_CLK 47
|
||||
#define GCC_CAMSS_CSI2PIX_CLK 48
|
||||
#define GCC_CAMSS_CSI2RDI_CLK 49
|
||||
#define GCC_CAMSS_CSI_VFE0_CLK 50
|
||||
#define GCC_CAMSS_CSI_VFE1_CLK 51
|
||||
#define GCC_CAMSS_GP0_CLK 52
|
||||
#define GCC_CAMSS_GP1_CLK 53
|
||||
#define GCC_CAMSS_ISPIF_AHB_CLK 54
|
||||
#define GCC_CAMSS_JPEG0_CLK 55
|
||||
#define GCC_CAMSS_JPEG_AHB_CLK 56
|
||||
#define GCC_CAMSS_JPEG_AXI_CLK 57
|
||||
#define GCC_CAMSS_MCLK0_CLK 58
|
||||
#define GCC_CAMSS_MCLK1_CLK 59
|
||||
#define GCC_CAMSS_MCLK2_CLK 60
|
||||
#define GCC_CAMSS_MICRO_AHB_CLK 61
|
||||
#define GCC_CAMSS_CSI0PHYTIMER_CLK 62
|
||||
#define GCC_CAMSS_CSI1PHYTIMER_CLK 63
|
||||
#define GCC_CAMSS_AHB_CLK 64
|
||||
#define GCC_CAMSS_TOP_AHB_CLK 65
|
||||
#define GCC_CAMSS_VFE0_CLK 66
|
||||
#define GCC_CAMSS_VFE_AHB_CLK 67
|
||||
#define GCC_CAMSS_VFE_AXI_CLK 68
|
||||
#define GCC_CAMSS_VFE1_AHB_CLK 69
|
||||
#define GCC_CAMSS_VFE1_AXI_CLK 70
|
||||
#define GCC_CAMSS_VFE1_CLK 71
|
||||
#define GCC_DCC_CLK 72
|
||||
#define GCC_GP1_CLK 73
|
||||
#define GCC_GP2_CLK 74
|
||||
#define GCC_GP3_CLK 75
|
||||
#define GCC_MDSS_AHB_CLK 76
|
||||
#define GCC_MDSS_AXI_CLK 77
|
||||
#define GCC_MDSS_ESC0_CLK 78
|
||||
#define GCC_MDSS_ESC1_CLK 79
|
||||
#define GCC_MDSS_MDP_CLK 80
|
||||
#define GCC_MDSS_VSYNC_CLK 81
|
||||
#define GCC_MSS_CFG_AHB_CLK 82
|
||||
#define GCC_MSS_Q6_BIMC_AXI_CLK 83
|
||||
#define GCC_PDM2_CLK 84
|
||||
#define GCC_PRNG_AHB_CLK 85
|
||||
#define GCC_PDM_AHB_CLK 86
|
||||
#define GCC_RBCPR_GFX_AHB_CLK 87
|
||||
#define GCC_RBCPR_GFX_CLK 88
|
||||
#define GCC_SDCC1_AHB_CLK 89
|
||||
#define GCC_SDCC1_APPS_CLK 90
|
||||
#define GCC_SDCC1_ICE_CORE_CLK 91
|
||||
#define GCC_SDCC2_AHB_CLK 92
|
||||
#define GCC_SDCC2_APPS_CLK 93
|
||||
#define GCC_SDCC3_AHB_CLK 94
|
||||
#define GCC_SDCC3_APPS_CLK 95
|
||||
#define GCC_USB2A_PHY_SLEEP_CLK 96
|
||||
#define GCC_USB_HS_PHY_CFG_AHB_CLK 97
|
||||
#define GCC_USB_FS_AHB_CLK 98
|
||||
#define GCC_USB_FS_IC_CLK 99
|
||||
#define GCC_USB_FS_SYSTEM_CLK 100
|
||||
#define GCC_USB_HS_AHB_CLK 101
|
||||
#define GCC_USB_HS_SYSTEM_CLK 102
|
||||
#define GCC_VENUS0_AHB_CLK 103
|
||||
#define GCC_VENUS0_AXI_CLK 104
|
||||
#define GCC_VENUS0_CORE0_VCODEC0_CLK 105
|
||||
#define GCC_VENUS0_CORE1_VCODEC0_CLK 106
|
||||
#define GCC_VENUS0_VCODEC0_CLK 107
|
||||
#define GCC_APSS_AHB_CLK 108
|
||||
#define GCC_APSS_AXI_CLK 109
|
||||
#define GCC_BLSP1_AHB_CLK 110
|
||||
#define GCC_BLSP2_AHB_CLK 111
|
||||
#define GCC_BOOT_ROM_AHB_CLK 112
|
||||
#define GCC_CRYPTO_AHB_CLK 113
|
||||
#define GCC_CRYPTO_AXI_CLK 114
|
||||
#define GCC_CRYPTO_CLK 115
|
||||
#define GCC_CPP_TBU_CLK 116
|
||||
#define GCC_APSS_TCU_CLK 117
|
||||
#define GCC_JPEG_TBU_CLK 118
|
||||
#define GCC_MDP_RT_TBU_CLK 119
|
||||
#define GCC_MDP_TBU_CLK 120
|
||||
#define GCC_SMMU_CFG_CLK 121
|
||||
#define GCC_VENUS_1_TBU_CLK 122
|
||||
#define GCC_VENUS_TBU_CLK 123
|
||||
#define GCC_VFE1_TBU_CLK 124
|
||||
#define GCC_VFE_TBU_CLK 125
|
||||
#define GCC_APS_0_CLK 126
|
||||
#define GCC_APS_1_CLK 127
|
||||
#define APS_0_CLK_SRC 128
|
||||
#define APS_1_CLK_SRC 129
|
||||
#define APSS_AHB_CLK_SRC 130
|
||||
#define BLSP1_QUP1_I2C_APPS_CLK_SRC 131
|
||||
#define BLSP1_QUP1_SPI_APPS_CLK_SRC 132
|
||||
#define BLSP1_QUP2_I2C_APPS_CLK_SRC 133
|
||||
#define BLSP1_QUP2_SPI_APPS_CLK_SRC 134
|
||||
#define BLSP1_QUP3_I2C_APPS_CLK_SRC 135
|
||||
#define BLSP1_QUP3_SPI_APPS_CLK_SRC 136
|
||||
#define BLSP1_QUP4_I2C_APPS_CLK_SRC 137
|
||||
#define BLSP1_QUP4_SPI_APPS_CLK_SRC 138
|
||||
#define BLSP1_UART1_APPS_CLK_SRC 139
|
||||
#define BLSP1_UART2_APPS_CLK_SRC 140
|
||||
#define BLSP2_QUP1_I2C_APPS_CLK_SRC 141
|
||||
#define BLSP2_QUP1_SPI_APPS_CLK_SRC 142
|
||||
#define BLSP2_QUP2_I2C_APPS_CLK_SRC 143
|
||||
#define BLSP2_QUP2_SPI_APPS_CLK_SRC 144
|
||||
#define BLSP2_QUP3_I2C_APPS_CLK_SRC 145
|
||||
#define BLSP2_QUP3_SPI_APPS_CLK_SRC 146
|
||||
#define BLSP2_QUP4_I2C_APPS_CLK_SRC 147
|
||||
#define BLSP2_QUP4_SPI_APPS_CLK_SRC 148
|
||||
#define BLSP2_UART1_APPS_CLK_SRC 149
|
||||
#define BLSP2_UART2_APPS_CLK_SRC 150
|
||||
#define CCI_CLK_SRC 151
|
||||
#define CPP_CLK_SRC 152
|
||||
#define CSI0_CLK_SRC 153
|
||||
#define CSI1_CLK_SRC 154
|
||||
#define CSI2_CLK_SRC 155
|
||||
#define CAMSS_GP0_CLK_SRC 156
|
||||
#define CAMSS_GP1_CLK_SRC 157
|
||||
#define JPEG0_CLK_SRC 158
|
||||
#define MCLK0_CLK_SRC 159
|
||||
#define MCLK1_CLK_SRC 160
|
||||
#define MCLK2_CLK_SRC 161
|
||||
#define CSI0PHYTIMER_CLK_SRC 162
|
||||
#define CSI1PHYTIMER_CLK_SRC 163
|
||||
#define CAMSS_TOP_AHB_CLK_SRC 164
|
||||
#define VFE0_CLK_SRC 165
|
||||
#define VFE1_CLK_SRC 166
|
||||
#define CRYPTO_CLK_SRC 167
|
||||
#define GP1_CLK_SRC 168
|
||||
#define GP2_CLK_SRC 169
|
||||
#define GP3_CLK_SRC 170
|
||||
#define ESC0_CLK_SRC 171
|
||||
#define ESC1_CLK_SRC 172
|
||||
#define MDP_CLK_SRC 173
|
||||
#define VSYNC_CLK_SRC 174
|
||||
#define PDM2_CLK_SRC 175
|
||||
#define RBCPR_GFX_CLK_SRC 176
|
||||
#define SDCC1_APPS_CLK_SRC 177
|
||||
#define SDCC1_ICE_CORE_CLK_SRC 178
|
||||
#define SDCC2_APPS_CLK_SRC 179
|
||||
#define SDCC3_APPS_CLK_SRC 180
|
||||
#define USB_FS_IC_CLK_SRC 181
|
||||
#define USB_FS_SYSTEM_CLK_SRC 182
|
||||
#define USB_HS_SYSTEM_CLK_SRC 183
|
||||
#define VCODEC0_CLK_SRC 184
|
||||
#define GCC_MDSS_BYTE0_CLK_SRC 185
|
||||
#define GCC_MDSS_BYTE1_CLK_SRC 186
|
||||
#define GCC_MDSS_BYTE0_CLK 187
|
||||
#define GCC_MDSS_BYTE1_CLK 188
|
||||
#define GCC_MDSS_PCLK0_CLK_SRC 189
|
||||
#define GCC_MDSS_PCLK1_CLK_SRC 190
|
||||
#define GCC_MDSS_PCLK0_CLK 191
|
||||
#define GCC_MDSS_PCLK1_CLK 192
|
||||
#define GCC_GFX3D_CLK_SRC 193
|
||||
#define GCC_GFX3D_OXILI_CLK 194
|
||||
#define GCC_GFX3D_BIMC_CLK 195
|
||||
#define GCC_GFX3D_OXILI_AHB_CLK 196
|
||||
#define GCC_GFX3D_OXILI_AON_CLK 197
|
||||
#define GCC_GFX3D_OXILI_GMEM_CLK 198
|
||||
#define GCC_GFX3D_OXILI_TIMER_CLK 199
|
||||
#define GCC_GFX3D_TBU0_CLK 200
|
||||
#define GCC_GFX3D_TBU1_CLK 201
|
||||
#define GCC_GFX3D_TCU_CLK 202
|
||||
#define GCC_GFX3D_GTCU_AHB_CLK 203
|
||||
|
||||
/* GCC block resets */
|
||||
#define RST_CAMSS_MICRO_BCR 0
|
||||
#define RST_USB_HS_BCR 1
|
||||
#define RST_QUSB2_PHY_BCR 2
|
||||
#define RST_USB2_HS_PHY_ONLY_BCR 3
|
||||
#define RST_USB_HS_PHY_CFG_AHB_BCR 4
|
||||
#define RST_USB_FS_BCR 5
|
||||
#define RST_CAMSS_CSI1PIX_BCR 6
|
||||
#define RST_CAMSS_CSI_VFE1_BCR 7
|
||||
#define RST_CAMSS_VFE1_BCR 8
|
||||
#define RST_CAMSS_CPP_BCR 9
|
||||
|
||||
/* GDSCs */
|
||||
#define VENUS_GDSC 0
|
||||
#define VENUS_CORE0_GDSC 1
|
||||
#define VENUS_CORE1_GDSC 2
|
||||
#define MDSS_GDSC 3
|
||||
#define JPEG_GDSC 4
|
||||
#define VFE0_GDSC 5
|
||||
#define VFE1_GDSC 6
|
||||
#define CPP_GDSC 7
|
||||
#define OXILI_GX_GDSC 8
|
||||
#define OXILI_CX_GDSC 9
|
||||
|
||||
#endif /* _DT_BINDINGS_CLK_MSM_GCC_8976_H */
|
||||
|
|
@ -0,0 +1,122 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SDX65_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_GCC_SDX65_H
|
||||
|
||||
/* GCC clocks */
|
||||
#define GPLL0 0
|
||||
#define GPLL0_OUT_EVEN 1
|
||||
#define GCC_AHB_PCIE_LINK_CLK 2
|
||||
#define GCC_BLSP1_AHB_CLK 3
|
||||
#define GCC_BLSP1_QUP1_I2C_APPS_CLK 4
|
||||
#define GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC 5
|
||||
#define GCC_BLSP1_QUP1_SPI_APPS_CLK 6
|
||||
#define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC 7
|
||||
#define GCC_BLSP1_QUP2_I2C_APPS_CLK 8
|
||||
#define GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC 9
|
||||
#define GCC_BLSP1_QUP2_SPI_APPS_CLK 10
|
||||
#define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC 11
|
||||
#define GCC_BLSP1_QUP3_I2C_APPS_CLK 12
|
||||
#define GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC 13
|
||||
#define GCC_BLSP1_QUP3_SPI_APPS_CLK 14
|
||||
#define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC 15
|
||||
#define GCC_BLSP1_QUP4_I2C_APPS_CLK 16
|
||||
#define GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC 17
|
||||
#define GCC_BLSP1_QUP4_SPI_APPS_CLK 18
|
||||
#define GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC 19
|
||||
#define GCC_BLSP1_SLEEP_CLK 20
|
||||
#define GCC_BLSP1_UART1_APPS_CLK 21
|
||||
#define GCC_BLSP1_UART1_APPS_CLK_SRC 22
|
||||
#define GCC_BLSP1_UART2_APPS_CLK 23
|
||||
#define GCC_BLSP1_UART2_APPS_CLK_SRC 24
|
||||
#define GCC_BLSP1_UART3_APPS_CLK 25
|
||||
#define GCC_BLSP1_UART3_APPS_CLK_SRC 26
|
||||
#define GCC_BLSP1_UART4_APPS_CLK 27
|
||||
#define GCC_BLSP1_UART4_APPS_CLK_SRC 28
|
||||
#define GCC_BOOT_ROM_AHB_CLK 29
|
||||
#define GCC_CPUSS_AHB_CLK 30
|
||||
#define GCC_CPUSS_AHB_CLK_SRC 31
|
||||
#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 32
|
||||
#define GCC_CPUSS_GNOC_CLK 33
|
||||
#define GCC_GP1_CLK 34
|
||||
#define GCC_GP1_CLK_SRC 35
|
||||
#define GCC_GP2_CLK 36
|
||||
#define GCC_GP2_CLK_SRC 37
|
||||
#define GCC_GP3_CLK 38
|
||||
#define GCC_GP3_CLK_SRC 39
|
||||
#define GCC_PCIE_0_CLKREF_EN 40
|
||||
#define GCC_PCIE_AUX_CLK 41
|
||||
#define GCC_PCIE_AUX_CLK_SRC 42
|
||||
#define GCC_PCIE_AUX_PHY_CLK_SRC 43
|
||||
#define GCC_PCIE_CFG_AHB_CLK 44
|
||||
#define GCC_PCIE_MSTR_AXI_CLK 45
|
||||
#define GCC_PCIE_PIPE_CLK 46
|
||||
#define GCC_PCIE_PIPE_CLK_SRC 47
|
||||
#define GCC_PCIE_RCHNG_PHY_CLK 48
|
||||
#define GCC_PCIE_RCHNG_PHY_CLK_SRC 49
|
||||
#define GCC_PCIE_SLEEP_CLK 50
|
||||
#define GCC_PCIE_SLV_AXI_CLK 51
|
||||
#define GCC_PCIE_SLV_Q2A_AXI_CLK 52
|
||||
#define GCC_PDM2_CLK 53
|
||||
#define GCC_PDM2_CLK_SRC 54
|
||||
#define GCC_PDM_AHB_CLK 55
|
||||
#define GCC_PDM_XO4_CLK 56
|
||||
#define GCC_RX1_USB2_CLKREF_EN 57
|
||||
#define GCC_SDCC1_AHB_CLK 58
|
||||
#define GCC_SDCC1_APPS_CLK 59
|
||||
#define GCC_SDCC1_APPS_CLK_SRC 60
|
||||
#define GCC_SPMI_FETCHER_AHB_CLK 61
|
||||
#define GCC_SPMI_FETCHER_CLK 62
|
||||
#define GCC_SPMI_FETCHER_CLK_SRC 63
|
||||
#define GCC_SYS_NOC_CPUSS_AHB_CLK 64
|
||||
#define GCC_USB30_MASTER_CLK 65
|
||||
#define GCC_USB30_MASTER_CLK_SRC 66
|
||||
#define GCC_USB30_MOCK_UTMI_CLK 67
|
||||
#define GCC_USB30_MOCK_UTMI_CLK_SRC 68
|
||||
#define GCC_USB30_MOCK_UTMI_POSTDIV_CLK_SRC 69
|
||||
#define GCC_USB30_MSTR_AXI_CLK 70
|
||||
#define GCC_USB30_SLEEP_CLK 71
|
||||
#define GCC_USB30_SLV_AHB_CLK 72
|
||||
#define GCC_USB3_PHY_AUX_CLK 73
|
||||
#define GCC_USB3_PHY_AUX_CLK_SRC 74
|
||||
#define GCC_USB3_PHY_PIPE_CLK 75
|
||||
#define GCC_USB3_PHY_PIPE_CLK_SRC 76
|
||||
#define GCC_USB3_PRIM_CLKREF_EN 77
|
||||
#define GCC_USB_PHY_CFG_AHB2PHY_CLK 78
|
||||
#define GCC_XO_DIV4_CLK 79
|
||||
#define GCC_XO_PCIE_LINK_CLK 80
|
||||
|
||||
/* GCC resets */
|
||||
#define GCC_BLSP1_QUP1_BCR 0
|
||||
#define GCC_BLSP1_QUP2_BCR 1
|
||||
#define GCC_BLSP1_QUP3_BCR 2
|
||||
#define GCC_BLSP1_QUP4_BCR 3
|
||||
#define GCC_BLSP1_UART1_BCR 4
|
||||
#define GCC_BLSP1_UART2_BCR 5
|
||||
#define GCC_BLSP1_UART3_BCR 6
|
||||
#define GCC_BLSP1_UART4_BCR 7
|
||||
#define GCC_PCIE_BCR 8
|
||||
#define GCC_PCIE_LINK_DOWN_BCR 9
|
||||
#define GCC_PCIE_NOCSR_COM_PHY_BCR 10
|
||||
#define GCC_PCIE_PHY_BCR 11
|
||||
#define GCC_PCIE_PHY_CFG_AHB_BCR 12
|
||||
#define GCC_PCIE_PHY_COM_BCR 13
|
||||
#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR 14
|
||||
#define GCC_PDM_BCR 15
|
||||
#define GCC_QUSB2PHY_BCR 16
|
||||
#define GCC_SDCC1_BCR 17
|
||||
#define GCC_SPMI_FETCHER_BCR 18
|
||||
#define GCC_TCSR_PCIE_BCR 19
|
||||
#define GCC_USB30_BCR 20
|
||||
#define GCC_USB3_PHY_BCR 21
|
||||
#define GCC_USB3PHY_PHY_BCR 22
|
||||
#define GCC_USB_PHY_CFG_AHB2PHY_BCR 23
|
||||
|
||||
/* GCC power domains */
|
||||
#define USB30_GDSC 0
|
||||
#define PCIE_GDSC 1
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,244 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2021, Linaro Limited
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8450_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_GCC_SM8450_H
|
||||
|
||||
/* GCC HW clocks */
|
||||
#define CORE_BI_PLL_TEST_SE 0
|
||||
#define PCIE_0_PIPE_CLK 1
|
||||
#define PCIE_1_PHY_AUX_CLK 2
|
||||
#define PCIE_1_PIPE_CLK 3
|
||||
#define UFS_PHY_RX_SYMBOL_0_CLK 4
|
||||
#define UFS_PHY_RX_SYMBOL_1_CLK 5
|
||||
#define UFS_PHY_TX_SYMBOL_0_CLK 6
|
||||
#define USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK 7
|
||||
|
||||
/* GCC clocks */
|
||||
#define GCC_AGGRE_NOC_PCIE_0_AXI_CLK 8
|
||||
#define GCC_AGGRE_NOC_PCIE_1_AXI_CLK 9
|
||||
#define GCC_AGGRE_UFS_PHY_AXI_CLK 10
|
||||
#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 11
|
||||
#define GCC_AGGRE_USB3_PRIM_AXI_CLK 12
|
||||
#define GCC_ANOC_PCIE_PWRCTL_CLK 13
|
||||
#define GCC_BOOT_ROM_AHB_CLK 14
|
||||
#define GCC_CAMERA_AHB_CLK 15
|
||||
#define GCC_CAMERA_HF_AXI_CLK 16
|
||||
#define GCC_CAMERA_SF_AXI_CLK 17
|
||||
#define GCC_CAMERA_XO_CLK 18
|
||||
#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 19
|
||||
#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 20
|
||||
#define GCC_CPUSS_AHB_CLK 21
|
||||
#define GCC_CPUSS_AHB_CLK_SRC 22
|
||||
#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 23
|
||||
#define GCC_CPUSS_CONFIG_NOC_SF_CLK 24
|
||||
#define GCC_DDRSS_GPU_AXI_CLK 25
|
||||
#define GCC_DDRSS_PCIE_SF_TBU_CLK 26
|
||||
#define GCC_DISP_AHB_CLK 27
|
||||
#define GCC_DISP_HF_AXI_CLK 28
|
||||
#define GCC_DISP_SF_AXI_CLK 29
|
||||
#define GCC_DISP_XO_CLK 30
|
||||
#define GCC_EUSB3_0_CLKREF_EN 31
|
||||
#define GCC_GP1_CLK 32
|
||||
#define GCC_GP1_CLK_SRC 33
|
||||
#define GCC_GP2_CLK 34
|
||||
#define GCC_GP2_CLK_SRC 35
|
||||
#define GCC_GP3_CLK 36
|
||||
#define GCC_GP3_CLK_SRC 37
|
||||
#define GCC_GPLL0 38
|
||||
#define GCC_GPLL0_OUT_EVEN 39
|
||||
#define GCC_GPLL4 40
|
||||
#define GCC_GPLL9 41
|
||||
#define GCC_GPU_CFG_AHB_CLK 42
|
||||
#define GCC_GPU_GPLL0_CLK_SRC 43
|
||||
#define GCC_GPU_GPLL0_DIV_CLK_SRC 44
|
||||
#define GCC_GPU_MEMNOC_GFX_CLK 45
|
||||
#define GCC_GPU_SNOC_DVM_GFX_CLK 46
|
||||
#define GCC_PCIE_0_AUX_CLK 47
|
||||
#define GCC_PCIE_0_AUX_CLK_SRC 48
|
||||
#define GCC_PCIE_0_CFG_AHB_CLK 49
|
||||
#define GCC_PCIE_0_CLKREF_EN 50
|
||||
#define GCC_PCIE_0_MSTR_AXI_CLK 51
|
||||
#define GCC_PCIE_0_PHY_RCHNG_CLK 52
|
||||
#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 53
|
||||
#define GCC_PCIE_0_PIPE_CLK 54
|
||||
#define GCC_PCIE_0_PIPE_CLK_SRC 55
|
||||
#define GCC_PCIE_0_SLV_AXI_CLK 56
|
||||
#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 57
|
||||
#define GCC_PCIE_1_AUX_CLK 58
|
||||
#define GCC_PCIE_1_AUX_CLK_SRC 59
|
||||
#define GCC_PCIE_1_CFG_AHB_CLK 60
|
||||
#define GCC_PCIE_1_CLKREF_EN 61
|
||||
#define GCC_PCIE_1_MSTR_AXI_CLK 62
|
||||
#define GCC_PCIE_1_PHY_AUX_CLK 63
|
||||
#define GCC_PCIE_1_PHY_AUX_CLK_SRC 64
|
||||
#define GCC_PCIE_1_PHY_RCHNG_CLK 65
|
||||
#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 66
|
||||
#define GCC_PCIE_1_PIPE_CLK 67
|
||||
#define GCC_PCIE_1_PIPE_CLK_SRC 68
|
||||
#define GCC_PCIE_1_SLV_AXI_CLK 69
|
||||
#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 70
|
||||
#define GCC_PDM2_CLK 71
|
||||
#define GCC_PDM2_CLK_SRC 72
|
||||
#define GCC_PDM_AHB_CLK 73
|
||||
#define GCC_PDM_XO4_CLK 74
|
||||
#define GCC_QMIP_CAMERA_NRT_AHB_CLK 75
|
||||
#define GCC_QMIP_CAMERA_RT_AHB_CLK 76
|
||||
#define GCC_QMIP_DISP_AHB_CLK 77
|
||||
#define GCC_QMIP_GPU_AHB_CLK 78
|
||||
#define GCC_QMIP_PCIE_AHB_CLK 79
|
||||
#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK 80
|
||||
#define GCC_QMIP_VIDEO_CVP_AHB_CLK 81
|
||||
#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 82
|
||||
#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 83
|
||||
#define GCC_QUPV3_WRAP0_CORE_2X_CLK 84
|
||||
#define GCC_QUPV3_WRAP0_CORE_CLK 85
|
||||
#define GCC_QUPV3_WRAP0_S0_CLK 86
|
||||
#define GCC_QUPV3_WRAP0_S0_CLK_SRC 87
|
||||
#define GCC_QUPV3_WRAP0_S1_CLK 88
|
||||
#define GCC_QUPV3_WRAP0_S1_CLK_SRC 89
|
||||
#define GCC_QUPV3_WRAP0_S2_CLK 90
|
||||
#define GCC_QUPV3_WRAP0_S2_CLK_SRC 91
|
||||
#define GCC_QUPV3_WRAP0_S3_CLK 92
|
||||
#define GCC_QUPV3_WRAP0_S3_CLK_SRC 93
|
||||
#define GCC_QUPV3_WRAP0_S4_CLK 94
|
||||
#define GCC_QUPV3_WRAP0_S4_CLK_SRC 95
|
||||
#define GCC_QUPV3_WRAP0_S5_CLK 96
|
||||
#define GCC_QUPV3_WRAP0_S5_CLK_SRC 97
|
||||
#define GCC_QUPV3_WRAP0_S6_CLK 98
|
||||
#define GCC_QUPV3_WRAP0_S6_CLK_SRC 99
|
||||
#define GCC_QUPV3_WRAP0_S7_CLK 100
|
||||
#define GCC_QUPV3_WRAP0_S7_CLK_SRC 101
|
||||
#define GCC_QUPV3_WRAP1_CORE_2X_CLK 102
|
||||
#define GCC_QUPV3_WRAP1_CORE_CLK 103
|
||||
#define GCC_QUPV3_WRAP1_S0_CLK 104
|
||||
#define GCC_QUPV3_WRAP1_S0_CLK_SRC 105
|
||||
#define GCC_QUPV3_WRAP1_S1_CLK 106
|
||||
#define GCC_QUPV3_WRAP1_S1_CLK_SRC 107
|
||||
#define GCC_QUPV3_WRAP1_S2_CLK 108
|
||||
#define GCC_QUPV3_WRAP1_S2_CLK_SRC 109
|
||||
#define GCC_QUPV3_WRAP1_S3_CLK 110
|
||||
#define GCC_QUPV3_WRAP1_S3_CLK_SRC 111
|
||||
#define GCC_QUPV3_WRAP1_S4_CLK 112
|
||||
#define GCC_QUPV3_WRAP1_S4_CLK_SRC 113
|
||||
#define GCC_QUPV3_WRAP1_S5_CLK 114
|
||||
#define GCC_QUPV3_WRAP1_S5_CLK_SRC 115
|
||||
#define GCC_QUPV3_WRAP1_S6_CLK 116
|
||||
#define GCC_QUPV3_WRAP1_S6_CLK_SRC 117
|
||||
#define GCC_QUPV3_WRAP2_CORE_2X_CLK 118
|
||||
#define GCC_QUPV3_WRAP2_CORE_CLK 119
|
||||
#define GCC_QUPV3_WRAP2_S0_CLK 120
|
||||
#define GCC_QUPV3_WRAP2_S0_CLK_SRC 121
|
||||
#define GCC_QUPV3_WRAP2_S1_CLK 122
|
||||
#define GCC_QUPV3_WRAP2_S1_CLK_SRC 123
|
||||
#define GCC_QUPV3_WRAP2_S2_CLK 124
|
||||
#define GCC_QUPV3_WRAP2_S2_CLK_SRC 125
|
||||
#define GCC_QUPV3_WRAP2_S3_CLK 126
|
||||
#define GCC_QUPV3_WRAP2_S3_CLK_SRC 127
|
||||
#define GCC_QUPV3_WRAP2_S4_CLK 128
|
||||
#define GCC_QUPV3_WRAP2_S4_CLK_SRC 129
|
||||
#define GCC_QUPV3_WRAP2_S5_CLK 130
|
||||
#define GCC_QUPV3_WRAP2_S5_CLK_SRC 131
|
||||
#define GCC_QUPV3_WRAP2_S6_CLK 132
|
||||
#define GCC_QUPV3_WRAP2_S6_CLK_SRC 133
|
||||
#define GCC_QUPV3_WRAP_0_M_AHB_CLK 134
|
||||
#define GCC_QUPV3_WRAP_0_S_AHB_CLK 135
|
||||
#define GCC_QUPV3_WRAP_1_M_AHB_CLK 136
|
||||
#define GCC_QUPV3_WRAP_1_S_AHB_CLK 137
|
||||
#define GCC_QUPV3_WRAP_2_M_AHB_CLK 138
|
||||
#define GCC_QUPV3_WRAP_2_S_AHB_CLK 139
|
||||
#define GCC_SDCC2_AHB_CLK 140
|
||||
#define GCC_SDCC2_APPS_CLK 141
|
||||
#define GCC_SDCC2_APPS_CLK_SRC 142
|
||||
#define GCC_SDCC2_AT_CLK 143
|
||||
#define GCC_SDCC4_AHB_CLK 144
|
||||
#define GCC_SDCC4_APPS_CLK 145
|
||||
#define GCC_SDCC4_APPS_CLK_SRC 146
|
||||
#define GCC_SDCC4_AT_CLK 147
|
||||
#define GCC_SYS_NOC_CPUSS_AHB_CLK 148
|
||||
#define GCC_UFS_0_CLKREF_EN 149
|
||||
#define GCC_UFS_PHY_AHB_CLK 150
|
||||
#define GCC_UFS_PHY_AXI_CLK 151
|
||||
#define GCC_UFS_PHY_AXI_CLK_SRC 152
|
||||
#define GCC_UFS_PHY_AXI_HW_CTL_CLK 153
|
||||
#define GCC_UFS_PHY_ICE_CORE_CLK 154
|
||||
#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 155
|
||||
#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 156
|
||||
#define GCC_UFS_PHY_PHY_AUX_CLK 157
|
||||
#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 158
|
||||
#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 159
|
||||
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 160
|
||||
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 161
|
||||
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 162
|
||||
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 163
|
||||
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 164
|
||||
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 165
|
||||
#define GCC_UFS_PHY_UNIPRO_CORE_CLK 166
|
||||
#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 167
|
||||
#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 168
|
||||
#define GCC_USB30_PRIM_MASTER_CLK 169
|
||||
#define GCC_USB30_PRIM_MASTER_CLK_SRC 170
|
||||
#define GCC_USB30_PRIM_MOCK_UTMI_CLK 171
|
||||
#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 172
|
||||
#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 173
|
||||
#define GCC_USB30_PRIM_SLEEP_CLK 174
|
||||
#define GCC_USB3_0_CLKREF_EN 175
|
||||
#define GCC_USB3_PRIM_PHY_AUX_CLK 176
|
||||
#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 177
|
||||
#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 178
|
||||
#define GCC_USB3_PRIM_PHY_PIPE_CLK 179
|
||||
#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 180
|
||||
#define GCC_VIDEO_AHB_CLK 181
|
||||
#define GCC_VIDEO_AXI0_CLK 182
|
||||
#define GCC_VIDEO_AXI1_CLK 183
|
||||
#define GCC_VIDEO_XO_CLK 184
|
||||
|
||||
/* GCC resets */
|
||||
#define GCC_CAMERA_BCR 0
|
||||
#define GCC_DISPLAY_BCR 1
|
||||
#define GCC_GPU_BCR 2
|
||||
#define GCC_MMSS_BCR 3
|
||||
#define GCC_PCIE_0_BCR 4
|
||||
#define GCC_PCIE_0_LINK_DOWN_BCR 5
|
||||
#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 6
|
||||
#define GCC_PCIE_0_PHY_BCR 7
|
||||
#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 8
|
||||
#define GCC_PCIE_1_BCR 9
|
||||
#define GCC_PCIE_1_LINK_DOWN_BCR 10
|
||||
#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 11
|
||||
#define GCC_PCIE_1_PHY_BCR 12
|
||||
#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 13
|
||||
#define GCC_PCIE_PHY_BCR 14
|
||||
#define GCC_PCIE_PHY_CFG_AHB_BCR 15
|
||||
#define GCC_PCIE_PHY_COM_BCR 16
|
||||
#define GCC_PDM_BCR 17
|
||||
#define GCC_QUPV3_WRAPPER_0_BCR 18
|
||||
#define GCC_QUPV3_WRAPPER_1_BCR 19
|
||||
#define GCC_QUPV3_WRAPPER_2_BCR 20
|
||||
#define GCC_QUSB2PHY_PRIM_BCR 21
|
||||
#define GCC_QUSB2PHY_SEC_BCR 22
|
||||
#define GCC_SDCC2_BCR 23
|
||||
#define GCC_SDCC4_BCR 24
|
||||
#define GCC_UFS_PHY_BCR 25
|
||||
#define GCC_USB30_PRIM_BCR 26
|
||||
#define GCC_USB3_DP_PHY_PRIM_BCR 27
|
||||
#define GCC_USB3_DP_PHY_SEC_BCR 28
|
||||
#define GCC_USB3_PHY_PRIM_BCR 29
|
||||
#define GCC_USB3_PHY_SEC_BCR 30
|
||||
#define GCC_USB3PHY_PHY_PRIM_BCR 31
|
||||
#define GCC_USB3PHY_PHY_SEC_BCR 32
|
||||
#define GCC_USB_PHY_CFG_AHB2PHY_BCR 33
|
||||
#define GCC_VIDEO_AXI0_CLK_ARES 34
|
||||
#define GCC_VIDEO_AXI1_CLK_ARES 35
|
||||
#define GCC_VIDEO_BCR 36
|
||||
|
||||
/* GCC power domains */
|
||||
#define PCIE_0_GDSC 0
|
||||
#define PCIE_1_GDSC 1
|
||||
#define UFS_PHY_GDSC 2
|
||||
#define USB30_PRIM_GDSC 3
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue