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perf vendor events intel: Update goldmont event topics 

Apply topic updates from:

https://github.com/intel/event-converter-for-linux-perf/

Signed-off-by: Ian Rogers <irogers@google.com>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.garry@huawei.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20220413210503.3256922-14-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Ian Rogers 2022-04-13 14:05:03 -07:00 committed by Arnaldo Carvalho de Melo
parent f51c401f11
commit 87e0a30e9a
2 changed files with 31 additions and 31 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

31
tools/perf/pmu-events/arch/x86/goldmont/other.json
View File

@ -47,34 +47,5 @@
"PublicDescription": "Counts hardware interrupts received by the processor.",
"SampleAfterValue": "203",
"UMask": "0x1"
},
{
"BriefDescription": "Unfilled issue slots per cycle",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0xCA",
"EventName": "ISSUE_SLOTS_NOT_CONSUMED.ANY",
"PublicDescription": "Counts the number of issue slots per core cycle that were not consumed by the backend due to either a full resource in the backend (RESOURCE_FULL) or due to the processor recovering from some event (RECOVERY).",
"SampleAfterValue": "200003"
},
{
"BriefDescription": "Unfilled issue slots per cycle to recover",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0xCA",
"EventName": "ISSUE_SLOTS_NOT_CONSUMED.RECOVERY",
"PublicDescription": "Counts the number of issue slots per core cycle that were not consumed by the backend because allocation is stalled waiting for a mispredicted jump to retire or other branch-like conditions (e.g. the event is relevant during certain microcode flows). Counts all issue slots blocked while within this window including slots where uops were not available in the Instruction Queue.",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Unfilled issue slots per cycle because of a full resource in the backend",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0xCA",
"EventName": "ISSUE_SLOTS_NOT_CONSUMED.RESOURCE_FULL",
"PublicDescription": "Counts the number of issue slots per core cycle that were not consumed because of a full resource in the backend. Including but not limited to resources such as the Re-order Buffer (ROB), reservation stations (RS), load/store buffers, physical registers, or any other needed machine resource that is currently unavailable. Note that uops must be available for consumption in order for this event to fire. If a uop is not available (Instruction Queue is empty), this event will not count.",
"SampleAfterValue": "200003",
"UMask": "0x1"
}
]
]

31
tools/perf/pmu-events/arch/x86/goldmont/pipeline.json
View File

@ -245,6 +245,35 @@
"PublicDescription": "Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The event continues counting during hardware interrupts, traps, and inside interrupt handlers. This is an architectural performance event. This event uses a (_P)rogrammable general purpose performance counter. *This event is Precise Event capable: The EventingRIP field in the PEBS record is precise to the address of the instruction which caused the event. Note: Because PEBS records can be collected only on IA32_PMC0, only one event can use the PEBS facility at a time.",
"SampleAfterValue": "2000003"
},
{
"BriefDescription": "Unfilled issue slots per cycle",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0xCA",
"EventName": "ISSUE_SLOTS_NOT_CONSUMED.ANY",
"PublicDescription": "Counts the number of issue slots per core cycle that were not consumed by the backend due to either a full resource in the backend (RESOURCE_FULL) or due to the processor recovering from some event (RECOVERY).",
"SampleAfterValue": "200003"
},
{
"BriefDescription": "Unfilled issue slots per cycle to recover",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0xCA",
"EventName": "ISSUE_SLOTS_NOT_CONSUMED.RECOVERY",
"PublicDescription": "Counts the number of issue slots per core cycle that were not consumed by the backend because allocation is stalled waiting for a mispredicted jump to retire or other branch-like conditions (e.g. the event is relevant during certain microcode flows). Counts all issue slots blocked while within this window including slots where uops were not available in the Instruction Queue.",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Unfilled issue slots per cycle because of a full resource in the backend",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0xCA",
"EventName": "ISSUE_SLOTS_NOT_CONSUMED.RESOURCE_FULL",
"PublicDescription": "Counts the number of issue slots per core cycle that were not consumed because of a full resource in the backend. Including but not limited to resources such as the Re-order Buffer (ROB), reservation stations (RS), load/store buffers, physical registers, or any other needed machine resource that is currently unavailable. Note that uops must be available for consumption in order for this event to fire. If a uop is not available (Instruction Queue is empty), this event will not count.",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "Loads blocked because address has 4k partial address false dependence (Precise event capable)",
"CollectPEBSRecord": "2",
@ -379,4 +408,4 @@
"SampleAfterValue": "2000003",
"UMask": "0x1"
}
]
]