net: phy: consolidate PHY reset in phy_init_hw()
There are quite a lot of drivers touching a PHY device MII_BMCR register to reset the PHY without taking care of: 1) ensuring that BMCR_RESET is cleared after a given timeout 2) the PHY state machine resuming to the proper state and re-applying potentially changed settings such as auto-negotiation Introduce phy_poll_reset() which will take care of polling the MII_BMCR for the BMCR_RESET bit to be cleared after a given timeout or return a timeout error code. In order to make sure the PHY is in a correct state, phy_init_hw() first issues a software reset through MII_BMCR and then applies any fixups. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -255,7 +255,8 @@ Writing a PHY driver
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config_init: configures PHY into a sane state after a reset.
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config_init: configures PHY into a sane state after a reset.
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For instance, a Davicom PHY requires descrambling disabled.
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For instance, a Davicom PHY requires descrambling disabled.
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probe: Does any setup needed by the driver
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probe: Allocate phy->priv, optionally refuse to bind.
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PHY may not have been reset or had fixups run yet.
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suspend/resume: power management
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suspend/resume: power management
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config_aneg: Changes the speed/duplex/negotiation settings
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config_aneg: Changes the speed/duplex/negotiation settings
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read_status: Reads the current speed/duplex/negotiation settings
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read_status: Reads the current speed/duplex/negotiation settings
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@ -318,6 +318,7 @@ int phy_mii_ioctl(struct phy_device *phydev,
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{
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{
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struct mii_ioctl_data *mii_data = if_mii(ifr);
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struct mii_ioctl_data *mii_data = if_mii(ifr);
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u16 val = mii_data->val_in;
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u16 val = mii_data->val_in;
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int ret = 0;
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switch (cmd) {
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switch (cmd) {
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case SIOCGMIIPHY:
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case SIOCGMIIPHY:
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@ -362,7 +363,7 @@ int phy_mii_ioctl(struct phy_device *phydev,
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if (mii_data->reg_num == MII_BMCR &&
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if (mii_data->reg_num == MII_BMCR &&
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val & BMCR_RESET)
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val & BMCR_RESET)
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phy_init_hw(phydev);
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ret = phy_init_hw(phydev);
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break;
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break;
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case SIOCSHWTSTAMP:
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case SIOCSHWTSTAMP:
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@ -374,7 +375,7 @@ int phy_mii_ioctl(struct phy_device *phydev,
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return -EOPNOTSUPP;
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return -EOPNOTSUPP;
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}
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}
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return 0;
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return ret;
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}
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}
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EXPORT_SYMBOL(phy_mii_ioctl);
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EXPORT_SYMBOL(phy_mii_ioctl);
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@ -364,7 +364,11 @@ int phy_device_register(struct phy_device *phydev)
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phydev->bus->phy_map[phydev->addr] = phydev;
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phydev->bus->phy_map[phydev->addr] = phydev;
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/* Run all of the fixups for this PHY */
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/* Run all of the fixups for this PHY */
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phy_scan_fixups(phydev);
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err = phy_init_hw(phydev);
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if (err) {
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pr_err("PHY %d failed to initialize\n", phydev->addr);
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goto out;
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}
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err = device_add(&phydev->dev);
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err = device_add(&phydev->dev);
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if (err) {
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if (err) {
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@ -497,6 +501,47 @@ void phy_disconnect(struct phy_device *phydev)
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}
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}
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EXPORT_SYMBOL(phy_disconnect);
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EXPORT_SYMBOL(phy_disconnect);
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/**
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* phy_poll_reset - Safely wait until a PHY reset has properly completed
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* @phydev: The PHY device to poll
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*
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* Description: According to IEEE 802.3, Section 2, Subsection 22.2.4.1.1, as
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* published in 2008, a PHY reset may take up to 0.5 seconds. The MII BMCR
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* register must be polled until the BMCR_RESET bit clears.
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*
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* Furthermore, any attempts to write to PHY registers may have no effect
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* or even generate MDIO bus errors until this is complete.
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*
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* Some PHYs (such as the Marvell 88E1111) don't entirely conform to the
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* standard and do not fully reset after the BMCR_RESET bit is set, and may
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* even *REQUIRE* a soft-reset to properly restart autonegotiation. In an
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* effort to support such broken PHYs, this function is separate from the
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* standard phy_init_hw() which will zero all the other bits in the BMCR
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* and reapply all driver-specific and board-specific fixups.
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*/
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static int phy_poll_reset(struct phy_device *phydev)
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{
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/* Poll until the reset bit clears (50ms per retry == 0.6 sec) */
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unsigned int retries = 12;
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int ret;
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do {
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msleep(50);
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ret = phy_read(phydev, MII_BMCR);
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if (ret < 0)
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return ret;
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} while (ret & BMCR_RESET && --retries);
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if (ret & BMCR_RESET)
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return -ETIMEDOUT;
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/*
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* Some chips (smsc911x) may still need up to another 1ms after the
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* BMCR_RESET bit is cleared before they are usable.
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*/
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msleep(1);
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return 0;
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}
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int phy_init_hw(struct phy_device *phydev)
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int phy_init_hw(struct phy_device *phydev)
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{
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{
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int ret;
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int ret;
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@ -504,12 +549,21 @@ int phy_init_hw(struct phy_device *phydev)
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if (!phydev->drv || !phydev->drv->config_init)
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if (!phydev->drv || !phydev->drv->config_init)
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return 0;
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return 0;
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ret = phy_write(phydev, MII_BMCR, BMCR_RESET);
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if (ret < 0)
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return ret;
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ret = phy_poll_reset(phydev);
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if (ret < 0)
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return ret;
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ret = phy_scan_fixups(phydev);
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ret = phy_scan_fixups(phydev);
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if (ret < 0)
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if (ret < 0)
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return ret;
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return ret;
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return phydev->drv->config_init(phydev);
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return phydev->drv->config_init(phydev);
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}
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}
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EXPORT_SYMBOL(phy_init_hw);
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/**
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/**
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* phy_attach_direct - attach a network device to a given PHY device pointer
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* phy_attach_direct - attach a network device to a given PHY device pointer
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