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ASoC: cs35l41: Set the max SPI speed for the whole device 

Higher speeds are only supported when PLL is enabled, but
the current driver doesn't enable PLL outside of stream
use cases, so better to set the lowest SPI speed accepted
by the entire device.

Move the current frequency set to the spi sub-driver so
the whole device can benefit from that speed.

spi-max-frequency property could be used, but ACPI systems don't
support it, so by setting it in the spi sub-driver probe
both Device Trees and ACPI systems are supported.

Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com>
Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20211123163149.1530535-2-tanureal@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Lucas Tanure 2021-11-23 16:31:39 +00:00 committed by Mark Brown
parent 8a6cc0ded6
commit 872fc0b6bd
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
3 changed files with 4 additions and 39 deletions
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32
sound/soc/codecs/cs35l41-spi.c
View File

@ -42,34 +42,6 @@ static const struct spi_device_id cs35l41_id_spi[] = {
MODULE_DEVICE_TABLE(spi, cs35l41_id_spi); MODULE_DEVICE_TABLE(spi, cs35l41_id_spi);
static void cs35l41_spi_otp_setup(struct cs35l41_private *cs35l41,
bool is_pre_setup, unsigned int *freq)
{
struct spi_device *spi;
u32 orig_spi_freq;
spi = to_spi_device(cs35l41->dev);
if (!spi) {
dev_err(cs35l41->dev, "%s: No SPI device\n", __func__);
return;
}
if (is_pre_setup) {
orig_spi_freq = spi->max_speed_hz;
if (orig_spi_freq > CS35L41_SPI_MAX_FREQ_OTP) {
spi->max_speed_hz = CS35L41_SPI_MAX_FREQ_OTP;
spi_setup(spi);
}
*freq = orig_spi_freq;
} else {
if (spi->max_speed_hz != *freq) {
spi->max_speed_hz = *freq;
spi_setup(spi);
}
}
}
static int cs35l41_spi_probe(struct spi_device *spi) static int cs35l41_spi_probe(struct spi_device *spi)
{ {
const struct regmap_config *regmap_config = &cs35l41_regmap_spi; const struct regmap_config *regmap_config = &cs35l41_regmap_spi;
@ -81,6 +53,9 @@ static int cs35l41_spi_probe(struct spi_device *spi)
if (!cs35l41) if (!cs35l41)
return -ENOMEM; return -ENOMEM;
spi->max_speed_hz = CS35L41_SPI_MAX_FREQ;
spi_setup(spi);
spi_set_drvdata(spi, cs35l41); spi_set_drvdata(spi, cs35l41);
cs35l41->regmap = devm_regmap_init_spi(spi, regmap_config); cs35l41->regmap = devm_regmap_init_spi(spi, regmap_config);
if (IS_ERR(cs35l41->regmap)) { if (IS_ERR(cs35l41->regmap)) {
@ -91,7 +66,6 @@ static int cs35l41_spi_probe(struct spi_device *spi)
cs35l41->dev = &spi->dev; cs35l41->dev = &spi->dev;
cs35l41->irq = spi->irq; cs35l41->irq = spi->irq;
cs35l41->otp_setup = cs35l41_spi_otp_setup;
return cs35l41_probe(cs35l41, pdata); return cs35l41_probe(cs35l41, pdata);
} }

7
sound/soc/codecs/cs35l41.c
View File

@ -302,7 +302,6 @@ static int cs35l41_otp_unpack(void *data)
const struct cs35l41_otp_packed_element_t *otp_map; const struct cs35l41_otp_packed_element_t *otp_map;
struct cs35l41_private *cs35l41 = data; struct cs35l41_private *cs35l41 = data;
int bit_offset, word_offset, ret, i; int bit_offset, word_offset, ret, i;
unsigned int orig_spi_freq;
unsigned int bit_sum = 8; unsigned int bit_sum = 8;
u32 otp_val, otp_id_reg; u32 otp_val, otp_id_reg;
u32 *otp_mem; u32 *otp_mem;
@ -326,9 +325,6 @@ static int cs35l41_otp_unpack(void *data)
goto err_otp_unpack; goto err_otp_unpack;
} }
if (cs35l41->otp_setup)
cs35l41->otp_setup(cs35l41, true, &orig_spi_freq);
ret = regmap_bulk_read(cs35l41->regmap, CS35L41_OTP_MEM0, otp_mem, ret = regmap_bulk_read(cs35l41->regmap, CS35L41_OTP_MEM0, otp_mem,
CS35L41_OTP_SIZE_WORDS); CS35L41_OTP_SIZE_WORDS);
if (ret < 0) { if (ret < 0) {
@ -336,9 +332,6 @@ static int cs35l41_otp_unpack(void *data)
goto err_otp_unpack; goto err_otp_unpack;
} }
if (cs35l41->otp_setup)
cs35l41->otp_setup(cs35l41, false, &orig_spi_freq);
otp_map = otp_map_match->map; otp_map = otp_map_match->map;
bit_offset = otp_map_match->bit_offset; bit_offset = otp_map_match->bit_offset;

4
sound/soc/codecs/cs35l41.h
View File

@ -726,7 +726,7 @@
#define CS35L41_FS2_WINDOW_MASK 0x00FFF800 #define CS35L41_FS2_WINDOW_MASK 0x00FFF800
#define CS35L41_FS2_WINDOW_SHIFT 12 #define CS35L41_FS2_WINDOW_SHIFT 12
#define CS35L41_SPI_MAX_FREQ_OTP 4000000 #define CS35L41_SPI_MAX_FREQ 4000000
#define CS35L41_RX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) #define CS35L41_RX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
#define CS35L41_TX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) #define CS35L41_TX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
@ -764,8 +764,6 @@ struct cs35l41_private {
int irq; int irq;
/* GPIO for /RST */ /* GPIO for /RST */
struct gpio_desc *reset_gpio; struct gpio_desc *reset_gpio;
void (*otp_setup)(struct cs35l41_private *cs35l41, bool is_pre_setup,
unsigned int *freq);
}; };
int cs35l41_probe(struct cs35l41_private *cs35l41, int cs35l41_probe(struct cs35l41_private *cs35l41,