misc: rtsx: rts522a rts5228 rts5261 support Runtime PM
rts522a, rts5228, rts5261 add extra init flow for rtd3 add more power_down setting for avoid being woken up by plugging or unplugging card when system in S3 Tested-by: Kai-Heng Feng <kai.heng.feng@canonical.com> Signed-off-by: Ricky Wu <ricky_wu@realtek.com> Link: https://lore.kernel.org/r/dace32f573a445908fec0a10482c394c@realtek.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -72,6 +72,8 @@ static void rts5227_fetch_vendor_settings(struct rtsx_pcr *pcr)
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pci_read_config_dword(pdev, PCR_SETTING_REG2, ®);
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pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
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if (CHK_PCI_PID(pcr, 0x522A))
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pcr->rtd3_en = rtsx_reg_to_rtd3(reg);
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if (rtsx_check_mmc_support(reg))
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pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
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pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
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@ -171,6 +173,28 @@ static int rts5227_extra_init_hw(struct rtsx_pcr *pcr)
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else
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x30, 0x00);
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if (CHK_PCI_PID(pcr, 0x522A))
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RTS522A_AUTOLOAD_CFG1,
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CD_RESUME_EN_MASK, CD_RESUME_EN_MASK);
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if (pcr->rtd3_en) {
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if (CHK_PCI_PID(pcr, 0x522A)) {
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RTS522A_PM_CTRL3, 0x01, 0x01);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RTS522A_PME_FORCE_CTL, 0x30, 0x30);
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} else {
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PM_CTRL3, 0x01, 0x01);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PME_FORCE_CTL, 0xFF, 0x33);
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}
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} else {
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if (CHK_PCI_PID(pcr, 0x522A)) {
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RTS522A_PM_CTRL3, 0x01, 0x00);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RTS522A_PME_FORCE_CTL, 0x30, 0x20);
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} else {
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PME_FORCE_CTL, 0xFF, 0x30);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PM_CTRL3, 0x01, 0x00);
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}
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}
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if (option->force_clkreq_0)
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,
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FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
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@ -438,6 +462,28 @@ static int rts522a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
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return rtsx_pci_send_cmd(pcr, 100);
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}
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static void rts522a_force_power_down(struct rtsx_pcr *pcr, u8 pm_state, bool runtime)
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{
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/* Set relink_time to 0 */
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rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);
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rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);
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rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3,
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RELINK_TIME_MASK, 0);
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rtsx_pci_write_register(pcr, RTS522A_PM_CTRL3,
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D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
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if (!runtime) {
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rtsx_pci_write_register(pcr, RTS522A_AUTOLOAD_CFG1,
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CD_RESUME_EN_MASK, 0);
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rtsx_pci_write_register(pcr, RTS522A_PM_CTRL3, 0x01, 0x00);
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rtsx_pci_write_register(pcr, RTS522A_PME_FORCE_CTL, 0x30, 0x20);
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}
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rtsx_pci_write_register(pcr, FPDCTL, ALL_POWER_DOWN, ALL_POWER_DOWN);
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}
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static void rts522a_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
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{
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struct rtsx_cr_option *option = &pcr->option;
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@ -473,6 +519,7 @@ static const struct pcr_ops rts522a_pcr_ops = {
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.card_power_on = rts5227_card_power_on,
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.card_power_off = rts5227_card_power_off,
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.switch_output_voltage = rts522a_switch_output_voltage,
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.force_power_down = rts522a_force_power_down,
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.cd_deglitch = NULL,
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.conv_clk_and_div_n = NULL,
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.set_l1off_cfg_sub_d0 = rts522a_set_l1off_cfg_sub_d0,
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@ -102,6 +102,14 @@ static void rts5228_force_power_down(struct rtsx_pcr *pcr, u8 pm_state, bool run
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rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
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D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
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if (!runtime) {
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rtsx_pci_write_register(pcr, RTS5228_AUTOLOAD_CFG1,
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CD_RESUME_EN_MASK, 0);
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rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00);
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rtsx_pci_write_register(pcr, RTS5228_REG_PME_FORCE_CTL,
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FORCE_PM_CONTROL | FORCE_PM_VALUE, FORCE_PM_CONTROL);
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}
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rtsx_pci_write_register(pcr, FPDCTL,
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SSC_POWER_DOWN, SSC_POWER_DOWN);
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}
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@ -480,9 +488,18 @@ static int rts5228_extra_init_hw(struct rtsx_pcr *pcr)
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FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
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rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, 0xFF, 0xFB);
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rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00);
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if (pcr->rtd3_en) {
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rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x01);
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rtsx_pci_write_register(pcr, RTS5228_REG_PME_FORCE_CTL,
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FORCE_PM_CONTROL | FORCE_PM_VALUE, FORCE_PM_CONTROL);
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FORCE_PM_CONTROL | FORCE_PM_VALUE,
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FORCE_PM_CONTROL | FORCE_PM_VALUE);
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} else {
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rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00);
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rtsx_pci_write_register(pcr, RTS5228_REG_PME_FORCE_CTL,
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FORCE_PM_CONTROL | FORCE_PM_VALUE, FORCE_PM_CONTROL);
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}
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rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, D3_DELINK_MODE_EN, 0x00);
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return 0;
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}
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@ -103,6 +103,24 @@ static void rts5261_force_power_down(struct rtsx_pcr *pcr, u8 pm_state, bool run
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rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
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D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
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if (!runtime) {
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rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG1,
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CD_RESUME_EN_MASK, 0);
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rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00);
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rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
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FORCE_PM_CONTROL | FORCE_PM_VALUE, FORCE_PM_CONTROL);
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} else {
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rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
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FORCE_PM_CONTROL | FORCE_PM_VALUE, 0);
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rtsx_pci_write_register(pcr, RTS5261_FW_CTL,
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RTS5261_INFORM_RTD3_COLD, RTS5261_INFORM_RTD3_COLD);
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rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG4,
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RTS5261_FORCE_PRSNT_LOW, RTS5261_FORCE_PRSNT_LOW);
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}
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rtsx_pci_write_register(pcr, RTS5261_REG_FPDCTL,
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SSC_POWER_DOWN, SSC_POWER_DOWN);
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}
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@ -536,9 +554,18 @@ static int rts5261_extra_init_hw(struct rtsx_pcr *pcr)
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FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
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rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, 0xFF, 0xFB);
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rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00);
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rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
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FORCE_PM_CONTROL | FORCE_PM_VALUE, FORCE_PM_CONTROL);
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if (pcr->rtd3_en) {
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rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x01);
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rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
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FORCE_PM_CONTROL | FORCE_PM_VALUE,
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FORCE_PM_CONTROL | FORCE_PM_VALUE);
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} else {
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rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00);
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rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
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FORCE_PM_CONTROL | FORCE_PM_VALUE, FORCE_PM_CONTROL);
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}
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rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, D3_DELINK_MODE_EN, 0x00);
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/* Clear Enter RTD3_cold Information*/
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rtsx_pci_write_register(pcr, RTS5261_FW_CTL,
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@ -15,6 +15,8 @@
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#define MIN_DIV_N_PCR 80
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#define MAX_DIV_N_PCR 208
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#define RTS522A_PME_FORCE_CTL 0xFF78
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#define RTS522A_AUTOLOAD_CFG1 0xFF7C
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#define RTS522A_PM_CTRL3 0xFF7E
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#define RTS524A_PME_FORCE_CTL 0xFF78
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