watchdog: ath79_wdt: flush register writes
The watchdog register writes required to have a flush in order to commit the values to the register. Without the flush, the driver not function correctly on AR934X SoCs. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
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@ -68,17 +68,23 @@ static int max_timeout;
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static inline void ath79_wdt_keepalive(void)
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static inline void ath79_wdt_keepalive(void)
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{
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{
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ath79_reset_wr(AR71XX_RESET_REG_WDOG, wdt_freq * timeout);
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ath79_reset_wr(AR71XX_RESET_REG_WDOG, wdt_freq * timeout);
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/* flush write */
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ath79_reset_rr(AR71XX_RESET_REG_WDOG);
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}
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}
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static inline void ath79_wdt_enable(void)
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static inline void ath79_wdt_enable(void)
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{
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{
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ath79_wdt_keepalive();
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ath79_wdt_keepalive();
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ath79_reset_wr(AR71XX_RESET_REG_WDOG_CTRL, WDOG_CTRL_ACTION_FCR);
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ath79_reset_wr(AR71XX_RESET_REG_WDOG_CTRL, WDOG_CTRL_ACTION_FCR);
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/* flush write */
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ath79_reset_rr(AR71XX_RESET_REG_WDOG_CTRL);
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}
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}
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static inline void ath79_wdt_disable(void)
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static inline void ath79_wdt_disable(void)
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{
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{
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ath79_reset_wr(AR71XX_RESET_REG_WDOG_CTRL, WDOG_CTRL_ACTION_NONE);
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ath79_reset_wr(AR71XX_RESET_REG_WDOG_CTRL, WDOG_CTRL_ACTION_NONE);
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/* flush write */
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ath79_reset_rr(AR71XX_RESET_REG_WDOG_CTRL);
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}
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}
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static int ath79_wdt_set_timeout(int val)
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static int ath79_wdt_set_timeout(int val)
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