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STM32 STM32MP25 for v6.5, round 1 

Highlights:
 ----------
 
 STM32MP25 family is composed of 4 SoCs defined as following:
 
   -STM32MP251: common part composed of 1*Cortex-A35,
    common peripherals like SDMMC, UART, SPI, I2C, PCIe, USB3,
    parallel and DSI display, 1*ETH ...
 
   -STM32MP253: STM32MP251 + 1*Cortex-A35 (dual CPU), a second ETH,
    CAN-FD and LVDS display.
 
   -STM32MP255: STM32MP253 + GPU/AI and video encode/decode.
   -STM32MP257: STM32MP255 + ETH TSN switch (2+1 ports).
 
   A second diversity layer exists for security features/A35 frequency:
   -STM32MP25xY, "Y" gives information:
     -Y = A means A35@1.2GHz + no cryp IP and no secure boot.
     -Y = C means A35@1.2GHz + cryp IP and secure boot.
     -Y = D means A35@1.5GHz + no cryp IP and no secure boot.
     -Y = F means A35@1.5GHz + cryp IP and secure boot.
 
 This PR adds the STM32MP257F EV1 board support. This board embeds a
 STM32MP257FAI SoC, with 4GB of DDR4, TSN switch (2+1 ports),
 2*USB typeA, 1*USB2 typeC, SNOR OctoSPI, mini PCIe, STPMIC2 for power distribution ...
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Merge tag 'stm32-mp25-for-v6.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/newsoc

STM32 STM32MP25 for v6.5, round 1

Highlights:
----------

STM32MP25 family is composed of 4 SoCs defined as following:

  -STM32MP251: common part composed of 1*Cortex-A35,
   common peripherals like SDMMC, UART, SPI, I2C, PCIe, USB3,
   parallel and DSI display, 1*ETH ...

  -STM32MP253: STM32MP251 + 1*Cortex-A35 (dual CPU), a second ETH,
   CAN-FD and LVDS display.

  -STM32MP255: STM32MP253 + GPU/AI and video encode/decode.
  -STM32MP257: STM32MP255 + ETH TSN switch (2+1 ports).

  A second diversity layer exists for security features/A35 frequency:
  -STM32MP25xY, "Y" gives information:
    -Y = A means A35@1.2GHz + no cryp IP and no secure boot.
    -Y = C means A35@1.2GHz + cryp IP and secure boot.
    -Y = D means A35@1.5GHz + no cryp IP and no secure boot.
    -Y = F means A35@1.5GHz + cryp IP and secure boot.

This PR adds the STM32MP257F EV1 board support. This board embeds a
STM32MP257FAI SoC, with 4GB of DDR4, TSN switch (2+1 ports),
2*USB typeA, 1*USB2 typeC, SNOR OctoSPI, mini PCIe, STPMIC2 for power distribution ...

* tag 'stm32-mp25-for-v6.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (44 commits)
  MAINTAINERS: add entry for ARM/STM32 ARCHITECTURE
  arm64: defconfig: enable ARCH_STM32 and STM32 serial driver
  arm64: dts: st: add stm32mp257f-ev1 board support
  dt-bindings: stm32: document stm32mp257f-ev1 board
  arm64: dts: st: introduce stm32mp25 pinctrl files
  arm64: dts: st: introduce stm32mp25 SoCs family
  arm64: introduce STM32 family on Armv8 architecture
  dt-bindings: stm32: add st,stm32mp25-syscfg compatible for syscon
  pinctrl: stm32: add stm32mp257 pinctrl support
  dt-bindings: pinctrl: stm32: support for stm32mp257 and additional packages
  ARM: dts: stm32: fix i2s endpoint format property for stm32mp15xx-dkx
  ARM: dts: stm32: Fix audio routing on STM32MP15xx DHCOM PDK2
  ARM: dts: stm32: add required supplies of ov5640 in stm32mp157c-ev1
  ARM: dts: stm32: Update to generic ADC channel binding on DHSOM systems
  ARM: dts: stm32: adopt generic iio bindings for adc channels on dhcor-testbench
  ARM: dts: stm32: adopt generic iio bindings for adc channels on dhcor-drc
  ARM: dts: stm32: adopt generic iio bindings for adc channels on emstamp-argon
  ARM: dts: stm32: adopt generic iio bindings for adc channels on stm32mp157c-ed1
  ARM: dts: stm32: enable adc on stm32mp15xx-dkx boards
  ARM: dts: stm32: add vrefint support to adc2 on stm32mp15
  ...

Link: https://lore.kernel.org/r/080fc303-45c1-6cc0-4c5e-694e730896a6@foss.st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2023-06-20 22:28:39 +02:00
parent 425d827ef9 c9cb7e72e2
commit 868a11b602
54 changed files with 4389 additions and 108 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml
View File

@ -15,12 +15,13 @@ properties:
oneOf:
- items:
- enum:
- st,stm32mp157-syscfg
- st,stm32mp151-pwr-mcu
- st,stm32-syscfg
- st,stm32-power-config
- st,stm32-syscfg
- st,stm32-tamp
- st,stm32f4-gcan
- st,stm32mp151-pwr-mcu
- st,stm32mp157-syscfg
- st,stm32mp25-syscfg
- const: syscon
- items:
- const: st,stm32-tamp

12
Documentation/devicetree/bindings/arm/stm32/stm32.yaml
View File

@ -155,6 +155,18 @@ properties:
- const: seeed,stm32mp157c-odyssey-som
- const: st,stm32mp157
- description: Phytec STM32MP1 SoM based Boards
items:
- const: phytec,phycore-stm32mp1-3
- const: phytec,phycore-stm32mp157c-som
- const: st,stm32mp157
- description: ST STM32MP257 based Boards
items:
- enum:
- st,stm32mp257f-ev1
- const: st,stm32mp257
additionalProperties: true
...

2
Documentation/devicetree/bindings/display/st,stm32-dsi.yaml
View File

@ -74,8 +74,6 @@ properties:
- const: 2
required:
- "#address-cells"
- "#size-cells"
- compatible
- reg
- clocks

4
Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
View File

@ -27,6 +27,8 @@ properties:
- st,stm32mp135-pinctrl
- st,stm32mp157-pinctrl
- st,stm32mp157-z-pinctrl
- st,stm32mp257-pinctrl
- st,stm32mp257-z-pinctrl
'#address-cells':
const: 1
@ -56,7 +58,7 @@ properties:
Indicates the SOC package used.
More details in include/dt-bindings/pinctrl/stm32-pinfunc.h
$ref: /schemas/types.yaml#/definitions/uint32
enum: [1, 2, 4, 8]
enum: [0x1, 0x2, 0x4, 0x8, 0x100, 0x400, 0x800]
patternProperties:
'^gpio@[0-9a-f]*$':

1
MAINTAINERS
View File

@ -2854,6 +2854,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32.git stm32-nex
F: arch/arm/boot/dts/stm32*
F: arch/arm/mach-stm32/
F: drivers/clocksource/armv7m_systick.c
F: arch/arm64/boot/dts/st/
N: stm32
N: stm

3
arch/arm/boot/dts/Makefile
View File

@ -1266,7 +1266,8 @@ dtb-$(CONFIG_ARCH_STM32) += \
stm32mp157c-ev1.dtb \
stm32mp157c-ev1-scmi.dtb \
stm32mp157c-lxa-mc1.dtb \
stm32mp157c-odyssey.dtb
stm32mp157c-odyssey.dtb \
stm32mp157c-phycore-stm32mp1-3.dtb
dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-a1000.dtb \
sun4i-a10-ba10-tvbox.dtb \

4
arch/arm/boot/dts/stm32f469-disco.dts
View File

@ -160,7 +160,7 @@
};
};
panel-dsi@0 {
panel@0 {
compatible = "orisetech,otm8009a";
reg = <0>; /* dsi virtual channel (0..3) */
reset-gpios = <&gpioh 7 GPIO_ACTIVE_LOW>;
@ -179,7 +179,7 @@
status = "okay";
port {
ltdc_out_dsi: endpoint@0 {
ltdc_out_dsi: endpoint {
remote-endpoint = <&dsi_in>;
};
};

2
arch/arm/boot/dts/stm32f746.dtsi
View File

@ -515,7 +515,7 @@
crc: crc@40023000 {
compatible = "st,stm32f7-crc";
reg = <0x40023000 0x400>;
clocks = <&rcc 0 12>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(CRC)>;
status = "disabled";
};

2
arch/arm/boot/dts/stm32h750i-art-pi.dts
View File

@ -208,7 +208,7 @@
dmas = <&dmamux1 45 0x400 0x05>,
<&dmamux1 46 0x400 0x05>;
dma-names = "rx", "tx";
st,hw-flow-ctrl;
uart-has-rtscts;
status = "okay";
bluetooth {

231
arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
View File

@ -341,6 +341,56 @@
};
};
ethernet0_rgmii_pins_d: rgmii-3 {
pins1 {
pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
<STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
<STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
<STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
<STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
<STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
<STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
pins2 {
pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins3 {
pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
<STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
<STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */
<STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
<STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
<STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
bias-disable;
};
};
ethernet0_rgmii_sleep_pins_d: rgmii-sleep-3 {
pins1 {
pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
<STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
<STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
<STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
<STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
<STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
<STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
<STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
<STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
<STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
<STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
<STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */
<STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
<STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
<STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
};
};
ethernet0_rmii_pins_a: rmii-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
@ -1441,6 +1491,30 @@
};
};
sai2b_pins_d: sai2b-3 {
pins1 {
pinmux = <STM32_PINMUX('H', 2, AF10)>, /* SAI2_SCK_B */
<STM32_PINMUX('C', 0, AF8)>, /* SAI2_FS_B */
<STM32_PINMUX('H', 3, AF10)>; /* SAI2_MCLK_B */
slew-rate = <0>;
drive-push-pull;
bias-disable;
};
pins2 {
pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
bias-disable;
};
};
sai2b_sleep_pins_d: sai2b-sleep-3 {
pins1 {
pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* SAI2_SCK_B */
<STM32_PINMUX('C', 0, ANALOG)>, /* SAI2_FS_B */
<STM32_PINMUX('H', 3, ANALOG)>, /* SAI2_MCLK_B */
<STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
};
};
sai4a_pins_a: sai4a-0 {
pins {
pinmux = <STM32_PINMUX('B', 5, AF10)>; /* SAI4_SD_A */
@ -1522,6 +1596,60 @@
};
};
sdmmc1_b4_pins_b: sdmmc1-b4-1 {
pins1 {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
<STM32_PINMUX('E', 6, AF8)>, /* SDMMC1_D2 */
<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
<STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
slew-rate = <1>;
drive-push-pull;
bias-disable;
};
pins2 {
pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
slew-rate = <2>;
drive-push-pull;
bias-disable;
};
};
sdmmc1_b4_od_pins_b: sdmmc1-b4-od-1 {
pins1 {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
<STM32_PINMUX('E', 6, AF8)>, /* SDMMC1_D2 */
<STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
slew-rate = <1>;
drive-push-pull;
bias-disable;
};
pins2 {
pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
slew-rate = <2>;
drive-push-pull;
bias-disable;
};
pins3 {
pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
slew-rate = <1>;
drive-open-drain;
bias-disable;
};
};
sdmmc1_b4_sleep_pins_b: sdmmc1-b4-sleep-1 {
pins {
pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
<STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
<STM32_PINMUX('E', 6, ANALOG)>, /* SDMMC1_D2 */
<STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
<STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
<STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
};
};
sdmmc1_dir_pins_a: sdmmc1-dir-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
@ -1759,6 +1887,27 @@
};
};
sdmmc2_d47_pins_e: sdmmc2-d47-4 {
pins {
pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
<STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
<STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
<STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
slew-rate = <1>;
drive-push-pull;
bias-pull-up;
};
};
sdmmc2_d47_sleep_pins_e: sdmmc2-d47-sleep-4 {
pins {
pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
<STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
<STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */
<STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */
};
};
sdmmc3_b4_pins_a: sdmmc3-b4-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
@ -2124,6 +2273,33 @@
};
};
usart1_pins_a: usart1-0 {
pins1 {
pinmux = <STM32_PINMUX('A', 12, AF7)>; /* USART1_RTS */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('A', 11, AF7)>; /* USART1_CTS_NSS */
bias-disable;
};
};
usart1_idle_pins_a: usart1-idle-0 {
pins1 {
pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* USART1_RTS */
<STM32_PINMUX('A', 11, AF7)>; /* USART1_CTS_NSS */
};
};
usart1_sleep_pins_a: usart1-sleep-0 {
pins {
pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* USART1_RTS */
<STM32_PINMUX('A', 11, ANALOG)>; /* USART1_CTS_NSS */
};
};
usart2_pins_a: usart2-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */
@ -2226,6 +2402,23 @@
};
};
usart3_idle_pins_a: usart3-idle-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, ANALOG)>; /* USART3_TX */
};
pins2 {
pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
bias-disable;
};
};
usart3_sleep_pins_a: usart3-sleep-0 {
pins {
pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
<STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */
};
};
usart3_pins_b: usart3-1 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
@ -2463,4 +2656,42 @@
bias-disable;
};
};
spi1_sleep_pins_a: spi1-sleep-0 {
pins {
pinmux = <STM32_PINMUX('Z', 0, ANALOG)>, /* SPI1_SCK */
<STM32_PINMUX('Z', 1, ANALOG)>, /* SPI1_MISO */
<STM32_PINMUX('Z', 2, ANALOG)>; /* SPI1_MOSI */
};
};
usart1_pins_b: usart1-1 {
pins1 {
pinmux = <STM32_PINMUX('Z', 7, AF7)>; /* USART1_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('Z', 6, AF7)>; /* USART1_RX */
bias-disable;
};
};
usart1_idle_pins_b: usart1-idle-1 {
pins1 {
pinmux = <STM32_PINMUX('Z', 7, ANALOG)>; /* USART1_TX */
};
pins2 {
pinmux = <STM32_PINMUX('Z', 6, AF7)>; /* USART1_RX */
bias-disable;
};
};
usart1_sleep_pins_b: usart1-sleep-1 {
pins {
pinmux = <STM32_PINMUX('Z', 7, ANALOG)>, /* USART1_TX */
<STM32_PINMUX('Z', 6, ANALOG)>; /* USART1_RX */
};
};
};

27
arch/arm/boot/dts/stm32mp151.dtsi
View File

@ -1093,6 +1093,8 @@
adc1: adc@0 {
compatible = "st,stm32mp1-adc";
#io-channel-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0>;
interrupt-parent = <&adc>;
interrupts = <0>;
@ -1104,12 +1106,24 @@
adc2: adc@100 {
compatible = "st,stm32mp1-adc";
#io-channel-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x100>;
interrupt-parent = <&adc>;
interrupts = <1>;
dmas = <&dmamux1 10 0x400 0x01>;
dma-names = "rx";
nvmem-cells = <&vrefint>;
nvmem-cell-names = "vrefint";
status = "disabled";
channel@13 {
reg = <13>;
label = "vrefint";
};
channel@14 {
reg = <14>;
label = "vddcore";
};
};
};
@ -1529,11 +1543,6 @@
clock-names = "lcd";
resets = <&rcc LTDC_R>;
status = "disabled";
port {
#address-cells = <1>;
#size-cells = <0>;
};
};
iwdg2: watchdog@5a002000 {
@ -1620,6 +1629,12 @@
reg = <0x5c005000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
part_number_otp: part-number-otp@4 {
reg = <0x4 0x1>;
};
vrefint: vrefin-cal@52 {
reg = <0x52 0x2>;
};
ts_cal1: calib@5c {
reg = <0x5c 0x2>;
};
@ -1820,8 +1835,8 @@
<0x30000000 0x40000>,
<0x38000000 0x10000>;
resets = <&rcc MCU_R>;
reset-names = "mcu_rst";
st,syscfg-holdboot = <&rcc 0x10C 0x1>;
st,syscfg-tz = <&rcc 0x000 0x1>;
st,syscfg-pdds = <&pwr_mcu 0x0 0x1>;
st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>;

7
arch/arm/boot/dts/stm32mp157.dtsi
View File

@ -24,14 +24,7 @@
clock-names = "pclk", "ref", "px_clk";
resets = <&rcc DSI_R>;
reset-names = "apb";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
};
};
};
};

7
arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts
View File

@ -55,8 +55,11 @@
resets = <&scmi_reset RST_SCMI_MDMA>;
};
&mlahb {
resets = <&scmi_reset RST_SCMI_MCU>;
&m4_rproc {
/delete-property/ st,syscfg-holdboot;
resets = <&scmi_reset RST_SCMI_MCU>,
<&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
reset-names = "mcu_rst", "hold_boot";
};
&rcc {

6
arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts
View File

@ -49,6 +49,9 @@
phy-dsi-supply = <&reg18>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi_in: endpoint {
@ -104,8 +107,7 @@
status = "okay";
port {
ltdc_ep0_out: endpoint@0 {
reg = <0>;
ltdc_ep0_out: endpoint {
remote-endpoint = <&dsi_in>;
};
};

6
arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts
View File

@ -49,6 +49,9 @@
phy-dsi-supply = <&reg18>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi_in_ltdc: endpoint {
@ -104,8 +107,7 @@
status = "okay";
port {
ltdc_out_dsi: endpoint@0 {
reg = <0>;
ltdc_out_dsi: endpoint {
remote-endpoint = <&dsi_in_ltdc>;
};
};

3
arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
View File

@ -81,8 +81,7 @@
status = "okay";
port {
ltdc_ep0_out: endpoint@0 {
reg = <0>;
ltdc_ep0_out: endpoint {
remote-endpoint = <&panel_in>;
};
};

4
arch/arm/boot/dts/stm32mp157a-stinger96.dtsi
View File

@ -287,7 +287,7 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&usart2_pins_b>;
pinctrl-1 = <&usart2_sleep_pins_b>;
st,hw-flow-ctrl;
uart-has-rtscts;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
@ -297,7 +297,7 @@
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&uart4_pins_c>;
st,hw-flow-ctrl;
uart-has-rtscts;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";

7
arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts
View File

@ -61,8 +61,11 @@
resets = <&scmi_reset RST_SCMI_MDMA>;
};
&mlahb {
resets = <&scmi_reset RST_SCMI_MCU>;
&m4_rproc {
/delete-property/ st,syscfg-holdboot;
resets = <&scmi_reset RST_SCMI_MCU>,
<&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
reset-names = "mcu_rst", "hold_boot";
};
&rcc {

8
arch/arm/boot/dts/stm32mp157c-dk2.dts
View File

@ -31,10 +31,15 @@
};
&dsi {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
phy-dsi-supply = <&reg18>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi_in: endpoint {
@ -82,6 +87,9 @@
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
ltdc_ep1_out: endpoint@1 {
reg = <1>;
remote-endpoint = <&dsi_in>;

7
arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts
View File

@ -60,8 +60,11 @@
resets = <&scmi_reset RST_SCMI_MDMA>;
};
&mlahb {
resets = <&scmi_reset RST_SCMI_MCU>;
&m4_rproc {
/delete-property/ st,syscfg-holdboot;
resets = <&scmi_reset RST_SCMI_MCU>,
<&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
reset-names = "mcu_rst", "hold_boot";
};
&rcc {

16
arch/arm/boot/dts/stm32mp157c-ed1.dts
View File

@ -103,10 +103,20 @@
vref-supply = <&vdda>;
status = "disabled";
adc1: adc@0 {
st,adc-channels = <0 1 6>;
/* 16.5 ck_cycles sampling time */
st,min-sample-time-nsecs = <400>;
status = "okay";
channel@0 {
reg = <0>;
/* 16.5 ck_cycles sampling time */
st,min-sample-time-ns = <400>;
};
channel@1 {
reg = <1>;
st,min-sample-time-ns = <400>;
};
channel@6 {
reg = <6>;
st,min-sample-time-ns = <400>;
};
};
};

6
arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi
View File

@ -97,9 +97,11 @@
adc1: adc@0 {
pinctrl-names = "default";
pinctrl-0 = <&adc1_in6_pins_a>;
st,min-sample-time-nsecs = <5000>;
st,adc-channels = <6>;
status = "disabled";
channel@6 {
reg = <6>;
st,min-sample-time-ns = <5000>;
};
};
adc2: adc@100 {

7
arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts
View File

@ -66,8 +66,11 @@
resets = <&scmi_reset RST_SCMI_MDMA>;
};
&mlahb {
resets = <&scmi_reset RST_SCMI_MCU>;
&m4_rproc {
/delete-property/ st,syscfg-holdboot;
resets = <&scmi_reset RST_SCMI_MCU>,
<&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
reset-names = "mcu_rst", "hold_boot";
};
&rcc {

12
arch/arm/boot/dts/stm32mp157c-ev1.dts
View File

@ -101,9 +101,14 @@
&dsi {
phy-dsi-supply = <&reg18>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi_in: endpoint {
@ -119,7 +124,7 @@
};
};
panel-dsi@0 {
panel@0 {
compatible = "raydium,rm68200";
reg = <0>;
reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>;
@ -185,7 +190,9 @@
reg = <0x3c>;
clocks = <&clk_ext_camera>;
clock-names = "xclk";
AVDD-supply = <&v2v8>;
DOVDD-supply = <&v2v8>;
DVDD-supply = <&v2v8>;
powerdown-gpios = <&stmfx_pinctrl 18 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>;
reset-gpios = <&stmfx_pinctrl 19 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
rotation = <180>;
@ -239,8 +246,7 @@
status = "okay";
port {
ltdc_ep0_out: endpoint@0 {
reg = <0>;
ltdc_ep0_out: endpoint {
remote-endpoint = <&dsi_in>;
};
};

3
arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts
View File

@ -161,8 +161,7 @@
status = "okay";
port {
ltdc_ep0_out: endpoint@0 {
reg = <0>;
ltdc_ep0_out: endpoint {
remote-endpoint = <&panel_input>;
};
};

60
arch/arm/boot/dts/stm32mp157c-phycore-stm32mp1-3.dts Normal file
View File

@ -0,0 +1,60 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) Phytec GmbH 2019-2020 - All Rights Reserved
* Author: Dom VOVARD <dom.vovard@linrt.com>.
*/
/dts-v1/;
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
#include "stm32mp157.dtsi"
#include "stm32mp15xc.dtsi"
#include "stm32mp15xxac-pinctrl.dtsi"
#include "stm32mp157c-phycore-stm32mp15-som.dtsi"
/ {
model = "PHYTEC phyCORE-STM32MP1-3 Dev Board";
compatible = "phytec,phycore-stm32mp1-3",
"phytec,phycore-stm32mp157c-som", "st,stm32mp157";
aliases {
mmc0 = &sdmmc1;
mmc1 = &sdmmc2;
mmc2 = &sdmmc3;
serial0 = &uart4;
serial1 = &usart3;
serial2 = &usart1;
};
};
&cryp1 {
status = "okay";
};
&dts {
status = "okay";
};
&fmc {
status = "disabled";
};
&gpu {
status = "okay";
};
&i2c4_eeprom {
status = "okay";
};
&i2c4_rtc {
status = "okay";
};
&qspi {
status = "okay";
};
&sdmmc2 {
status = "okay";
};

577
arch/arm/boot/dts/stm32mp157c-phycore-stm32mp15-som.dtsi Normal file
View File

@ -0,0 +1,577 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) 2022-2023 Steffen Trumtrar <kernel@pengutronix.de>
* Copyright (C) Phytec GmbH 2019-2020 - All Rights Reserved
* Author: Dom VOVARD <dom.vovard@linrt.com>.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/leds/leds-pca9532.h>
#include <dt-bindings/mfd/st,stpmic1.h>
#include <dt-bindings/net/ti-dp83867.h>
#include "stm32mp15-pinctrl.dtsi"
/ {
model = "PHYTEC phyCORE-STM32MP15 SOM";
compatible = "phytec,phycore-stm32mp157c-som", "st,stm32mp157";
aliases {
ethernet0 = &ethernet0;
rtc0 = &i2c4_rtc;
rtc1 = &rtc;
};
chosen {
stdout-path = "serial0:115200n8";
};
gpio-keys {
compatible = "gpio-keys";
key-home {
label = "Home";
gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOME>;
};
key-enter {
label = "Enter";
gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
linux,code = <KEY_ENTER>;
};
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
retram: retram@38000000 {
compatible = "shared-dma-pool";
reg = <0x38000000 0x10000>;
no-map;
};
mcuram: mcuram@30000000 {
compatible = "shared-dma-pool";
reg = <0x30000000 0x40000>;
no-map;
};
mcuram2: mcuram2@10000000 {
compatible = "shared-dma-pool";
reg = <0x10000000 0x40000>;
no-map;
};
vdev0vring0: vdev0vring0@10040000 {
compatible = "shared-dma-pool";
reg = <0x10040000 0x1000>;
no-map;
};
vdev0vring1: vdev0vring1@10041000 {
compatible = "shared-dma-pool";
reg = <0x10041000 0x1000>;
no-map;
};
vdev0buffer: vdev0buffer@10042000 {
compatible = "shared-dma-pool";
reg = <0x10042000 0x4000>;
no-map;
};
};
sound {
compatible = "audio-graph-card";
label = "STM32MP1-PHYCORE";
routing =
"Playback", "MCLK", /* Set a route between "MCLK" and "playback" widgets */
"Capture", "MCLK";
dais = <&sai2b_port>,
<&sai2a_port>;
};
regulator_vin: regulator {
compatible = "regulator-fixed";
regulator-name = "vin";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
};
&ethernet0 {
pinctrl-0 = <&ethernet0_rgmii_pins_d>;
pinctrl-1 = <&ethernet0_rgmii_sleep_pins_d>;
pinctrl-names = "default", "sleep";
phy-mode = "rgmii-id";
max-speed = <1000>;
phy-handle = <&phy0>;
st,eth-clk-sel;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
interrupt-parent = <&gpiog>;
interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,min-output-impedance;
enet-phy-lane-no-swap;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
};
};
};
&i2c1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c1_pins_b>;
pinctrl-1 = <&i2c1_sleep_pins_b>;
i2c-scl-rising-time-ns = <100>;
i2c-scl-falling-time-ns = <7>;
status = "okay";
codec@18 {
compatible = "ti,tlv320aic3007";
reg = <0x18>;
#sound-dai-cells = <0>;
ai3x-micbias-vg = <2>;
AVDD-supply = <&v3v3>;
IOVDD-supply = <&v3v3>;
DRVDD-supply = <&v3v3>;
DVDD-supply = <&v1v8_audio>;
clocks = <&sai2b>;
port {
#address-cells = <1>;
#size-cells = <0>;
tlv320_tx_endpoint: endpoint@0 {
reg = <0>;
remote-endpoint = <&sai2b_endpoint>;
frame-master;
bitclock-master;
};
tlv320_rx_endpoint: endpoint@1 {
reg = <1>;
remote-endpoint = <&sai2a_endpoint>;
frame-master;
bitclock-master;
};
};
};
touch@44 {
compatible = "st,stmpe811";
reg = <0x44>;
interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
interrupt-parent = <&gpioi>;
vio-supply = <&v3v3>;
vcc-supply = <&v3v3>;
touchscreen {
compatible = "st,stmpe-ts";
st,sample-time = <4>;
st,mod-12b = <1>;
st,ref-sel = <0>;
st,adc-freq = <1>;
st,ave-ctrl = <1>;
st,touch-det-delay = <2>;
st,settling = <2>;
st,fraction-z = <7>;
st,i-drive = <1>;
};
};
leds@62 {
compatible = "nxp,pca9533";
reg = <0x62>;
led-0 {
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_POWER;
type = <PCA9532_TYPE_LED>;
};
led-1 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_POWER;
type = <PCA9532_TYPE_LED>;
};
led-2 {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_HEARTBEAT;
type = <PCA9532_TYPE_LED>;
linux,default-trigger = "heartbeat";
};
};
};
&i2c4 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c4_pins_a>;
pinctrl-1 = <&i2c4_sleep_pins_a>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
pmic@33 {
compatible = "st,stpmic1";
reg = <0x33>;
interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
regulators {
compatible = "st,stpmic1-regulators";
buck1-supply = <&regulator_vin>;
buck2-supply = <&regulator_vin>;
buck3-supply = <&regulator_vin>;
buck4-supply = <&regulator_vin>;
ldo1-supply = <&v3v3>;
ldo2-supply = <&v3v3>;
ldo3-supply = <&vdd_ddr>;
ldo4-supply = <&regulator_vin>;
ldo5-supply = <&v3v3>;
ldo6-supply = <&v3v3>;
boost-supply = <&regulator_vin>;
pwr_sw1-supply = <&bst_out>;
pwr_sw2-supply = <&bst_out>;
vddcore: buck1 {
regulator-name = "vddcore";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-initial-mode = <0>;
};
vdd_ddr: buck2 {
regulator-name = "vdd_ddr";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-initial-mode = <0>;
};
vdd: buck3 {
regulator-name = "vdd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
st,mask-reset;
regulator-initial-mode = <0>;
};
v3v3: buck4 {
regulator-name = "v3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-initial-mode = <0>;
};
v1v8_audio: ldo1 {
regulator-name = "v1v8_audio";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
interrupts = <IT_CURLIM_LDO1 0>;
};
vdd_eth_2v5: ldo2 {
regulator-name = "dd_eth_2v5";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
interrupts = <IT_CURLIM_LDO2 0>;
};
vtt_ddr: ldo3 {
regulator-name = "vtt_ddr";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <750000>;
regulator-always-on;
regulator-over-current-protection;
};
vdd_usb: ldo4 {
regulator-name = "vdd_usb";
interrupts = <IT_CURLIM_LDO4 0>;
};
vdda: ldo5 {
regulator-name = "vdda";
regulator-min-microvolt = <2900000>;
regulator-max-microvolt = <2900000>;
interrupts = <IT_CURLIM_LDO5 0>;
regulator-boot-on;
};
vdd_eth_1v0: ldo6 {
regulator-name = "vdd_eth_1v0";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
interrupts = <IT_CURLIM_LDO6 0>;
};
vref_ddr: vref_ddr {
regulator-name = "vref_ddr";
regulator-always-on;
};
bst_out: boost {
regulator-name = "bst_out";
interrupts = <IT_OCP_BOOST 0>;
};
vbus_otg: pwr_sw1 {
regulator-name = "vbus_otg";
interrupts = <IT_OCP_OTG 0>;
regulator-active-discharge = <1>;
};
vbus_sw: pwr_sw2 {
regulator-name = "vbus_sw";
interrupts = <IT_OCP_SWOUT 0>;
regulator-active-discharge = <1>;
};
};
onkey {
compatible = "st,stpmic1-onkey";
interrupts = <IT_PONKEY_F 0>,
<IT_PONKEY_R 0>;
interrupt-names = "onkey-falling",
"onkey-rising";
power-off-time-sec = <10>;
};
watchdog {
compatible = "st,stpmic1-wdt";
};
};
i2c4_eeprom: eeprom@50 {
compatible = "microchip,24c32",
"atmel,24c32";
reg = <0x50>;
};
i2c4_rtc: rtc@52 {
compatible = "microcrystal,rv3028";
reg = <0x52>;
};
};
&ipcc {
status = "okay";
};
&iwdg2 {
timeout-sec = <32>;
status = "okay";
};
&m_can2 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&m_can2_pins_a>;
pinctrl-1 = <&m_can2_sleep_pins_a>;
status = "okay";
};
&m4_rproc {
memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
<&vdev0vring1>, <&vdev0buffer>;
mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
mbox-names = "vq0", "vq1", "shutdown", "detach";
interrupt-parent = <&exti>;
interrupts = <68 1>;
status = "okay";
};
&pwr_regulators {
vdd-supply = <&vdd>;
vdd_3v3_usbfs-supply = <&vdd_usb>;
};
&qspi {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>;
status = "okay";
flash0: flash@0 {
compatible = "winbond,w25q128", "jedec,spi-nor";
reg = <0>;
spi-rx-bus-width = <4>;
spi-max-frequency = <50000000>;
m25p,fast-read;
#address-cells = <1>;
#size-cells = <1>;
};
};
&rng1 {
status = "okay";
};
&rtc {
status = "okay";
};
&sai2 {
clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
clock-names = "pclk", "x8k", "x11k";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sai2a_pins_b>, <&sai2b_pins_d>;
pinctrl-1 = <&sai2a_sleep_pins_b>, <&sai2b_sleep_pins_d>;
status = "okay";
};
&sai2a {
dma-names = "rx";
st,sync = <&sai2b 2>;
clocks = <&rcc SAI2_K>, <&sai2b>;
clock-names = "sai_ck", "MCLK";
#clock-cells = <0>;
sai2a_port: port {
sai2a_endpoint: endpoint {
remote-endpoint = <&tlv320_rx_endpoint>;
mclk-fs = <256>;
dai-tdm-slot-num = <2>;
dai-tdm-slot-width = <16>;
};
};
};
&sai2b {
dma-names = "tx";
#clock-cells = <0>;
sai2b_port: port {
sai2b_endpoint: endpoint {
remote-endpoint = <&tlv320_tx_endpoint>;
mclk-fs = <256>;
dai-tdm-slot-num = <2>;
dai-tdm-slot-width = <16>;
};
};
};
&sdmmc1 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc1_b4_pins_b>;
pinctrl-1 = <&sdmmc1_b4_od_pins_b>;
pinctrl-2 = <&sdmmc1_b4_sleep_pins_b>;
cd-gpios = <&gpiof 3 GPIO_ACTIVE_LOW>;
disable-wp;
st,neg-edge;
bus-width = <4>;
vmmc-supply = <&v3v3>;
status = "okay";
};
&sdmmc2 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_e>;
pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_e>;
pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_e>;
non-removable;
no-sd;
no-sdio;
st,neg-edge;
bus-width = <8>;
vmmc-supply = <&v3v3>;
vqmmc-supply = <&v3v3>;
mmc-ddr-3_3v;
};
&spi1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi1_pins_a>;
pinctrl-1 = <&spi1_sleep_pins_a>;
cs-gpios = <&gpioz 3 0>;
status = "okay";
};
&uart4 {
pinctrl-names = "default", "sleep", "idle";
pinctrl-0 = <&uart4_pins_a>;
pinctrl-1 = <&uart4_sleep_pins_a>;
pinctrl-2 = <&uart4_idle_pins_a>;
pinctrl-3 = <&uart4_pins_a>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};
&usart1 {
pinctrl-names = "default", "sleep", "idle";
pinctrl-0 = <&usart1_pins_b &usart1_pins_a>;
pinctrl-1 = <&usart1_sleep_pins_b &usart1_sleep_pins_a>;
pinctrl-2 = <&usart1_idle_pins_b &usart1_idle_pins_a>;
uart-has-rtscts;
status = "okay";
};
&usart3 {
pinctrl-names = "default", "sleep", "idle";
pinctrl-0 = <&usart3_pins_a>;
pinctrl-1 = <&usart3_sleep_pins_a>;
pinctrl-2 = <&usart3_idle_pins_a>;
status = "okay";
};
&usbh_ehci {
phys = <&usbphyc_port0>;
phy-names = "usb";
status = "okay";
};
&usbh_ohci {
phys = <&usbphyc_port0>;
phy-names = "usb";
status = "okay";
};
&usbotg_hs {
phys = <&usbphyc_port1 0>;
phy-names = "usb2-phy";
status = "okay";
};
&usbphyc {
status = "okay";
};
&usbphyc_port0 {
phy-supply = <&vdd_usb>;
};
&usbphyc_port1 {
phy-supply = <&vdd_usb>;
};

11
arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi
View File

@ -137,10 +137,13 @@
sound {
compatible = "audio-graph-card";
routing =
"MIC_IN", "Capture",
"Capture", "Mic Bias",
"Playback", "HP_OUT";
widgets = "Headphone", "Headphone Jack",
"Line", "Line In Jack",
"Microphone", "Microphone Jack";
routing = "Headphone Jack", "HP_OUT",
"LINE_IN", "Line In Jack",
"MIC_IN", "Microphone Jack",
"Microphone Jack", "Mic Bias";
dais = <&sai2a_port &sai2b_port>;
status = "okay";
};

18
arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi
View File

@ -80,17 +80,19 @@
vdda-supply = <&vdda>;
vref-supply = <&vdda>;
status = "okay";
};
adc1: adc@0 {
st,min-sample-time-nsecs = <5000>;
st,adc-channels = <0>;
status = "okay";
&adc1 {
channel@0 {
reg = <0>;
st,min-sample-time-ns = <5000>;
};
};
adc2: adc@100 {
st,adc-channels = <1>;
st,min-sample-time-nsecs = <5000>;
status = "okay";
&adc2 {
channel@1 {
reg = <1>;
st,min-sample-time-ns = <5000>;
};
};

54
arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi
View File

@ -87,7 +87,7 @@
sound {
compatible = "audio-graph-card";
label = "STM32MP1-AV96-HDMI";
label = "STM32-AV96-HDMI";
dais = <&sai2a_port>;
status = "okay";
};
@ -111,17 +111,39 @@
vdda-supply = <&vdda>;
vref-supply = <&vdda>;
status = "okay";
};
adc1: adc@0 {
st,adc-channels = <0 1 6>;
st,min-sample-time-nsecs = <5000>;
status = "okay";
&adc1 {
channel@0 {
reg = <0>;
st,min-sample-time-ns = <5000>;
};
adc2: adc@100 {
st,adc-channels = <0 1 2>;
st,min-sample-time-nsecs = <5000>;
status = "okay";
channel@1 {
reg = <1>;
st,min-sample-time-ns = <5000>;
};
channel@6 {
reg = <6>;
st,min-sample-time-ns = <5000>;
};
};
&adc2 {
channel@0 {
reg = <0>;
st,min-sample-time-ns = <5000>;
};
channel@1 {
reg = <1>;
st,min-sample-time-ns = <5000>;
};
channel@2 {
reg = <2>;
st,min-sample-time-ns = <5000>;
};
};
@ -321,6 +343,12 @@
};
};
};
dh_mac_eeprom: eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;
pagesize = <16>;
};
};
&ltdc {
@ -330,11 +358,7 @@
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
ltdc_ep0_out: endpoint@0 {
reg = <0>;
ltdc_ep0_out: endpoint {
remote-endpoint = <&adv7513_in>;
};
};
@ -452,7 +476,7 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&usart2_pins_a>;
pinctrl-1 = <&usart2_sleep_pins_a>;
st,hw-flow-ctrl;
uart-has-rtscts;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";

34
arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi
View File

@ -57,15 +57,35 @@
status = "okay";
adc1: adc@0 {
st,adc-channels = <0 1 6>;
st,min-sample-time-nsecs = <5000>;
status = "okay";
channel@0 {
reg = <0>;
st,min-sample-time-ns = <5000>;
};
channel@1 {
reg = <1>;
st,min-sample-time-ns = <5000>;
};
channel@6 {
reg = <6>;
st,min-sample-time-ns = <5000>;
};
};
adc2: adc@100 {
st,adc-channels = <0 1 2>;
st,min-sample-time-nsecs = <5000>;
status = "okay";
channel@0 {
reg = <0>;
st,min-sample-time-ns = <5000>;
};
channel@1 {
reg = <1>;
st,min-sample-time-ns = <5000>;
};
channel@2 {
reg = <2>;
st,min-sample-time-ns = <5000>;
};
};
};
@ -192,6 +212,12 @@
reg = <0x50>;
pagesize = <16>;
};
dh_mac_eeprom: eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;
pagesize = <16>;
};
};
&sdmmc1 { /* MicroSD */

6
arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi
View File

@ -213,12 +213,6 @@
status = "disabled";
};
};
eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;
pagesize = <16>;
};
};
&ipcc {

36
arch/arm/boot/dts/stm32mp15xx-dhcor-testbench.dtsi
View File

@ -41,15 +41,35 @@
status = "okay";
adc1: adc@0 {
st,adc-channels = <0 1 6>;
st,min-sample-time-nsecs = <5000>;
status = "okay";
channel@0 {
reg = <0>;
st,min-sample-time-ns = <5000>;
};
channel@1 {
reg = <1>;
st,min-sample-time-ns = <5000>;
};
channel@6 {
reg = <6>;
st,min-sample-time-ns = <5000>;
};
};
adc2: adc@100 {
st,adc-channels = <0 1 2>;
st,min-sample-time-nsecs = <5000>;
status = "okay";
channel@0 {
reg = <0>;
st,min-sample-time-ns = <5000>;
};
channel@1 {
reg = <1>;
st,min-sample-time-ns = <5000>;
};
channel@2 {
reg = <2>;
st,min-sample-time-ns = <5000>;
};
};
};
@ -90,6 +110,14 @@
};
};
&i2c4 {
dh_mac_eeprom: eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;
pagesize = <16>;
};
};
&sdmmc1 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>;

44
arch/arm/boot/dts/stm32mp15xx-dkx.dtsi
View File

@ -93,28 +93,39 @@
&adc {
pinctrl-names = "default";
pinctrl-0 = <&adc12_ain_pins_a>, <&adc12_usb_cc_pins_a>;
pinctrl-0 = <&adc12_usb_cc_pins_a>;
vdd-supply = <&vdd>;
vdda-supply = <&vdd>;
vref-supply = <&vrefbuf>;
status = "disabled";
status = "okay";
adc1: adc@0 {
status = "okay";
/*
* Type-C USB_PWR_CC1 & USB_PWR_CC2 on in18 & in19.
* Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
* 5 * (56 + 47kOhms) * 5pF => 2.5us.
* Use arbitrary margin here (e.g. 5us).
*/
st,min-sample-time-nsecs = <5000>;
/* AIN connector, USB Type-C CC1 & CC2 */
st,adc-channels = <0 1 6 13 18 19>;
status = "okay";
channel@18 {
reg = <18>;
st,min-sample-time-ns = <5000>;
};
channel@19 {
reg = <19>;
st,min-sample-time-ns = <5000>;
};
};
adc2: adc@100 {
/* AIN connector, USB Type-C CC1 & CC2 */
st,adc-channels = <0 1 2 6 18 19>;
st,min-sample-time-nsecs = <5000>;
status = "okay";
/* USB Type-C CC1 & CC2 */
channel@18 {
reg = <18>;
st,min-sample-time-ns = <5000>;
};
channel@19 {
reg = <19>;
st,min-sample-time-ns = <5000>;
};
};
};
@ -379,21 +390,21 @@
regulator-always-on;
};
bst_out: boost {
bst_out: boost {
regulator-name = "bst_out";
interrupts = <IT_OCP_BOOST 0>;
};
};
vbus_otg: pwr_sw1 {
regulator-name = "vbus_otg";
interrupts = <IT_OCP_OTG 0>;
};
};
vbus_sw: pwr_sw2 {
vbus_sw: pwr_sw2 {
regulator-name = "vbus_sw";
interrupts = <IT_OCP_SWOUT 0>;
regulator-active-discharge = <1>;
};
};
};
onkey {
@ -435,7 +446,7 @@
i2s2_port: port {
i2s2_endpoint: endpoint {
remote-endpoint = <&sii9022_tx_endpoint>;
format = "i2s";
dai-format = "i2s";
mclk-fs = <256>;
};
};
@ -457,8 +468,7 @@
status = "okay";
port {
ltdc_ep0_out: endpoint@0 {
reg = <0>;
ltdc_ep0_out: endpoint {
remote-endpoint = <&sii9022_in>;
};
};

14
arch/arm64/Kconfig.platforms
View File

@ -285,6 +285,20 @@ config ARCH_INTEL_SOCFPGA
Stratix 10 (ex. Altera), Stratix10 Software Virtual Platform,
Agilex and eASIC N5X.
config ARCH_STM32
bool "STMicroelectronics STM32 SoC Family"
select GPIOLIB
select PINCTRL
select PINCTRL_STM32MP257
select ARM_SMC_MBOX
select ARM_SCMI_PROTOCOL
select COMMON_CLK_SCMI
help
This enables support for ARMv8 based STMicroelectronics
STM32 family, including:
- STM32MP25:
- STM32MP251, STM32MP253, STM32MP255 and STM32MP257.
config ARCH_SYNQUACER
bool "Socionext SynQuacer SoC Family"
select IRQ_FASTEOI_HIERARCHY_HANDLERS

1
arch/arm64/boot/dts/Makefile
View File

@ -27,6 +27,7 @@ subdir-y += renesas
subdir-y += rockchip
subdir-y += socionext
subdir-y += sprd
subdir-y += st
subdir-y += synaptics
subdir-y += tesla
subdir-y += ti

2
arch/arm64/boot/dts/st/Makefile Normal file
View File

@ -0,0 +1,2 @@
# SPDX-License-Identifier: GPL-2.0-only
dtb-$(CONFIG_ARCH_STM32) += stm32mp257f-ev1.dtb

38
arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi Normal file
View File

@ -0,0 +1,38 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
&pinctrl {
usart2_pins_a: usart2-0 {
pins1 {
pinmux = <STM32_PINMUX('A', 4, AF6)>; /* USART2_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('A', 8, AF8)>; /* USART2_RX */
bias-disable;
};
};
usart2_idle_pins_a: usart2-idle-0 {
pins1 {
pinmux = <STM32_PINMUX('A', 4, ANALOG)>; /* USART2_TX */
};
pins2 {
pinmux = <STM32_PINMUX('A', 8, AF8)>; /* USART2_RX */
bias-disable;
};
};
usart2_sleep_pins_a: usart2-sleep-0 {
pins {
pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* USART2_TX */
<STM32_PINMUX('A', 8, ANALOG)>; /* USART2_RX */
};
};
};

279
arch/arm64/boot/dts/st/stm32mp251.dtsi Normal file
View File

@ -0,0 +1,279 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a35";
device_type = "cpu";
reg = <0>;
enable-method = "psci";
};
};
arm-pmu {
compatible = "arm,cortex-a35-pmu";
interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>;
interrupt-parent = <&intc>;
};
clocks {
ck_flexgen_08: ck-flexgen-08 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <100000000>;
};
ck_flexgen_51: ck-flexgen-51 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <200000000>;
};
ck_icn_ls_mcu: ck-icn-ls-mcu {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <200000000>;
};
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
scmi {
compatible = "linaro,scmi-optee";
#address-cells = <1>;
#size-cells = <0>;
linaro,optee-channel-id = <0>;
scmi_clk: protocol@14 {
reg = <0x14>;
#clock-cells = <1>;
};
scmi_reset: protocol@16 {
reg = <0x16>;
#reset-cells = <1>;
};
};
};
intc: interrupt-controller@4ac00000 {
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>;
#address-cells = <1>;
interrupt-controller;
reg = <0x0 0x4ac10000 0x0 0x1000>,
<0x0 0x4ac20000 0x0 0x2000>,
<0x0 0x4ac40000 0x0 0x2000>,
<0x0 0x4ac60000 0x0 0x2000>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&intc>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
always-on;
};
soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
ranges = <0x0 0x0 0x0 0x80000000>;
rifsc: rifsc-bus@42080000 {
compatible = "simple-bus";
reg = <0x42080000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
usart2: serial@400e0000 {
compatible = "st,stm32h7-uart";
reg = <0x400e0000 0x400>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ck_flexgen_08>;
status = "disabled";
};
};
syscfg: syscon@44230000 {
compatible = "st,stm32mp25-syscfg", "syscon";
reg = <0x44230000 0x10000>;
};
pinctrl: pinctrl@44240000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stm32mp257-pinctrl";
ranges = <0 0x44240000 0xa0400>;
pins-are-numbered;
gpioa: gpio@44240000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x0 0x400>;
clocks = <&ck_icn_ls_mcu>;
st,bank-name = "GPIOA";
status = "disabled";
};
gpiob: gpio@44250000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x10000 0x400>;
clocks = <&ck_icn_ls_mcu>;
st,bank-name = "GPIOB";
status = "disabled";
};
gpioc: gpio@44260000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x20000 0x400>;
clocks = <&ck_icn_ls_mcu>;
st,bank-name = "GPIOC";
status = "disabled";
};
gpiod: gpio@44270000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x30000 0x400>;
clocks = <&ck_icn_ls_mcu>;
st,bank-name = "GPIOD";
status = "disabled";
};
gpioe: gpio@44280000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x40000 0x400>;
clocks = <&ck_icn_ls_mcu>;
st,bank-name = "GPIOE";
status = "disabled";
};
gpiof: gpio@44290000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x50000 0x400>;
clocks = <&ck_icn_ls_mcu>;
st,bank-name = "GPIOF";
status = "disabled";
};
gpiog: gpio@442a0000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x60000 0x400>;
clocks = <&ck_icn_ls_mcu>;
st,bank-name = "GPIOG";
status = "disabled";
};
gpioh: gpio@442b0000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x70000 0x400>;
clocks = <&ck_icn_ls_mcu>;
st,bank-name = "GPIOH";
status = "disabled";
};
gpioi: gpio@442c0000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x80000 0x400>;
clocks = <&ck_icn_ls_mcu>;
st,bank-name = "GPIOI";
status = "disabled";
};
gpioj: gpio@442d0000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x90000 0x400>;
clocks = <&ck_icn_ls_mcu>;
st,bank-name = "GPIOJ";
status = "disabled";
};
gpiok: gpio@442e0000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0xa0000 0x400>;
clocks = <&ck_icn_ls_mcu>;
st,bank-name = "GPIOK";
status = "disabled";
};
};
pinctrl_z: pinctrl@46200000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stm32mp257-z-pinctrl";
ranges = <0 0x46200000 0x400>;
pins-are-numbered;
gpioz: gpio@46200000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0 0x400>;
clocks = <&ck_icn_ls_mcu>;
st,bank-name = "GPIOZ";
st,bank-ioport = <11>;
status = "disabled";
};
};
};
};

23
arch/arm64/boot/dts/st/stm32mp253.dtsi Normal file
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@ -0,0 +1,23 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
#include "stm32mp251.dtsi"
/ {
cpus {
cpu1: cpu@1 {
compatible = "arm,cortex-a35";
device_type = "cpu";
reg = <1>;
enable-method = "psci";
};
};
arm-pmu {
interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>;
};
};

9
arch/arm64/boot/dts/st/stm32mp255.dtsi Normal file
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@ -0,0 +1,9 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
#include "stm32mp253.dtsi"
/ {
};

9
arch/arm64/boot/dts/st/stm32mp257.dtsi Normal file
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@ -0,0 +1,9 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
#include "stm32mp255.dtsi"
/ {
};

50
arch/arm64/boot/dts/st/stm32mp257f-ev1.dts Normal file
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@ -0,0 +1,50 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
/dts-v1/;
#include "stm32mp257.dtsi"
#include "stm32mp25xf.dtsi"
#include "stm32mp25-pinctrl.dtsi"
#include "stm32mp25xxai-pinctrl.dtsi"
/ {
model = "STMicroelectronics STM32MP257F-EV1 Evaluation Board";
compatible = "st,stm32mp257f-ev1", "st,stm32mp257";
aliases {
serial0 = &usart2;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x1 0x0>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
fw@80000000 {
compatible = "shared-dma-pool";
reg = <0x0 0x80000000 0x0 0x4000000>;
no-map;
};
};
};
&usart2 {
pinctrl-names = "default", "idle", "sleep";
pinctrl-0 = <&usart2_pins_a>;
pinctrl-1 = <&usart2_idle_pins_a>;
pinctrl-2 = <&usart2_sleep_pins_a>;
status = "okay";
};

8
arch/arm64/boot/dts/st/stm32mp25xc.dtsi Normal file
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@ -0,0 +1,8 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
/ {
};

8
arch/arm64/boot/dts/st/stm32mp25xf.dtsi Normal file
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@ -0,0 +1,8 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
/ {
};

83
arch/arm64/boot/dts/st/stm32mp25xxai-pinctrl.dtsi Normal file
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@ -0,0 +1,83 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
&pinctrl {
st,package = <STM32MP_PKG_AI>;
gpioa: gpio@44240000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 0 16>;
};
gpiob: gpio@44250000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 16 16>;
};
gpioc: gpio@44260000 {
status = "okay";
ngpios = <14>;
gpio-ranges = <&pinctrl 0 32 14>;
};
gpiod: gpio@44270000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 48 16>;
};
gpioe: gpio@44280000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 64 16>;
};
gpiof: gpio@44290000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 80 16>;
};
gpiog: gpio@442a0000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 96 16>;
};
gpioh: gpio@442b0000 {
status = "okay";
ngpios = <12>;
gpio-ranges = <&pinctrl 2 114 12>;
};
gpioi: gpio@442c0000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 128 16>;
};
gpioj: gpio@442d0000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 144 16>;
};
gpiok: gpio@442e0000 {
status = "okay";
ngpios = <8>;
gpio-ranges = <&pinctrl 0 160 8>;
};
};
&pinctrl_z {
gpioz: gpio@46200000 {
status = "okay";
ngpios = <10>;
gpio-ranges = <&pinctrl_z 0 400 10>;
};
};

71
arch/arm64/boot/dts/st/stm32mp25xxak-pinctrl.dtsi Normal file
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@ -0,0 +1,71 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
&pinctrl {
st,package = <STM32MP_PKG_AK>;
gpioa: gpio@44240000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 0 16>;
};
gpiob: gpio@44250000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 16 16>;
};
gpioc: gpio@44260000 {
status = "okay";
ngpios = <14>;
gpio-ranges = <&pinctrl 0 32 14>;
};
gpiod: gpio@44270000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 48 16>;
};
gpioe: gpio@44280000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 64 16>;
};
gpiof: gpio@44290000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 80 16>;
};
gpiog: gpio@442a0000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 96 16>;
};
gpioh: gpio@442b0000 {
status = "okay";
ngpios = <12>;
gpio-ranges = <&pinctrl 2 114 12>;
};
gpioi: gpio@442c0000 {
status = "okay";
ngpios = <12>;
gpio-ranges = <&pinctrl 0 128 12>;
};
};
&pinctrl_z {
gpioz: gpio@46200000 {
status = "okay";
ngpios = <10>;
gpio-ranges = <&pinctrl_z 0 400 10>;
};
};

71
arch/arm64/boot/dts/st/stm32mp25xxal-pinctrl.dtsi Normal file
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@ -0,0 +1,71 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
&pinctrl {
st,package = <STM32MP_PKG_AL>;
gpioa: gpio@44240000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 0 16>;
};
gpiob: gpio@44250000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 16 16>;
};
gpioc: gpio@44260000 {
status = "okay";
ngpios = <14>;
gpio-ranges = <&pinctrl 0 32 14>;
};
gpiod: gpio@44270000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 48 16>;
};
gpioe: gpio@44280000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 64 16>;
};
gpiof: gpio@44290000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 80 16>;
};
gpiog: gpio@442a0000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 96 16>;
};
gpioh: gpio@442b0000 {
status = "okay";
ngpios = <12>;
gpio-ranges = <&pinctrl 2 114 12>;
};
gpioi: gpio@442c0000 {
status = "okay";
ngpios = <12>;
gpio-ranges = <&pinctrl 0 128 12>;
};
};
&pinctrl_z {
gpioz: gpio@46200000 {
status = "okay";
ngpios = <10>;
gpio-ranges = <&pinctrl_z 0 400 10>;
};
};

3
arch/arm64/configs/defconfig
View File

@ -59,6 +59,7 @@ CONFIG_ARCH_RENESAS=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_ARCH_SEATTLE=y
CONFIG_ARCH_INTEL_SOCFPGA=y
CONFIG_ARCH_STM32=y
CONFIG_ARCH_SYNQUACER=y
CONFIG_ARCH_TEGRA=y
CONFIG_ARCH_TESLA_FSD=y
@ -462,6 +463,8 @@ CONFIG_SERIAL_FSL_LPUART=y
CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
CONFIG_SERIAL_FSL_LINFLEXUART=y
CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y
CONFIG_SERIAL_STM32=y
CONFIG_SERIAL_STM32_CONSOLE=y
CONFIG_SERIAL_MVEBU_UART=y
CONFIG_SERIAL_OWL=y
CONFIG_SERIAL_DEV_BUS=y

6
drivers/pinctrl/stm32/Kconfig
View File

@ -51,4 +51,10 @@ config PINCTRL_STM32MP157
depends on OF && HAS_IOMEM
default MACH_STM32MP157
select PINCTRL_STM32
config PINCTRL_STM32MP257
bool "STMicroelectronics STM32MP257 pin control" if COMPILE_TEST && !MACH_STM32MP25
depends on OF && HAS_IOMEM
default MACH_STM32MP25
select PINCTRL_STM32
endif

1
drivers/pinctrl/stm32/Makefile
View File

@ -10,3 +10,4 @@ obj-$(CONFIG_PINCTRL_STM32F769) += pinctrl-stm32f769.o
obj-$(CONFIG_PINCTRL_STM32H743) += pinctrl-stm32h743.o
obj-$(CONFIG_PINCTRL_STM32MP135) += pinctrl-stm32mp135.o
obj-$(CONFIG_PINCTRL_STM32MP157) += pinctrl-stm32mp157.o
obj-$(CONFIG_PINCTRL_STM32MP257) += pinctrl-stm32mp257.o

3
drivers/pinctrl/stm32/pinctrl-stm32.h
View File

@ -24,6 +24,9 @@
#define STM32MP_PKG_AB BIT(1)
#define STM32MP_PKG_AC BIT(2)
#define STM32MP_PKG_AD BIT(3)
#define STM32MP_PKG_AI BIT(8)
#define STM32MP_PKG_AK BIT(10)
#define STM32MP_PKG_AL BIT(11)
struct stm32_desc_function {
const char *name;

2581
drivers/pinctrl/stm32/pinctrl-stm32mp257.c Normal file
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File diff suppressed because it is too large Load Diff

3
include/dt-bindings/pinctrl/stm32-pinfunc.h
View File

@ -37,6 +37,9 @@
#define STM32MP_PKG_AB 0x2
#define STM32MP_PKG_AC 0x4
#define STM32MP_PKG_AD 0x8
#define STM32MP_PKG_AI 0x100
#define STM32MP_PKG_AK 0x400
#define STM32MP_PKG_AL 0x800
#endif /* _DT_BINDINGS_STM32_PINFUNC_H */