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gpio: add gpio offset in gpio range cells property 

Add gpio offset into "gpio-range-cells" property. It's used to support
sparse pinctrl range in gpio chip.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Haojian Zhuang 2013-02-17 19:42:47 +08:00 committed by Linus Walleij
parent e392971494
commit 86853c83e3
6 changed files with 13 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
Documentation/devicetree/bindings/gpio/gpio.txt
View File

@ -98,7 +98,7 @@ announce the pinrange to the pin ctrl subsystem. For example,
compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank"; compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
reg = <0x1460 0x18>; reg = <0x1460 0x18>;
gpio-controller; gpio-controller;
gpio-ranges = <&pinctrl1 20 10>, <&pinctrl2 50 20>; gpio-ranges = <&pinctrl1 0 20 10>, <&pinctrl2 10 50 20>;
} }
@ -107,8 +107,8 @@ where,
Next values specify the base pin and number of pins for the range Next values specify the base pin and number of pins for the range
handled by 'qe_pio_e' gpio. In the given example from base pin 20 to handled by 'qe_pio_e' gpio. In the given example from base pin 20 to
pin 29 under pinctrl1 and pin 50 to pin 69 under pinctrl2 is handled pin 29 under pinctrl1 with gpio offset 0 and pin 50 to pin 69 under
by this gpio controller. pinctrl2 with gpio offset 10 is handled by this gpio controller.
The pinctrl node must have "#gpio-range-cells" property to show number of The pinctrl node must have "#gpio-range-cells" property to show number of
arguments to pass with phandle from gpio controllers node. arguments to pass with phandle from gpio controllers node.

4
arch/arm/boot/dts/spear1310.dtsi
View File

@ -89,7 +89,7 @@
pinmux: pinmux@e0700000 { pinmux: pinmux@e0700000 {
compatible = "st,spear1310-pinmux"; compatible = "st,spear1310-pinmux";
reg = <0xe0700000 0x1000>; reg = <0xe0700000 0x1000>;
#gpio-range-cells = <2>; #gpio-range-cells = <3>;
}; };
apb { apb {
@ -212,7 +212,7 @@
interrupt-controller; interrupt-controller;
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;
gpio-ranges = <&pinmux 0 246>; gpio-ranges = <&pinmux 0 0 246>;
status = "disabled"; status = "disabled";
st-plgpio,ngpio = <246>; st-plgpio,ngpio = <246>;

4
arch/arm/boot/dts/spear1340.dtsi
View File

@ -63,7 +63,7 @@
pinmux: pinmux@e0700000 { pinmux: pinmux@e0700000 {
compatible = "st,spear1340-pinmux"; compatible = "st,spear1340-pinmux";
reg = <0xe0700000 0x1000>; reg = <0xe0700000 0x1000>;
#gpio-range-cells = <2>; #gpio-range-cells = <3>;
}; };
pwm: pwm@e0180000 { pwm: pwm@e0180000 {
@ -127,7 +127,7 @@
interrupt-controller; interrupt-controller;
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;
gpio-ranges = <&pinmux 0 252>; gpio-ranges = <&pinmux 0 0 252>;
status = "disabled"; status = "disabled";
st-plgpio,ngpio = <250>; st-plgpio,ngpio = <250>;

4
arch/arm/boot/dts/spear310.dtsi
View File

@ -25,7 +25,7 @@
pinmux: pinmux@b4000000 { pinmux: pinmux@b4000000 {
compatible = "st,spear310-pinmux"; compatible = "st,spear310-pinmux";
reg = <0xb4000000 0x1000>; reg = <0xb4000000 0x1000>;
#gpio-range-cells = <2>; #gpio-range-cells = <3>;
}; };
fsmc: flash@44000000 { fsmc: flash@44000000 {
@ -102,7 +102,7 @@
interrupt-controller; interrupt-controller;
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;
gpio-ranges = <&pinmux 0 102>; gpio-ranges = <&pinmux 0 0 102>;
status = "disabled"; status = "disabled";
st-plgpio,ngpio = <102>; st-plgpio,ngpio = <102>;

4
arch/arm/boot/dts/spear320.dtsi
View File

@ -24,7 +24,7 @@
pinmux: pinmux@b3000000 { pinmux: pinmux@b3000000 {
compatible = "st,spear320-pinmux"; compatible = "st,spear320-pinmux";
reg = <0xb3000000 0x1000>; reg = <0xb3000000 0x1000>;
#gpio-range-cells = <2>; #gpio-range-cells = <3>;
}; };
clcd@90000000 { clcd@90000000 {
@ -130,7 +130,7 @@
interrupt-controller; interrupt-controller;
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;
gpio-ranges = <&pinmux 0 102>; gpio-ranges = <&pinmux 0 0 102>;
status = "disabled"; status = "disabled";
st-plgpio,ngpio = <102>; st-plgpio,ngpio = <102>;

15
drivers/gpio/gpiolib-of.c
View File

@ -203,22 +203,11 @@ static void of_gpiochip_add_pin_range(struct gpio_chip *chip)
if (!pctldev) if (!pctldev)
break; break;
/*
* This assumes that the n GPIO pins are consecutive in the
* GPIO number space, and that the pins are also consecutive
* in their local number space. Currently it is not possible
* to add different ranges for one and the same GPIO chip,
* as the code assumes that we have one consecutive range
* on both, mapping 1-to-1.
*
* TODO: make the OF bindings handle multiple sparse ranges
* on the same GPIO chip.
*/
ret = gpiochip_add_pin_range(chip, ret = gpiochip_add_pin_range(chip,
pinctrl_dev_get_devname(pctldev), pinctrl_dev_get_devname(pctldev),
0, /* offset in gpiochip */
pinspec.args[0], pinspec.args[0],
pinspec.args[1]); pinspec.args[1],
pinspec.args[2]);
if (ret) if (ret)
break; break;