x86/mm: Add support for 5-level paging for KASLR
With 5-level paging randomization happens on P4D level instead of PUD. Maximum amount of physical memory also bumped to 52-bits for 5-level paging. Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Andy Lutomirski <luto@kernel.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Brian Gerst <brgerst@gmail.com> Cc: Dave Hansen <dave.hansen@intel.com> Cc: Denys Vlasenko <dvlasenk@redhat.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Josh Poimboeuf <jpoimboe@redhat.com> Cc: Kees Cook <keescook@chromium.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-arch@vger.kernel.org Cc: linux-mm@kvack.org Link: http://lkml.kernel.org/r/20170606113133.22974-13-kirill.shutemov@linux.intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
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@ -6,12 +6,12 @@
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*
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*
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* Entropy is generated using the KASLR early boot functions now shared in
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* Entropy is generated using the KASLR early boot functions now shared in
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* the lib directory (originally written by Kees Cook). Randomization is
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* the lib directory (originally written by Kees Cook). Randomization is
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* done on PGD & PUD page table levels to increase possible addresses. The
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* done on PGD & P4D/PUD page table levels to increase possible addresses.
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* physical memory mapping code was adapted to support PUD level virtual
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* The physical memory mapping code was adapted to support P4D/PUD level
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* addresses. This implementation on the best configuration provides 30,000
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* virtual addresses. This implementation on the best configuration provides
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* possible virtual addresses in average for each memory region. An additional
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* 30,000 possible virtual addresses in average for each memory region.
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* low memory page is used to ensure each CPU can start with a PGD aligned
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* An additional low memory page is used to ensure each CPU can start with
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* virtual address (for realmode).
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* a PGD aligned virtual address (for realmode).
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*
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*
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* The order of each memory region is not changed. The feature looks at
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* The order of each memory region is not changed. The feature looks at
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* the available space for the regions based on different configuration
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* the available space for the regions based on different configuration
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@ -70,7 +70,7 @@ static __initdata struct kaslr_memory_region {
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unsigned long *base;
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unsigned long *base;
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unsigned long size_tb;
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unsigned long size_tb;
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} kaslr_regions[] = {
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} kaslr_regions[] = {
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{ &page_offset_base, 64/* Maximum */ },
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{ &page_offset_base, 1 << (__PHYSICAL_MASK_SHIFT - TB_SHIFT) /* Maximum */ },
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{ &vmalloc_base, VMALLOC_SIZE_TB },
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{ &vmalloc_base, VMALLOC_SIZE_TB },
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{ &vmemmap_base, 1 },
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{ &vmemmap_base, 1 },
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};
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};
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@ -142,6 +142,9 @@ void __init kernel_randomize_memory(void)
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*/
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*/
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entropy = remain_entropy / (ARRAY_SIZE(kaslr_regions) - i);
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entropy = remain_entropy / (ARRAY_SIZE(kaslr_regions) - i);
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prandom_bytes_state(&rand_state, &rand, sizeof(rand));
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prandom_bytes_state(&rand_state, &rand, sizeof(rand));
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if (IS_ENABLED(CONFIG_X86_5LEVEL))
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entropy = (rand % (entropy + 1)) & P4D_MASK;
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else
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entropy = (rand % (entropy + 1)) & PUD_MASK;
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entropy = (rand % (entropy + 1)) & PUD_MASK;
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vaddr += entropy;
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vaddr += entropy;
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*kaslr_regions[i].base = vaddr;
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*kaslr_regions[i].base = vaddr;
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@ -151,27 +154,21 @@ void __init kernel_randomize_memory(void)
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* randomization alignment.
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* randomization alignment.
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*/
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*/
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vaddr += get_padding(&kaslr_regions[i]);
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vaddr += get_padding(&kaslr_regions[i]);
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if (IS_ENABLED(CONFIG_X86_5LEVEL))
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vaddr = round_up(vaddr + 1, P4D_SIZE);
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else
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vaddr = round_up(vaddr + 1, PUD_SIZE);
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vaddr = round_up(vaddr + 1, PUD_SIZE);
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remain_entropy -= entropy;
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remain_entropy -= entropy;
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}
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}
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}
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}
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/*
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static void __meminit init_trampoline_pud(void)
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* Create PGD aligned trampoline table to allow real mode initialization
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* of additional CPUs. Consume only 1 low memory page.
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*/
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void __meminit init_trampoline(void)
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{
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{
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unsigned long paddr, paddr_next;
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unsigned long paddr, paddr_next;
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pgd_t *pgd;
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pgd_t *pgd;
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pud_t *pud_page, *pud_page_tramp;
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pud_t *pud_page, *pud_page_tramp;
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int i;
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int i;
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if (!kaslr_memory_enabled()) {
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init_trampoline_default();
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return;
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}
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pud_page_tramp = alloc_low_page();
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pud_page_tramp = alloc_low_page();
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paddr = 0;
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paddr = 0;
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@ -192,3 +189,49 @@ void __meminit init_trampoline(void)
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set_pgd(&trampoline_pgd_entry,
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set_pgd(&trampoline_pgd_entry,
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__pgd(_KERNPG_TABLE | __pa(pud_page_tramp)));
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__pgd(_KERNPG_TABLE | __pa(pud_page_tramp)));
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}
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}
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static void __meminit init_trampoline_p4d(void)
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{
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unsigned long paddr, paddr_next;
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pgd_t *pgd;
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p4d_t *p4d_page, *p4d_page_tramp;
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int i;
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p4d_page_tramp = alloc_low_page();
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paddr = 0;
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pgd = pgd_offset_k((unsigned long)__va(paddr));
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p4d_page = (p4d_t *) pgd_page_vaddr(*pgd);
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for (i = p4d_index(paddr); i < PTRS_PER_P4D; i++, paddr = paddr_next) {
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p4d_t *p4d, *p4d_tramp;
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unsigned long vaddr = (unsigned long)__va(paddr);
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p4d_tramp = p4d_page_tramp + p4d_index(paddr);
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p4d = p4d_page + p4d_index(vaddr);
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paddr_next = (paddr & P4D_MASK) + P4D_SIZE;
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*p4d_tramp = *p4d;
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}
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set_pgd(&trampoline_pgd_entry,
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__pgd(_KERNPG_TABLE | __pa(p4d_page_tramp)));
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}
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/*
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* Create PGD aligned trampoline table to allow real mode initialization
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* of additional CPUs. Consume only 1 low memory page.
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*/
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void __meminit init_trampoline(void)
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{
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if (!kaslr_memory_enabled()) {
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init_trampoline_default();
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return;
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}
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if (IS_ENABLED(CONFIG_X86_5LEVEL))
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init_trampoline_p4d();
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else
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init_trampoline_pud();
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}
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