spi: stm32: rename STM32 SPI registers to STM32H7
Rename STM32 SPI registers to be related to STM32H7 SPI driver and not STM32 generally. Signed-off-by: Cezary Gapinski <cezary.gapinski@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Cezary Gapinski
Mark Brown
parent
6962b055a1
commit
8602663096
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@ -20,86 +20,86 @@
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#define DRIVER_NAME "spi_stm32"
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/* STM32 SPI registers */
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#define STM32_SPI_CR1 0x00
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#define STM32_SPI_CR2 0x04
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#define STM32_SPI_CFG1 0x08
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#define STM32_SPI_CFG2 0x0C
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#define STM32_SPI_IER 0x10
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#define STM32_SPI_SR 0x14
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#define STM32_SPI_IFCR 0x18
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#define STM32_SPI_TXDR 0x20
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#define STM32_SPI_RXDR 0x30
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#define STM32_SPI_I2SCFGR 0x50
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/* STM32H7 SPI registers */
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#define STM32H7_SPI_CR1 0x00
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#define STM32H7_SPI_CR2 0x04
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#define STM32H7_SPI_CFG1 0x08
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#define STM32H7_SPI_CFG2 0x0C
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#define STM32H7_SPI_IER 0x10
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#define STM32H7_SPI_SR 0x14
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#define STM32H7_SPI_IFCR 0x18
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#define STM32H7_SPI_TXDR 0x20
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#define STM32H7_SPI_RXDR 0x30
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#define STM32H7_SPI_I2SCFGR 0x50
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/* STM32_SPI_CR1 bit fields */
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#define SPI_CR1_SPE BIT(0)
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#define SPI_CR1_MASRX BIT(8)
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#define SPI_CR1_CSTART BIT(9)
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#define SPI_CR1_CSUSP BIT(10)
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#define SPI_CR1_HDDIR BIT(11)
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#define SPI_CR1_SSI BIT(12)
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/* STM32H7_SPI_CR1 bit fields */
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#define STM32H7_SPI_CR1_SPE BIT(0)
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#define STM32H7_SPI_CR1_MASRX BIT(8)
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#define STM32H7_SPI_CR1_CSTART BIT(9)
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#define STM32H7_SPI_CR1_CSUSP BIT(10)
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#define STM32H7_SPI_CR1_HDDIR BIT(11)
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#define STM32H7_SPI_CR1_SSI BIT(12)
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/* STM32_SPI_CR2 bit fields */
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#define SPI_CR2_TSIZE_SHIFT 0
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#define SPI_CR2_TSIZE GENMASK(15, 0)
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/* STM32H7_SPI_CR2 bit fields */
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#define STM32H7_SPI_CR2_TSIZE_SHIFT 0
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#define STM32H7_SPI_CR2_TSIZE GENMASK(15, 0)
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/* STM32_SPI_CFG1 bit fields */
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#define SPI_CFG1_DSIZE_SHIFT 0
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#define SPI_CFG1_DSIZE GENMASK(4, 0)
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#define SPI_CFG1_FTHLV_SHIFT 5
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#define SPI_CFG1_FTHLV GENMASK(8, 5)
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#define SPI_CFG1_RXDMAEN BIT(14)
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#define SPI_CFG1_TXDMAEN BIT(15)
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#define SPI_CFG1_MBR_SHIFT 28
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#define SPI_CFG1_MBR GENMASK(30, 28)
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#define SPI_CFG1_MBR_MIN 0
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#define SPI_CFG1_MBR_MAX (GENMASK(30, 28) >> 28)
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/* STM32H7_SPI_CFG1 bit fields */
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#define STM32H7_SPI_CFG1_DSIZE_SHIFT 0
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#define STM32H7_SPI_CFG1_DSIZE GENMASK(4, 0)
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#define STM32H7_SPI_CFG1_FTHLV_SHIFT 5
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#define STM32H7_SPI_CFG1_FTHLV GENMASK(8, 5)
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#define STM32H7_SPI_CFG1_RXDMAEN BIT(14)
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#define STM32H7_SPI_CFG1_TXDMAEN BIT(15)
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#define STM32H7_SPI_CFG1_MBR_SHIFT 28
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#define STM32H7_SPI_CFG1_MBR GENMASK(30, 28)
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#define STM32H7_SPI_CFG1_MBR_MIN 0
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#define STM32H7_SPI_CFG1_MBR_MAX (GENMASK(30, 28) >> 28)
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/* STM32_SPI_CFG2 bit fields */
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#define SPI_CFG2_MIDI_SHIFT 4
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#define SPI_CFG2_MIDI GENMASK(7, 4)
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#define SPI_CFG2_COMM_SHIFT 17
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#define SPI_CFG2_COMM GENMASK(18, 17)
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#define SPI_CFG2_SP_SHIFT 19
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#define SPI_CFG2_SP GENMASK(21, 19)
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#define SPI_CFG2_MASTER BIT(22)
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#define SPI_CFG2_LSBFRST BIT(23)
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#define SPI_CFG2_CPHA BIT(24)
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#define SPI_CFG2_CPOL BIT(25)
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#define SPI_CFG2_SSM BIT(26)
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#define SPI_CFG2_AFCNTR BIT(31)
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/* STM32H7_SPI_CFG2 bit fields */
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#define STM32H7_SPI_CFG2_MIDI_SHIFT 4
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#define STM32H7_SPI_CFG2_MIDI GENMASK(7, 4)
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#define STM32H7_SPI_CFG2_COMM_SHIFT 17
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#define STM32H7_SPI_CFG2_COMM GENMASK(18, 17)
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#define STM32H7_SPI_CFG2_SP_SHIFT 19
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#define STM32H7_SPI_CFG2_SP GENMASK(21, 19)
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#define STM32H7_SPI_CFG2_MASTER BIT(22)
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#define STM32H7_SPI_CFG2_LSBFRST BIT(23)
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#define STM32H7_SPI_CFG2_CPHA BIT(24)
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#define STM32H7_SPI_CFG2_CPOL BIT(25)
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#define STM32H7_SPI_CFG2_SSM BIT(26)
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#define STM32H7_SPI_CFG2_AFCNTR BIT(31)
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/* STM32_SPI_IER bit fields */
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#define SPI_IER_RXPIE BIT(0)
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#define SPI_IER_TXPIE BIT(1)
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#define SPI_IER_DXPIE BIT(2)
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#define SPI_IER_EOTIE BIT(3)
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#define SPI_IER_TXTFIE BIT(4)
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#define SPI_IER_OVRIE BIT(6)
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#define SPI_IER_MODFIE BIT(9)
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#define SPI_IER_ALL GENMASK(10, 0)
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/* STM32H7_SPI_IER bit fields */
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#define STM32H7_SPI_IER_RXPIE BIT(0)
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#define STM32H7_SPI_IER_TXPIE BIT(1)
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#define STM32H7_SPI_IER_DXPIE BIT(2)
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#define STM32H7_SPI_IER_EOTIE BIT(3)
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#define STM32H7_SPI_IER_TXTFIE BIT(4)
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#define STM32H7_SPI_IER_OVRIE BIT(6)
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#define STM32H7_SPI_IER_MODFIE BIT(9)
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#define STM32H7_SPI_IER_ALL GENMASK(10, 0)
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/* STM32_SPI_SR bit fields */
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#define SPI_SR_RXP BIT(0)
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#define SPI_SR_TXP BIT(1)
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#define SPI_SR_EOT BIT(3)
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#define SPI_SR_OVR BIT(6)
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#define SPI_SR_MODF BIT(9)
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#define SPI_SR_SUSP BIT(11)
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#define SPI_SR_RXPLVL_SHIFT 13
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#define SPI_SR_RXPLVL GENMASK(14, 13)
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#define SPI_SR_RXWNE BIT(15)
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/* STM32H7_SPI_SR bit fields */
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#define STM32H7_SPI_SR_RXP BIT(0)
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#define STM32H7_SPI_SR_TXP BIT(1)
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#define STM32H7_SPI_SR_EOT BIT(3)
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#define STM32H7_SPI_SR_OVR BIT(6)
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#define STM32H7_SPI_SR_MODF BIT(9)
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#define STM32H7_SPI_SR_SUSP BIT(11)
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#define STM32H7_SPI_SR_RXPLVL_SHIFT 13
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#define STM32H7_SPI_SR_RXPLVL GENMASK(14, 13)
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#define STM32H7_SPI_SR_RXWNE BIT(15)
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/* STM32_SPI_IFCR bit fields */
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#define SPI_IFCR_ALL GENMASK(11, 3)
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/* STM32H7_SPI_IFCR bit fields */
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#define STM32H7_SPI_IFCR_ALL GENMASK(11, 3)
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/* STM32_SPI_I2SCFGR bit fields */
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#define SPI_I2SCFGR_I2SMOD BIT(0)
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/* STM32H7_SPI_I2SCFGR bit fields */
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#define STM32H7_SPI_I2SCFGR_I2SMOD BIT(0)
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/* SPI Master Baud Rate min/max divisor */
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#define SPI_MBR_DIV_MIN (2 << SPI_CFG1_MBR_MIN)
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#define SPI_MBR_DIV_MAX (2 << SPI_CFG1_MBR_MAX)
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/* STM32H7 SPI Master Baud Rate min/max divisor */
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#define STM32H7_SPI_MBR_DIV_MIN (2 << STM32H7_SPI_CFG1_MBR_MIN)
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#define STM32H7_SPI_MBR_DIV_MAX (2 << STM32H7_SPI_CFG1_MBR_MAX)
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/* SPI Communication mode */
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#define SPI_FULL_DUPLEX 0
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@ -188,12 +188,12 @@ static int stm32_spi_get_fifo_size(struct stm32_spi *spi)
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spin_lock_irqsave(&spi->lock, flags);
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stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_SPE);
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stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
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while (readl_relaxed(spi->base + STM32_SPI_SR) & SPI_SR_TXP)
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writeb_relaxed(++count, spi->base + STM32_SPI_TXDR);
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while (readl_relaxed(spi->base + STM32H7_SPI_SR) & STM32H7_SPI_SR_TXP)
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writeb_relaxed(++count, spi->base + STM32H7_SPI_TXDR);
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stm32_spi_clr_bits(spi, STM32_SPI_CR1, SPI_CR1_SPE);
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stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
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spin_unlock_irqrestore(&spi->lock, flags);
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@ -217,10 +217,11 @@ static int stm32_spi_get_bpw_mask(struct stm32_spi *spi)
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* The most significant bit at DSIZE bit field is reserved when the
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* maximum data size of periperal instances is limited to 16-bit
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*/
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stm32_spi_set_bits(spi, STM32_SPI_CFG1, SPI_CFG1_DSIZE);
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stm32_spi_set_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_DSIZE);
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cfg1 = readl_relaxed(spi->base + STM32_SPI_CFG1);
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max_bpw = (cfg1 & SPI_CFG1_DSIZE) >> SPI_CFG1_DSIZE_SHIFT;
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cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1);
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max_bpw = (cfg1 & STM32H7_SPI_CFG1_DSIZE) >>
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STM32H7_SPI_CFG1_DSIZE_SHIFT;
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max_bpw += 1;
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spin_unlock_irqrestore(&spi->lock, flags);
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@ -250,8 +251,8 @@ static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz)
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* no need to check it there.
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* However, we need to ensure the following calculations.
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*/
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if (div < SPI_MBR_DIV_MIN ||
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div > SPI_MBR_DIV_MAX)
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if (div < STM32H7_SPI_MBR_DIV_MIN ||
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div > STM32H7_SPI_MBR_DIV_MAX)
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return -EINVAL;
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/* Determine the first power of 2 greater than or equal to div */
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@ -302,23 +303,24 @@ static u32 stm32_spi_prepare_fthlv(struct stm32_spi *spi)
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static void stm32_spi_write_txfifo(struct stm32_spi *spi)
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{
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while ((spi->tx_len > 0) &&
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(readl_relaxed(spi->base + STM32_SPI_SR) & SPI_SR_TXP)) {
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(readl_relaxed(spi->base + STM32H7_SPI_SR) &
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STM32H7_SPI_SR_TXP)) {
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u32 offs = spi->cur_xferlen - spi->tx_len;
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if (spi->tx_len >= sizeof(u32)) {
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const u32 *tx_buf32 = (const u32 *)(spi->tx_buf + offs);
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writel_relaxed(*tx_buf32, spi->base + STM32_SPI_TXDR);
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writel_relaxed(*tx_buf32, spi->base + STM32H7_SPI_TXDR);
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spi->tx_len -= sizeof(u32);
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} else if (spi->tx_len >= sizeof(u16)) {
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const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs);
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writew_relaxed(*tx_buf16, spi->base + STM32_SPI_TXDR);
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writew_relaxed(*tx_buf16, spi->base + STM32H7_SPI_TXDR);
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spi->tx_len -= sizeof(u16);
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} else {
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const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs);
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writeb_relaxed(*tx_buf8, spi->base + STM32_SPI_TXDR);
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writeb_relaxed(*tx_buf8, spi->base + STM32H7_SPI_TXDR);
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spi->tx_len -= sizeof(u8);
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}
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}
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@ -335,35 +337,37 @@ static void stm32_spi_write_txfifo(struct stm32_spi *spi)
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*/
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static void stm32_spi_read_rxfifo(struct stm32_spi *spi, bool flush)
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{
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u32 sr = readl_relaxed(spi->base + STM32_SPI_SR);
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u32 rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT;
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u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
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u32 rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >>
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STM32H7_SPI_SR_RXPLVL_SHIFT;
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while ((spi->rx_len > 0) &&
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((sr & SPI_SR_RXP) ||
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(flush && ((sr & SPI_SR_RXWNE) || (rxplvl > 0))))) {
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((sr & STM32H7_SPI_SR_RXP) ||
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(flush && ((sr & STM32H7_SPI_SR_RXWNE) || (rxplvl > 0))))) {
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u32 offs = spi->cur_xferlen - spi->rx_len;
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if ((spi->rx_len >= sizeof(u32)) ||
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(flush && (sr & SPI_SR_RXWNE))) {
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(flush && (sr & STM32H7_SPI_SR_RXWNE))) {
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u32 *rx_buf32 = (u32 *)(spi->rx_buf + offs);
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*rx_buf32 = readl_relaxed(spi->base + STM32_SPI_RXDR);
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*rx_buf32 = readl_relaxed(spi->base + STM32H7_SPI_RXDR);
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spi->rx_len -= sizeof(u32);
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} else if ((spi->rx_len >= sizeof(u16)) ||
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(flush && (rxplvl >= 2 || spi->cur_bpw > 8))) {
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u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
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*rx_buf16 = readw_relaxed(spi->base + STM32_SPI_RXDR);
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*rx_buf16 = readw_relaxed(spi->base + STM32H7_SPI_RXDR);
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spi->rx_len -= sizeof(u16);
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} else {
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u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs);
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*rx_buf8 = readb_relaxed(spi->base + STM32_SPI_RXDR);
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*rx_buf8 = readb_relaxed(spi->base + STM32H7_SPI_RXDR);
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spi->rx_len -= sizeof(u8);
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}
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sr = readl_relaxed(spi->base + STM32_SPI_SR);
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rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT;
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sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
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rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >>
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STM32H7_SPI_SR_RXPLVL_SHIFT;
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}
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dev_dbg(spi->dev, "%s%s: %d bytes left\n", __func__,
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@ -381,7 +385,7 @@ static void stm32_spi_enable(struct stm32_spi *spi)
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{
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dev_dbg(spi->dev, "enable controller\n");
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stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_SPE);
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stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
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}
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/**
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@ -401,23 +405,23 @@ static void stm32_spi_disable(struct stm32_spi *spi)
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spin_lock_irqsave(&spi->lock, flags);
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cr1 = readl_relaxed(spi->base + STM32_SPI_CR1);
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cr1 = readl_relaxed(spi->base + STM32H7_SPI_CR1);
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if (!(cr1 & SPI_CR1_SPE)) {
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if (!(cr1 & STM32H7_SPI_CR1_SPE)) {
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spin_unlock_irqrestore(&spi->lock, flags);
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return;
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}
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/* Wait on EOT or suspend the flow */
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if (readl_relaxed_poll_timeout_atomic(spi->base + STM32_SPI_SR,
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sr, !(sr & SPI_SR_EOT),
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if (readl_relaxed_poll_timeout_atomic(spi->base + STM32H7_SPI_SR,
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sr, !(sr & STM32H7_SPI_SR_EOT),
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10, 100000) < 0) {
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if (cr1 & SPI_CR1_CSTART) {
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writel_relaxed(cr1 | SPI_CR1_CSUSP,
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spi->base + STM32_SPI_CR1);
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if (cr1 & STM32H7_SPI_CR1_CSTART) {
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writel_relaxed(cr1 | STM32H7_SPI_CR1_CSUSP,
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spi->base + STM32H7_SPI_CR1);
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if (readl_relaxed_poll_timeout_atomic(
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spi->base + STM32_SPI_SR,
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sr, !(sr & SPI_SR_SUSP),
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spi->base + STM32H7_SPI_SR,
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sr, !(sr & STM32H7_SPI_SR_SUSP),
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10, 100000) < 0)
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dev_warn(spi->dev,
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"Suspend request timeout\n");
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@ -432,14 +436,14 @@ static void stm32_spi_disable(struct stm32_spi *spi)
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if (spi->cur_usedma && spi->dma_rx)
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dmaengine_terminate_all(spi->dma_rx);
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stm32_spi_clr_bits(spi, STM32_SPI_CR1, SPI_CR1_SPE);
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stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
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stm32_spi_clr_bits(spi, STM32_SPI_CFG1, SPI_CFG1_TXDMAEN |
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SPI_CFG1_RXDMAEN);
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stm32_spi_clr_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN |
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STM32H7_SPI_CFG1_RXDMAEN);
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/* Disable interrupts and clear status flags */
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writel_relaxed(0, spi->base + STM32_SPI_IER);
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writel_relaxed(SPI_IFCR_ALL, spi->base + STM32_SPI_IFCR);
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writel_relaxed(0, spi->base + STM32H7_SPI_IER);
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writel_relaxed(STM32H7_SPI_IFCR_ALL, spi->base + STM32H7_SPI_IFCR);
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spin_unlock_irqrestore(&spi->lock, flags);
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}
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@ -476,19 +480,19 @@ static irqreturn_t stm32_spi_irq(int irq, void *dev_id)
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|
||||
spin_lock_irqsave(&spi->lock, flags);
|
||||
|
||||
sr = readl_relaxed(spi->base + STM32_SPI_SR);
|
||||
ier = readl_relaxed(spi->base + STM32_SPI_IER);
|
||||
sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
|
||||
ier = readl_relaxed(spi->base + STM32H7_SPI_IER);
|
||||
|
||||
mask = ier;
|
||||
/* EOTIE is triggered on EOT, SUSP and TXC events. */
|
||||
mask |= SPI_SR_SUSP;
|
||||
mask |= STM32H7_SPI_SR_SUSP;
|
||||
/*
|
||||
* When TXTF is set, DXPIE and TXPIE are cleared. So in case of
|
||||
* Full-Duplex, need to poll RXP event to know if there are remaining
|
||||
* data, before disabling SPI.
|
||||
*/
|
||||
if (spi->rx_buf && !spi->cur_usedma)
|
||||
mask |= SPI_SR_RXP;
|
||||
mask |= STM32H7_SPI_SR_RXP;
|
||||
|
||||
if (!(sr & mask)) {
|
||||
dev_dbg(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n",
|
||||
|
|
@ -497,7 +501,7 @@ static irqreturn_t stm32_spi_irq(int irq, void *dev_id)
|
|||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
if (sr & SPI_SR_SUSP) {
|
||||
if (sr & STM32H7_SPI_SR_SUSP) {
|
||||
dev_warn(spi->dev, "Communication suspended\n");
|
||||
if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
|
||||
stm32_spi_read_rxfifo(spi, false);
|
||||
|
|
@ -509,12 +513,12 @@ static irqreturn_t stm32_spi_irq(int irq, void *dev_id)
|
|||
end = true;
|
||||
}
|
||||
|
||||
if (sr & SPI_SR_MODF) {
|
||||
if (sr & STM32H7_SPI_SR_MODF) {
|
||||
dev_warn(spi->dev, "Mode fault: transfer aborted\n");
|
||||
end = true;
|
||||
}
|
||||
|
||||
if (sr & SPI_SR_OVR) {
|
||||
if (sr & STM32H7_SPI_SR_OVR) {
|
||||
dev_warn(spi->dev, "Overrun: received value discarded\n");
|
||||
if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
|
||||
stm32_spi_read_rxfifo(spi, false);
|
||||
|
|
@ -526,21 +530,21 @@ static irqreturn_t stm32_spi_irq(int irq, void *dev_id)
|
|||
end = true;
|
||||
}
|
||||
|
||||
if (sr & SPI_SR_EOT) {
|
||||
if (sr & STM32H7_SPI_SR_EOT) {
|
||||
if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
|
||||
stm32_spi_read_rxfifo(spi, true);
|
||||
end = true;
|
||||
}
|
||||
|
||||
if (sr & SPI_SR_TXP)
|
||||
if (sr & STM32H7_SPI_SR_TXP)
|
||||
if (!spi->cur_usedma && (spi->tx_buf && (spi->tx_len > 0)))
|
||||
stm32_spi_write_txfifo(spi);
|
||||
|
||||
if (sr & SPI_SR_RXP)
|
||||
if (sr & STM32H7_SPI_SR_RXP)
|
||||
if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
|
||||
stm32_spi_read_rxfifo(spi, false);
|
||||
|
||||
writel_relaxed(mask, spi->base + STM32_SPI_IFCR);
|
||||
writel_relaxed(mask, spi->base + STM32H7_SPI_IFCR);
|
||||
|
||||
spin_unlock_irqrestore(&spi->lock, flags);
|
||||
|
||||
|
|
@ -593,19 +597,19 @@ static int stm32_spi_prepare_msg(struct spi_master *master,
|
|||
dev_dbg(spi->dev, "%dns inter-data idleness\n", spi->cur_midi);
|
||||
|
||||
if (spi_dev->mode & SPI_CPOL)
|
||||
cfg2_setb |= SPI_CFG2_CPOL;
|
||||
cfg2_setb |= STM32H7_SPI_CFG2_CPOL;
|
||||
else
|
||||
cfg2_clrb |= SPI_CFG2_CPOL;
|
||||
cfg2_clrb |= STM32H7_SPI_CFG2_CPOL;
|
||||
|
||||
if (spi_dev->mode & SPI_CPHA)
|
||||
cfg2_setb |= SPI_CFG2_CPHA;
|
||||
cfg2_setb |= STM32H7_SPI_CFG2_CPHA;
|
||||
else
|
||||
cfg2_clrb |= SPI_CFG2_CPHA;
|
||||
cfg2_clrb |= STM32H7_SPI_CFG2_CPHA;
|
||||
|
||||
if (spi_dev->mode & SPI_LSB_FIRST)
|
||||
cfg2_setb |= SPI_CFG2_LSBFRST;
|
||||
cfg2_setb |= STM32H7_SPI_CFG2_LSBFRST;
|
||||
else
|
||||
cfg2_clrb |= SPI_CFG2_LSBFRST;
|
||||
cfg2_clrb |= STM32H7_SPI_CFG2_LSBFRST;
|
||||
|
||||
dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n",
|
||||
spi_dev->mode & SPI_CPOL,
|
||||
|
|
@ -617,9 +621,9 @@ static int stm32_spi_prepare_msg(struct spi_master *master,
|
|||
|
||||
if (cfg2_clrb || cfg2_setb)
|
||||
writel_relaxed(
|
||||
(readl_relaxed(spi->base + STM32_SPI_CFG2) &
|
||||
(readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
|
||||
~cfg2_clrb) | cfg2_setb,
|
||||
spi->base + STM32_SPI_CFG2);
|
||||
spi->base + STM32H7_SPI_CFG2);
|
||||
|
||||
spin_unlock_irqrestore(&spi->lock, flags);
|
||||
|
||||
|
|
@ -640,11 +644,11 @@ static void stm32_spi_dma_cb(void *data)
|
|||
|
||||
spin_lock_irqsave(&spi->lock, flags);
|
||||
|
||||
sr = readl_relaxed(spi->base + STM32_SPI_SR);
|
||||
sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
|
||||
|
||||
spin_unlock_irqrestore(&spi->lock, flags);
|
||||
|
||||
if (!(sr & SPI_SR_EOT))
|
||||
if (!(sr & STM32H7_SPI_SR_EOT))
|
||||
dev_warn(spi->dev, "DMA error (sr=0x%08x)\n", sr);
|
||||
|
||||
/* Now wait for EOT, or SUSP or OVR in case of error */
|
||||
|
|
@ -677,14 +681,14 @@ static void stm32_spi_dma_config(struct stm32_spi *spi,
|
|||
memset(dma_conf, 0, sizeof(struct dma_slave_config));
|
||||
dma_conf->direction = dir;
|
||||
if (dma_conf->direction == DMA_DEV_TO_MEM) { /* RX */
|
||||
dma_conf->src_addr = spi->phys_addr + STM32_SPI_RXDR;
|
||||
dma_conf->src_addr = spi->phys_addr + STM32H7_SPI_RXDR;
|
||||
dma_conf->src_addr_width = buswidth;
|
||||
dma_conf->src_maxburst = maxburst;
|
||||
|
||||
dev_dbg(spi->dev, "Rx DMA config buswidth=%d, maxburst=%d\n",
|
||||
buswidth, maxburst);
|
||||
} else if (dma_conf->direction == DMA_MEM_TO_DEV) { /* TX */
|
||||
dma_conf->dst_addr = spi->phys_addr + STM32_SPI_TXDR;
|
||||
dma_conf->dst_addr = spi->phys_addr + STM32H7_SPI_TXDR;
|
||||
dma_conf->dst_addr_width = buswidth;
|
||||
dma_conf->dst_maxburst = maxburst;
|
||||
|
||||
|
|
@ -707,14 +711,15 @@ static int stm32_spi_transfer_one_irq(struct stm32_spi *spi)
|
|||
|
||||
/* Enable the interrupts relative to the current communication mode */
|
||||
if (spi->tx_buf && spi->rx_buf) /* Full Duplex */
|
||||
ier |= SPI_IER_DXPIE;
|
||||
ier |= STM32H7_SPI_IER_DXPIE;
|
||||
else if (spi->tx_buf) /* Half-Duplex TX dir or Simplex TX */
|
||||
ier |= SPI_IER_TXPIE;
|
||||
ier |= STM32H7_SPI_IER_TXPIE;
|
||||
else if (spi->rx_buf) /* Half-Duplex RX dir or Simplex RX */
|
||||
ier |= SPI_IER_RXPIE;
|
||||
ier |= STM32H7_SPI_IER_RXPIE;
|
||||
|
||||
/* Enable the interrupts relative to the end of transfer */
|
||||
ier |= SPI_IER_EOTIE | SPI_IER_TXTFIE | SPI_IER_OVRIE | SPI_IER_MODFIE;
|
||||
ier |= STM32H7_SPI_IER_EOTIE | STM32H7_SPI_IER_TXTFIE |
|
||||
STM32H7_SPI_IER_OVRIE | STM32H7_SPI_IER_MODFIE;
|
||||
|
||||
spin_lock_irqsave(&spi->lock, flags);
|
||||
|
||||
|
|
@ -724,9 +729,9 @@ static int stm32_spi_transfer_one_irq(struct stm32_spi *spi)
|
|||
if (spi->tx_buf)
|
||||
stm32_spi_write_txfifo(spi);
|
||||
|
||||
stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_CSTART);
|
||||
stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
|
||||
|
||||
writel_relaxed(ier, spi->base + STM32_SPI_IER);
|
||||
writel_relaxed(ier, spi->base + STM32H7_SPI_IER);
|
||||
|
||||
spin_unlock_irqrestore(&spi->lock, flags);
|
||||
|
||||
|
|
@ -755,7 +760,8 @@ static int stm32_spi_transfer_one_dma(struct stm32_spi *spi,
|
|||
dmaengine_slave_config(spi->dma_rx, &rx_dma_conf);
|
||||
|
||||
/* Enable Rx DMA request */
|
||||
stm32_spi_set_bits(spi, STM32_SPI_CFG1, SPI_CFG1_RXDMAEN);
|
||||
stm32_spi_set_bits(spi, STM32H7_SPI_CFG1,
|
||||
STM32H7_SPI_CFG1_RXDMAEN);
|
||||
|
||||
rx_dma_desc = dmaengine_prep_slave_sg(
|
||||
spi->dma_rx, xfer->rx_sg.sgl,
|
||||
|
|
@ -809,16 +815,18 @@ static int stm32_spi_transfer_one_dma(struct stm32_spi *spi,
|
|||
dma_async_issue_pending(spi->dma_tx);
|
||||
|
||||
/* Enable Tx DMA request */
|
||||
stm32_spi_set_bits(spi, STM32_SPI_CFG1, SPI_CFG1_TXDMAEN);
|
||||
stm32_spi_set_bits(spi, STM32H7_SPI_CFG1,
|
||||
STM32H7_SPI_CFG1_TXDMAEN);
|
||||
}
|
||||
|
||||
/* Enable the interrupts relative to the end of transfer */
|
||||
ier |= SPI_IER_EOTIE | SPI_IER_TXTFIE | SPI_IER_OVRIE | SPI_IER_MODFIE;
|
||||
writel_relaxed(ier, spi->base + STM32_SPI_IER);
|
||||
ier |= STM32H7_SPI_IER_EOTIE | STM32H7_SPI_IER_TXTFIE |
|
||||
STM32H7_SPI_IER_OVRIE | STM32H7_SPI_IER_MODFIE;
|
||||
writel_relaxed(ier, spi->base + STM32H7_SPI_IER);
|
||||
|
||||
stm32_spi_enable(spi);
|
||||
|
||||
stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_CSTART);
|
||||
stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
|
||||
|
||||
spin_unlock_irqrestore(&spi->lock, flags);
|
||||
|
||||
|
|
@ -829,7 +837,7 @@ dma_submit_error:
|
|||
dmaengine_terminate_all(spi->dma_rx);
|
||||
|
||||
dma_desc_error:
|
||||
stm32_spi_clr_bits(spi, STM32_SPI_CFG1, SPI_CFG1_RXDMAEN);
|
||||
stm32_spi_clr_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_RXDMAEN);
|
||||
|
||||
spin_unlock_irqrestore(&spi->lock, flags);
|
||||
|
||||
|
|
@ -861,14 +869,16 @@ static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
|
|||
spi->cur_bpw = transfer->bits_per_word;
|
||||
bpw = spi->cur_bpw - 1;
|
||||
|
||||
cfg1_clrb |= SPI_CFG1_DSIZE;
|
||||
cfg1_setb |= (bpw << SPI_CFG1_DSIZE_SHIFT) & SPI_CFG1_DSIZE;
|
||||
cfg1_clrb |= STM32H7_SPI_CFG1_DSIZE;
|
||||
cfg1_setb |= (bpw << STM32H7_SPI_CFG1_DSIZE_SHIFT) &
|
||||
STM32H7_SPI_CFG1_DSIZE;
|
||||
|
||||
spi->cur_fthlv = stm32_spi_prepare_fthlv(spi);
|
||||
fthlv = spi->cur_fthlv - 1;
|
||||
|
||||
cfg1_clrb |= SPI_CFG1_FTHLV;
|
||||
cfg1_setb |= (fthlv << SPI_CFG1_FTHLV_SHIFT) & SPI_CFG1_FTHLV;
|
||||
cfg1_clrb |= STM32H7_SPI_CFG1_FTHLV;
|
||||
cfg1_setb |= (fthlv << STM32H7_SPI_CFG1_FTHLV_SHIFT) &
|
||||
STM32H7_SPI_CFG1_FTHLV;
|
||||
}
|
||||
|
||||
if (spi->cur_speed != transfer->speed_hz) {
|
||||
|
|
@ -883,14 +893,15 @@ static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
|
|||
|
||||
transfer->speed_hz = spi->cur_speed;
|
||||
|
||||
cfg1_clrb |= SPI_CFG1_MBR;
|
||||
cfg1_setb |= ((u32)mbr << SPI_CFG1_MBR_SHIFT) & SPI_CFG1_MBR;
|
||||
cfg1_clrb |= STM32H7_SPI_CFG1_MBR;
|
||||
cfg1_setb |= ((u32)mbr << STM32H7_SPI_CFG1_MBR_SHIFT) &
|
||||
STM32H7_SPI_CFG1_MBR;
|
||||
}
|
||||
|
||||
if (cfg1_clrb || cfg1_setb)
|
||||
writel_relaxed((readl_relaxed(spi->base + STM32_SPI_CFG1) &
|
||||
writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG1) &
|
||||
~cfg1_clrb) | cfg1_setb,
|
||||
spi->base + STM32_SPI_CFG1);
|
||||
spi->base + STM32H7_SPI_CFG1);
|
||||
|
||||
mode = SPI_FULL_DUPLEX;
|
||||
if (spi_dev->mode & SPI_3WIRE) { /* MISO/MOSI signals shared */
|
||||
|
|
@ -902,9 +913,11 @@ static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
|
|||
*/
|
||||
mode = SPI_HALF_DUPLEX;
|
||||
if (!transfer->tx_buf)
|
||||
stm32_spi_clr_bits(spi, STM32_SPI_CR1, SPI_CR1_HDDIR);
|
||||
stm32_spi_clr_bits(spi, STM32H7_SPI_CR1,
|
||||
STM32H7_SPI_CR1_HDDIR);
|
||||
else if (!transfer->rx_buf)
|
||||
stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_HDDIR);
|
||||
stm32_spi_set_bits(spi, STM32H7_SPI_CR1,
|
||||
STM32H7_SPI_CR1_HDDIR);
|
||||
} else {
|
||||
if (!transfer->tx_buf)
|
||||
mode = SPI_SIMPLEX_RX;
|
||||
|
|
@ -914,26 +927,29 @@ static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
|
|||
if (spi->cur_comm != mode) {
|
||||
spi->cur_comm = mode;
|
||||
|
||||
cfg2_clrb |= SPI_CFG2_COMM;
|
||||
cfg2_setb |= (mode << SPI_CFG2_COMM_SHIFT) & SPI_CFG2_COMM;
|
||||
cfg2_clrb |= STM32H7_SPI_CFG2_COMM;
|
||||
cfg2_setb |= (mode << STM32H7_SPI_CFG2_COMM_SHIFT) &
|
||||
STM32H7_SPI_CFG2_COMM;
|
||||
}
|
||||
|
||||
cfg2_clrb |= SPI_CFG2_MIDI;
|
||||
cfg2_clrb |= STM32H7_SPI_CFG2_MIDI;
|
||||
if ((transfer->len > 1) && (spi->cur_midi > 0)) {
|
||||
u32 sck_period_ns = DIV_ROUND_UP(SPI_1HZ_NS, spi->cur_speed);
|
||||
u32 midi = min((u32)DIV_ROUND_UP(spi->cur_midi, sck_period_ns),
|
||||
(u32)SPI_CFG2_MIDI >> SPI_CFG2_MIDI_SHIFT);
|
||||
(u32)STM32H7_SPI_CFG2_MIDI >>
|
||||
STM32H7_SPI_CFG2_MIDI_SHIFT);
|
||||
|
||||
dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n",
|
||||
sck_period_ns, midi, midi * sck_period_ns);
|
||||
|
||||
cfg2_setb |= (midi << SPI_CFG2_MIDI_SHIFT) & SPI_CFG2_MIDI;
|
||||
cfg2_setb |= (midi << STM32H7_SPI_CFG2_MIDI_SHIFT) &
|
||||
STM32H7_SPI_CFG2_MIDI;
|
||||
}
|
||||
|
||||
if (cfg2_clrb || cfg2_setb)
|
||||
writel_relaxed((readl_relaxed(spi->base + STM32_SPI_CFG2) &
|
||||
writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
|
||||
~cfg2_clrb) | cfg2_setb,
|
||||
spi->base + STM32_SPI_CFG2);
|
||||
spi->base + STM32H7_SPI_CFG2);
|
||||
|
||||
if (spi->cur_bpw <= 8)
|
||||
nb_words = transfer->len;
|
||||
|
|
@ -941,10 +957,10 @@ static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
|
|||
nb_words = DIV_ROUND_UP(transfer->len * 8, 16);
|
||||
else
|
||||
nb_words = DIV_ROUND_UP(transfer->len * 8, 32);
|
||||
nb_words <<= SPI_CR2_TSIZE_SHIFT;
|
||||
nb_words <<= STM32H7_SPI_CR2_TSIZE_SHIFT;
|
||||
|
||||
if (nb_words <= SPI_CR2_TSIZE) {
|
||||
writel_relaxed(nb_words, spi->base + STM32_SPI_CR2);
|
||||
if (nb_words <= STM32H7_SPI_CR2_TSIZE) {
|
||||
writel_relaxed(nb_words, spi->base + STM32H7_SPI_CR2);
|
||||
} else {
|
||||
ret = -EMSGSIZE;
|
||||
goto out;
|
||||
|
|
@ -1030,16 +1046,17 @@ static int stm32_spi_config(struct stm32_spi *spi)
|
|||
spin_lock_irqsave(&spi->lock, flags);
|
||||
|
||||
/* Ensure I2SMOD bit is kept cleared */
|
||||
stm32_spi_clr_bits(spi, STM32_SPI_I2SCFGR, SPI_I2SCFGR_I2SMOD);
|
||||
stm32_spi_clr_bits(spi, STM32H7_SPI_I2SCFGR,
|
||||
STM32H7_SPI_I2SCFGR_I2SMOD);
|
||||
|
||||
/*
|
||||
* - SS input value high
|
||||
* - transmitter half duplex direction
|
||||
* - automatic communication suspend when RX-Fifo is full
|
||||
*/
|
||||
stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_SSI |
|
||||
SPI_CR1_HDDIR |
|
||||
SPI_CR1_MASRX);
|
||||
stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SSI |
|
||||
STM32H7_SPI_CR1_HDDIR |
|
||||
STM32H7_SPI_CR1_MASRX);
|
||||
|
||||
/*
|
||||
* - Set the master mode (default Motorola mode)
|
||||
|
|
@ -1047,9 +1064,9 @@ static int stm32_spi_config(struct stm32_spi *spi)
|
|||
* SS input value is determined by the SSI bit
|
||||
* - keep control of all associated GPIOs
|
||||
*/
|
||||
stm32_spi_set_bits(spi, STM32_SPI_CFG2, SPI_CFG2_MASTER |
|
||||
SPI_CFG2_SSM |
|
||||
SPI_CFG2_AFCNTR);
|
||||
stm32_spi_set_bits(spi, STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_MASTER |
|
||||
STM32H7_SPI_CFG2_SSM |
|
||||
STM32H7_SPI_CFG2_AFCNTR);
|
||||
|
||||
spin_unlock_irqrestore(&spi->lock, flags);
|
||||
|
||||
|
|
@ -1145,8 +1162,8 @@ static int stm32_spi_probe(struct platform_device *pdev)
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|||
master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST |
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||||
SPI_3WIRE;
|
||||
master->bits_per_word_mask = stm32_spi_get_bpw_mask(spi);
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||||
master->max_speed_hz = spi->clk_rate / SPI_MBR_DIV_MIN;
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||||
master->min_speed_hz = spi->clk_rate / SPI_MBR_DIV_MAX;
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||||
master->max_speed_hz = spi->clk_rate / STM32H7_SPI_MBR_DIV_MIN;
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||||
master->min_speed_hz = spi->clk_rate / STM32H7_SPI_MBR_DIV_MAX;
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||||
master->setup = stm32_spi_setup;
|
||||
master->prepare_message = stm32_spi_prepare_msg;
|
||||
master->transfer_one = stm32_spi_transfer_one;
|
||||
|
|
|
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Reference in New Issue