drm/sun4i: dsi: Restrict DSI tcon clock divider
The current code allows the TCON clock divider to have a range between 4 and 127 when feeding the DSI controller. The only display supported so far had a display clock rate that ended up using a divider of 4, but testing with other displays show that only 4 seems to be functional. This also aligns with what Allwinner is doing in their BSP, so let's just hardcode that we want a divider of 4 when using the DSI output. Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/074e88ae472f5e0492e26939c74b44fb4125ffbd.1549896081.git-series.maxime.ripard@bootlin.com
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@ -341,8 +341,8 @@ static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon,
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u32 block_space, start_delay;
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u32 tcon_div;
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tcon->dclk_min_div = 4;
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tcon->dclk_max_div = 127;
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tcon->dclk_min_div = SUN6I_DSI_TCON_DIV;
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tcon->dclk_max_div = SUN6I_DSI_TCON_DIV;
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sun4i_tcon0_mode_set_common(tcon, mode);
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@ -13,6 +13,8 @@
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#include <drm/drm_encoder.h>
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#include <drm/drm_mipi_dsi.h>
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#define SUN6I_DSI_TCON_DIV 4
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struct sun6i_dsi {
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struct drm_connector connector;
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struct drm_encoder encoder;
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