Pin control fixes for v4.11, take two:
- Kconfig fixup for the TI IOdelay pinctrl-single add-on. - Fix up a typo in the meson i2c ao groups. - Switch a remapping back to use devm_ioremap() as devm_ioremap_resource() does not allow for sharing memory regions. - Do not clear the Qualcomm irq status bit in irq_unmask(), as this can lead to missing interrupts while the irq handler is executing. - Add irq_request/release_resources() on the ST driver. - Add a bunch of mysteriously missing pingroups for high numbered pins in the Qualcomm ipq4019 driver. -----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJY2MAtAAoJEEEQszewGV1zjGEQAJjwAQ0Guht7s5WJdrw4330z Cy1ln5PSXQrIj8ZNrNdgJy/CfwFYG/2x7DEG393wIeiEhXscV+LqHUrfe0M9rN7z zgqA+nlAwzcsWp8tvASmCjYXIjIEGjAh4qBsJbW7kWMToct3+UfBAnmL+T88P36z 30MJ9eFPaS5J5660wkqgPu3hjUuPebReVFkyrH4xd2ky6CIuLxal0h0tQCBFEK8j 9jN6LO41ScririvrB+Z0wpDVz74DCxqlspOmHSnHYEXwoMfhG/Zp1WMo94YOIXg2 /Ob8xSeN5YhyGszYjXXnMhHR9tiI2rlXcoJA63CTZsJ83V91v7QJpqDNPFmS1t11 +RFd4B49Q5th7/fNMtqFK+Y9zlSUpinkigAvCAImic42X9kYgV4kNmlW6TX/Um22 5e0KbvS4U1YeCxY4y8fbJ9eHv+Yjv5K7c/4wFEhHq1KfFZ/yyFcqzXcCIKKZ74+u DaU+rSPkSNWrsAunfNg1EnrExWOzl5YXzl6SUb/fSYdXY0BNm6jsAzsiSOkqs7VV aQgGAN5VJ88Ho5cn14qAZw9IlpPKAzf9twna//CgJLUBD/TEs4SiPeBq9vwdjB5a 3m0smorY+jXnziLe5GCdiZRvvJAgeKV9wB7i87BugCsQbB4W98MO0aJg24X1z+zK nsf+0ff7+UCSOHjx9Lxw =0sa2 -----END PGP SIGNATURE----- Merge tag 'pinctrl-v4.11-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull more pin control fixes from Linus Walleij: "Here is a bunch of pin control fixes again A bit more than I'd like for this subsystem at this point, but what can I do. They are all driver fixes for hardware issues, as like "we forgot", "we didn't think of the fact that this could happen", "oops that one goes there" etc - Kconfig fixup for the TI IOdelay pinctrl-single add-on - fix up a typo in the meson i2c ao groups - switch a remapping back to use devm_ioremap() as devm_ioremap_resource() does not allow for sharing memory regions - do not clear the Qualcomm irq status bit in irq_unmask(), as this can lead to missing interrupts while the irq handler is executing - add irq_request/release_resources() on the ST driver - add a bunch of mysteriously missing pingroups for high numbered pins in the Qualcomm ipq4019 driver" * tag 'pinctrl-v4.11-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: pinctrl: qcom: ipq4019: add missing pingroups for pins > 70 pinctrl: st: add irq_request/release_resources callbacks pinctrl: qcom: Don't clear status bit on irq_unmask pinctrl: samsung: Fix memory mapping code pinctrl: meson-gxbb: Fix typo in i2c ao groups pinctrl: ti: The IODelay driver is a DRA7xxx feature so depend on that SoC
This commit is contained in:
commit
85f91d5c51
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@ -667,11 +667,11 @@ static const char * const uart_ao_b_groups[] = {
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};
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static const char * const i2c_ao_groups[] = {
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"i2c_sdk_ao", "i2c_sda_ao",
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"i2c_sck_ao", "i2c_sda_ao",
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};
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static const char * const i2c_slave_ao_groups[] = {
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"i2c_slave_sdk_ao", "i2c_slave_sda_ao",
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"i2c_slave_sck_ao", "i2c_slave_sda_ao",
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};
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static const char * const remote_input_ao_groups[] = {
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@ -1285,6 +1285,22 @@ static void st_gpio_irq_unmask(struct irq_data *d)
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writel(BIT(d->hwirq), bank->base + REG_PIO_SET_PMASK);
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}
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static int st_gpio_irq_request_resources(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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st_gpio_direction_input(gc, d->hwirq);
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return gpiochip_lock_as_irq(gc, d->hwirq);
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}
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static void st_gpio_irq_release_resources(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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gpiochip_unlock_as_irq(gc, d->hwirq);
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}
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static int st_gpio_irq_set_type(struct irq_data *d, unsigned type)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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@ -1438,12 +1454,14 @@ static struct gpio_chip st_gpio_template = {
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};
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static struct irq_chip st_gpio_irqchip = {
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.name = "GPIO",
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.irq_disable = st_gpio_irq_mask,
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.irq_mask = st_gpio_irq_mask,
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.irq_unmask = st_gpio_irq_unmask,
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.irq_set_type = st_gpio_irq_set_type,
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.flags = IRQCHIP_SKIP_SET_WAKE,
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.name = "GPIO",
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.irq_request_resources = st_gpio_irq_request_resources,
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.irq_release_resources = st_gpio_irq_release_resources,
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.irq_disable = st_gpio_irq_mask,
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.irq_mask = st_gpio_irq_mask,
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.irq_unmask = st_gpio_irq_unmask,
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.irq_set_type = st_gpio_irq_set_type,
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.flags = IRQCHIP_SKIP_SET_WAKE,
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};
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static int st_gpiolib_register_bank(struct st_pinctrl *info,
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@ -405,6 +405,36 @@ static const struct msm_pingroup ipq4019_groups[] = {
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PINGROUP(67, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(68, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(69, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(70, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(71, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(72, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(73, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(74, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(75, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(76, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(77, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(78, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(79, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(80, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(81, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(82, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(83, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(84, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(85, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(86, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(87, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(88, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(89, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(90, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(91, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(92, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(93, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(94, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(95, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(96, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(97, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(98, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(99, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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};
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static const struct msm_pinctrl_soc_data ipq4019_pinctrl = {
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@ -609,10 +609,6 @@ static void msm_gpio_irq_unmask(struct irq_data *d)
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raw_spin_lock_irqsave(&pctrl->lock, flags);
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val = readl(pctrl->regs + g->intr_status_reg);
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val &= ~BIT(g->intr_status_bit);
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writel(val, pctrl->regs + g->intr_status_reg);
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val = readl(pctrl->regs + g->intr_cfg_reg);
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val |= BIT(g->intr_enable_bit);
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writel(val, pctrl->regs + g->intr_cfg_reg);
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@ -988,9 +988,16 @@ samsung_pinctrl_get_soc_data(struct samsung_pinctrl_drv_data *d,
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for (i = 0; i < ctrl->nr_ext_resources + 1; i++) {
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res = platform_get_resource(pdev, IORESOURCE_MEM, i);
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virt_base[i] = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(virt_base[i]))
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return ERR_CAST(virt_base[i]);
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if (!res) {
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dev_err(&pdev->dev, "failed to get mem%d resource\n", i);
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return ERR_PTR(-EINVAL);
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}
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virt_base[i] = devm_ioremap(&pdev->dev, res->start,
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resource_size(res));
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if (!virt_base[i]) {
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dev_err(&pdev->dev, "failed to ioremap %pR\n", res);
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return ERR_PTR(-EIO);
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}
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}
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bank = d->pin_banks;
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@ -1,6 +1,6 @@
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config PINCTRL_TI_IODELAY
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tristate "TI IODelay Module pinconf driver"
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depends on OF
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depends on OF && (SOC_DRA7XX || COMPILE_TEST)
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select GENERIC_PINCTRL_GROUPS
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select GENERIC_PINMUX_FUNCTIONS
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select GENERIC_PINCONF
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