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staging: sm750fb: share common bits in display control registers 

The display control registers for primary and secondary display share some
of the bits and those bits can be defined in a single place and then used
for manipulations of the relevant registers.

Signed-off-by: Mike Rapoport <mike.rapoport@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Mike Rapoport 2016-02-10 18:34:04 +02:00 committed by Greg Kroah-Hartman
parent 7755265a99
commit 85e4db5347
4 changed files with 58 additions and 87 deletions
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6
drivers/staging/sm750fb/ddk750_chip.c
View File

@ -249,17 +249,17 @@ int ddk750_initHw(initchip_param_t *pInitParam)
/* Disable Overlay, if a former application left it on */ /* Disable Overlay, if a former application left it on */
reg = PEEK32(VIDEO_DISPLAY_CTRL); reg = PEEK32(VIDEO_DISPLAY_CTRL);
reg = FIELD_SET(reg, VIDEO_DISPLAY_CTRL, PLANE, DISABLE); reg = FIELD_SET(reg, DISPLAY_CTRL, PLANE, DISABLE);
POKE32(VIDEO_DISPLAY_CTRL, reg); POKE32(VIDEO_DISPLAY_CTRL, reg);
/* Disable video alpha, if a former application left it on */ /* Disable video alpha, if a former application left it on */
reg = PEEK32(VIDEO_ALPHA_DISPLAY_CTRL); reg = PEEK32(VIDEO_ALPHA_DISPLAY_CTRL);
reg = FIELD_SET(reg, VIDEO_ALPHA_DISPLAY_CTRL, PLANE, DISABLE); reg = FIELD_SET(reg, DISPLAY_CTRL, PLANE, DISABLE);
POKE32(VIDEO_ALPHA_DISPLAY_CTRL, reg); POKE32(VIDEO_ALPHA_DISPLAY_CTRL, reg);
/* Disable alpha plane, if a former application left it on */ /* Disable alpha plane, if a former application left it on */
reg = PEEK32(ALPHA_DISPLAY_CTRL); reg = PEEK32(ALPHA_DISPLAY_CTRL);
reg = FIELD_SET(reg, ALPHA_DISPLAY_CTRL, PLANE, DISABLE); reg = FIELD_SET(reg, DISPLAY_CTRL, PLANE, DISABLE);
POKE32(ALPHA_DISPLAY_CTRL, reg); POKE32(ALPHA_DISPLAY_CTRL, reg);
/* Disable DMA Channel, if a former application left it on */ /* Disable DMA Channel, if a former application left it on */

34
drivers/staging/sm750fb/ddk750_display.c
View File

@ -23,12 +23,10 @@ static void setDisplayControl(int ctrl, int disp_state)
* because changing at the same time does not guarantee that * because changing at the same time does not guarantee that
* the plane will also enabled or disabled. * the plane will also enabled or disabled.
*/ */
reg = FIELD_SET(reg, reg = FIELD_SET(reg, DISPLAY_CTRL, TIMING, ENABLE);
PANEL_DISPLAY_CTRL, TIMING, ENABLE);
POKE32(PANEL_DISPLAY_CTRL, reg); POKE32(PANEL_DISPLAY_CTRL, reg);
reg = FIELD_SET(reg, reg = FIELD_SET(reg, DISPLAY_CTRL, PLANE, ENABLE);
PANEL_DISPLAY_CTRL, PLANE, ENABLE);
/* Added some masks to mask out the reserved bits. /* Added some masks to mask out the reserved bits.
* Sometimes, the reserved bits are set/reset randomly when * Sometimes, the reserved bits are set/reset randomly when
@ -57,12 +55,10 @@ static void setDisplayControl(int ctrl, int disp_state)
* next vertical sync. Need to find out if it is necessary to * next vertical sync. Need to find out if it is necessary to
* wait for 1 vsync before modifying the timing enable bit. * wait for 1 vsync before modifying the timing enable bit.
* */ * */
reg = FIELD_SET(reg, reg = FIELD_SET(reg, DISPLAY_CTRL, PLANE, DISABLE);
PANEL_DISPLAY_CTRL, PLANE, DISABLE);
POKE32(PANEL_DISPLAY_CTRL, reg); POKE32(PANEL_DISPLAY_CTRL, reg);
reg = FIELD_SET(reg, reg = FIELD_SET(reg, DISPLAY_CTRL, TIMING, DISABLE);
PANEL_DISPLAY_CTRL, TIMING, DISABLE);
POKE32(PANEL_DISPLAY_CTRL, reg); POKE32(PANEL_DISPLAY_CTRL, reg);
} }
@ -74,12 +70,10 @@ static void setDisplayControl(int ctrl, int disp_state)
/* Timing should be enabled first before enabling the plane because changing at the /* Timing should be enabled first before enabling the plane because changing at the
same time does not guarantee that the plane will also enabled or disabled. same time does not guarantee that the plane will also enabled or disabled.
*/ */
reg = FIELD_SET(reg, reg = FIELD_SET(reg, DISPLAY_CTRL, TIMING, ENABLE);
CRT_DISPLAY_CTRL, TIMING, ENABLE);
POKE32(CRT_DISPLAY_CTRL, reg); POKE32(CRT_DISPLAY_CTRL, reg);
reg = FIELD_SET(reg, reg = FIELD_SET(reg, DISPLAY_CTRL, PLANE, ENABLE);
CRT_DISPLAY_CTRL, PLANE, ENABLE);
/* Added some masks to mask out the reserved bits. /* Added some masks to mask out the reserved bits.
* Sometimes, the reserved bits are set/reset randomly when * Sometimes, the reserved bits are set/reset randomly when
@ -106,12 +100,10 @@ static void setDisplayControl(int ctrl, int disp_state)
* vertical sync. Need to find out if it is necessary to * vertical sync. Need to find out if it is necessary to
* wait for 1 vsync before modifying the timing enable bit. * wait for 1 vsync before modifying the timing enable bit.
*/ */
reg = FIELD_SET(reg, reg = FIELD_SET(reg, DISPLAY_CTRL, PLANE, DISABLE);
CRT_DISPLAY_CTRL, PLANE, DISABLE);
POKE32(CRT_DISPLAY_CTRL, reg); POKE32(CRT_DISPLAY_CTRL, reg);
reg = FIELD_SET(reg, reg = FIELD_SET(reg, DISPLAY_CTRL, TIMING, DISABLE);
CRT_DISPLAY_CTRL, TIMING, DISABLE);
POKE32(CRT_DISPLAY_CTRL, reg); POKE32(CRT_DISPLAY_CTRL, reg);
} }
} }
@ -127,8 +119,9 @@ static void waitNextVerticalSync(int ctrl, int delay)
/* Do not wait when the Primary PLL is off or display control is already off. /* Do not wait when the Primary PLL is off or display control is already off.
This will prevent the software to wait forever. */ This will prevent the software to wait forever. */
if (!(PEEK32(PANEL_PLL_CTRL) & PLL_CTRL_POWER) || if (!(PEEK32(PANEL_PLL_CTRL) & PLL_CTRL_POWER) ||
(FIELD_GET(PEEK32(PANEL_DISPLAY_CTRL), PANEL_DISPLAY_CTRL, TIMING) == (FIELD_GET(PEEK32(PANEL_DISPLAY_CTRL),
PANEL_DISPLAY_CTRL_TIMING_DISABLE)) { DISPLAY_CTRL, TIMING) ==
DISPLAY_CTRL_TIMING_DISABLE)) {
return; return;
} }
@ -149,8 +142,9 @@ static void waitNextVerticalSync(int ctrl, int delay)
/* Do not wait when the Primary PLL is off or display control is already off. /* Do not wait when the Primary PLL is off or display control is already off.
This will prevent the software to wait forever. */ This will prevent the software to wait forever. */
if (!(PEEK32(CRT_PLL_CTRL) & PLL_CTRL_POWER) || if (!(PEEK32(CRT_PLL_CTRL) & PLL_CTRL_POWER) ||
(FIELD_GET(PEEK32(CRT_DISPLAY_CTRL), CRT_DISPLAY_CTRL, TIMING) == (FIELD_GET(PEEK32(CRT_DISPLAY_CTRL),
CRT_DISPLAY_CTRL_TIMING_DISABLE)) { DISPLAY_CTRL, TIMING) ==
DISPLAY_CTRL_TIMING_DISABLE)) {
return; return;
} }

42
drivers/staging/sm750fb/ddk750_mode.c
View File

@ -65,7 +65,8 @@ static unsigned long displayControlAdjust_SM750LE(mode_parameter_t *pModeParam,
dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, RGBBIT, 24BIT); dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, RGBBIT, 24BIT);
/* Set bit 14 of display controller */ /* Set bit 14 of display controller */
dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLOCK_PHASE, ACTIVE_LOW); dispControl = FIELD_SET(dispControl, DISPLAY_CTRL, CLOCK_PHASE,
ACTIVE_LOW);
POKE32(CRT_DISPLAY_CTRL, dispControl); POKE32(CRT_DISPLAY_CTRL, dispControl);
@ -101,21 +102,22 @@ static int programModeRegisters(mode_parameter_t *pModeParam, pll_value_t *pll)
| FIELD_VALUE(0, CRT_VERTICAL_SYNC, START, pModeParam->vertical_sync_start - 1)); | FIELD_VALUE(0, CRT_VERTICAL_SYNC, START, pModeParam->vertical_sync_start - 1));
tmp = FIELD_VALUE(0, CRT_DISPLAY_CTRL, VSYNC_PHASE, tmp = FIELD_VALUE(0, DISPLAY_CTRL, VSYNC_PHASE,
pModeParam->vertical_sync_polarity) | pModeParam->vertical_sync_polarity) |
FIELD_VALUE(0, CRT_DISPLAY_CTRL, HSYNC_PHASE, pModeParam->horizontal_sync_polarity) | FIELD_VALUE(0, DISPLAY_CTRL, HSYNC_PHASE,
FIELD_SET(0, CRT_DISPLAY_CTRL, TIMING, ENABLE) | pModeParam->horizontal_sync_polarity) |
FIELD_SET(0, CRT_DISPLAY_CTRL, PLANE, ENABLE); FIELD_SET(0, DISPLAY_CTRL, TIMING, ENABLE) |
FIELD_SET(0, DISPLAY_CTRL, PLANE, ENABLE);
if (getChipType() == SM750LE) { if (getChipType() == SM750LE) {
displayControlAdjust_SM750LE(pModeParam, tmp); displayControlAdjust_SM750LE(pModeParam, tmp);
} else { } else {
reg = PEEK32(CRT_DISPLAY_CTRL) reg = PEEK32(CRT_DISPLAY_CTRL)
& FIELD_CLEAR(CRT_DISPLAY_CTRL, VSYNC_PHASE) & FIELD_CLEAR(DISPLAY_CTRL, VSYNC_PHASE)
& FIELD_CLEAR(CRT_DISPLAY_CTRL, HSYNC_PHASE) & FIELD_CLEAR(DISPLAY_CTRL, HSYNC_PHASE)
& FIELD_CLEAR(CRT_DISPLAY_CTRL, TIMING) & FIELD_CLEAR(DISPLAY_CTRL, TIMING)
& FIELD_CLEAR(CRT_DISPLAY_CTRL, PLANE); & FIELD_CLEAR(DISPLAY_CTRL, PLANE);
POKE32(CRT_DISPLAY_CTRL, tmp | reg); POKE32(CRT_DISPLAY_CTRL, tmp | reg);
} }
@ -141,12 +143,14 @@ static int programModeRegisters(mode_parameter_t *pModeParam, pll_value_t *pll)
FIELD_VALUE(0, PANEL_VERTICAL_SYNC, HEIGHT, pModeParam->vertical_sync_height) FIELD_VALUE(0, PANEL_VERTICAL_SYNC, HEIGHT, pModeParam->vertical_sync_height)
| FIELD_VALUE(0, PANEL_VERTICAL_SYNC, START, pModeParam->vertical_sync_start - 1)); | FIELD_VALUE(0, PANEL_VERTICAL_SYNC, START, pModeParam->vertical_sync_start - 1));
tmp = FIELD_VALUE(0, PANEL_DISPLAY_CTRL, VSYNC_PHASE, tmp = FIELD_VALUE(0, DISPLAY_CTRL, VSYNC_PHASE,
pModeParam->vertical_sync_polarity) | pModeParam->vertical_sync_polarity) |
FIELD_VALUE(0, PANEL_DISPLAY_CTRL, HSYNC_PHASE, pModeParam->horizontal_sync_polarity) | FIELD_VALUE(0, DISPLAY_CTRL, HSYNC_PHASE,
FIELD_VALUE(0, PANEL_DISPLAY_CTRL, CLOCK_PHASE, pModeParam->clock_phase_polarity) | pModeParam->horizontal_sync_polarity) |
FIELD_SET(0, PANEL_DISPLAY_CTRL, TIMING, ENABLE) | FIELD_VALUE(0, DISPLAY_CTRL, CLOCK_PHASE,
FIELD_SET(0, PANEL_DISPLAY_CTRL, PLANE, ENABLE); pModeParam->clock_phase_polarity) |
FIELD_SET(0, DISPLAY_CTRL, TIMING, ENABLE) |
FIELD_SET(0, DISPLAY_CTRL, PLANE, ENABLE);
reserved = FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_1_MASK, reserved = FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_1_MASK,
ENABLE) | ENABLE) |
@ -155,11 +159,11 @@ static int programModeRegisters(mode_parameter_t *pModeParam, pll_value_t *pll)
FIELD_SET(0, PANEL_DISPLAY_CTRL, VSYNC, ACTIVE_LOW); FIELD_SET(0, PANEL_DISPLAY_CTRL, VSYNC, ACTIVE_LOW);
reg = (PEEK32(PANEL_DISPLAY_CTRL) & ~reserved) reg = (PEEK32(PANEL_DISPLAY_CTRL) & ~reserved)
& FIELD_CLEAR(PANEL_DISPLAY_CTRL, CLOCK_PHASE) & FIELD_CLEAR(DISPLAY_CTRL, CLOCK_PHASE)
& FIELD_CLEAR(PANEL_DISPLAY_CTRL, VSYNC_PHASE) & FIELD_CLEAR(DISPLAY_CTRL, VSYNC_PHASE)
& FIELD_CLEAR(PANEL_DISPLAY_CTRL, HSYNC_PHASE) & FIELD_CLEAR(DISPLAY_CTRL, HSYNC_PHASE)
& FIELD_CLEAR(PANEL_DISPLAY_CTRL, TIMING) & FIELD_CLEAR(DISPLAY_CTRL, TIMING)
& FIELD_CLEAR(PANEL_DISPLAY_CTRL, PLANE); & FIELD_CLEAR(DISPLAY_CTRL, PLANE);
/* May a hardware bug or just my test chip (not confirmed). /* May a hardware bug or just my test chip (not confirmed).

63
drivers/staging/sm750fb/ddk750_reg.h
View File

@ -825,15 +825,15 @@
#define PANEL_DISPLAY_CTRL_RESERVED_3_MASK 15:15 #define PANEL_DISPLAY_CTRL_RESERVED_3_MASK 15:15
#define PANEL_DISPLAY_CTRL_RESERVED_3_MASK_DISABLE 0 #define PANEL_DISPLAY_CTRL_RESERVED_3_MASK_DISABLE 0
#define PANEL_DISPLAY_CTRL_RESERVED_3_MASK_ENABLE 1 #define PANEL_DISPLAY_CTRL_RESERVED_3_MASK_ENABLE 1
#define PANEL_DISPLAY_CTRL_CLOCK_PHASE 14:14 #define DISPLAY_CTRL_CLOCK_PHASE 14:14
#define PANEL_DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_HIGH 0 #define DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_HIGH 0
#define PANEL_DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_LOW 1 #define DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_LOW 1
#define PANEL_DISPLAY_CTRL_VSYNC_PHASE 13:13 #define DISPLAY_CTRL_VSYNC_PHASE 13:13
#define PANEL_DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_HIGH 0 #define DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_HIGH 0
#define PANEL_DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_LOW 1 #define DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_LOW 1
#define PANEL_DISPLAY_CTRL_HSYNC_PHASE 12:12 #define DISPLAY_CTRL_HSYNC_PHASE 12:12
#define PANEL_DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_HIGH 0 #define DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_HIGH 0
#define PANEL_DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_LOW 1 #define DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_LOW 1
#define PANEL_DISPLAY_CTRL_VSYNC 11:11 #define PANEL_DISPLAY_CTRL_VSYNC 11:11
#define PANEL_DISPLAY_CTRL_VSYNC_ACTIVE_HIGH 0 #define PANEL_DISPLAY_CTRL_VSYNC_ACTIVE_HIGH 0
#define PANEL_DISPLAY_CTRL_VSYNC_ACTIVE_LOW 1 #define PANEL_DISPLAY_CTRL_VSYNC_ACTIVE_LOW 1
@ -843,9 +843,9 @@
#define PANEL_DISPLAY_CTRL_COLOR_KEY 9:9 #define PANEL_DISPLAY_CTRL_COLOR_KEY 9:9
#define PANEL_DISPLAY_CTRL_COLOR_KEY_DISABLE 0 #define PANEL_DISPLAY_CTRL_COLOR_KEY_DISABLE 0
#define PANEL_DISPLAY_CTRL_COLOR_KEY_ENABLE 1 #define PANEL_DISPLAY_CTRL_COLOR_KEY_ENABLE 1
#define PANEL_DISPLAY_CTRL_TIMING 8:8 #define DISPLAY_CTRL_TIMING 8:8
#define PANEL_DISPLAY_CTRL_TIMING_DISABLE 0 #define DISPLAY_CTRL_TIMING_DISABLE 0
#define PANEL_DISPLAY_CTRL_TIMING_ENABLE 1 #define DISPLAY_CTRL_TIMING_ENABLE 1
#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR 7:7 #define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR 7:7
#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR_DOWN 0 #define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR_DOWN 0
#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR_UP 1 #define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR_UP 1
@ -858,12 +858,12 @@
#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN 4:4 #define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN 4:4
#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DISABLE 0 #define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DISABLE 0
#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_ENABLE 1 #define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_ENABLE 1
#define PANEL_DISPLAY_CTRL_GAMMA 3:3 #define DISPLAY_CTRL_GAMMA 3:3
#define PANEL_DISPLAY_CTRL_GAMMA_DISABLE 0 #define DISPLAY_CTRL_GAMMA_DISABLE 0
#define PANEL_DISPLAY_CTRL_GAMMA_ENABLE 1 #define DISPLAY_CTRL_GAMMA_ENABLE 1
#define PANEL_DISPLAY_CTRL_PLANE 2:2 #define DISPLAY_CTRL_PLANE 2:2
#define PANEL_DISPLAY_CTRL_PLANE_DISABLE 0 #define DISPLAY_CTRL_PLANE_DISABLE 0
#define PANEL_DISPLAY_CTRL_PLANE_ENABLE 1 #define DISPLAY_CTRL_PLANE_ENABLE 1
#define PANEL_DISPLAY_CTRL_FORMAT 1:0 #define PANEL_DISPLAY_CTRL_FORMAT 1:0
#define PANEL_DISPLAY_CTRL_FORMAT_8 0 #define PANEL_DISPLAY_CTRL_FORMAT_8 0
#define PANEL_DISPLAY_CTRL_FORMAT_16 1 #define PANEL_DISPLAY_CTRL_FORMAT_16 1
@ -966,9 +966,6 @@
#define VIDEO_DISPLAY_CTRL_GAMMA 3:3 #define VIDEO_DISPLAY_CTRL_GAMMA 3:3
#define VIDEO_DISPLAY_CTRL_GAMMA_DISABLE 0 #define VIDEO_DISPLAY_CTRL_GAMMA_DISABLE 0
#define VIDEO_DISPLAY_CTRL_GAMMA_ENABLE 1 #define VIDEO_DISPLAY_CTRL_GAMMA_ENABLE 1
#define VIDEO_DISPLAY_CTRL_PLANE 2:2
#define VIDEO_DISPLAY_CTRL_PLANE_DISABLE 0
#define VIDEO_DISPLAY_CTRL_PLANE_ENABLE 1
#define VIDEO_DISPLAY_CTRL_FORMAT 1:0 #define VIDEO_DISPLAY_CTRL_FORMAT 1:0
#define VIDEO_DISPLAY_CTRL_FORMAT_8 0 #define VIDEO_DISPLAY_CTRL_FORMAT_8 0
#define VIDEO_DISPLAY_CTRL_FORMAT_16 1 #define VIDEO_DISPLAY_CTRL_FORMAT_16 1
@ -1065,9 +1062,6 @@
#define VIDEO_ALPHA_DISPLAY_CTRL_CHROMA_KEY 3:3 #define VIDEO_ALPHA_DISPLAY_CTRL_CHROMA_KEY 3:3
#define VIDEO_ALPHA_DISPLAY_CTRL_CHROMA_KEY_DISABLE 0 #define VIDEO_ALPHA_DISPLAY_CTRL_CHROMA_KEY_DISABLE 0
#define VIDEO_ALPHA_DISPLAY_CTRL_CHROMA_KEY_ENABLE 1 #define VIDEO_ALPHA_DISPLAY_CTRL_CHROMA_KEY_ENABLE 1
#define VIDEO_ALPHA_DISPLAY_CTRL_PLANE 2:2
#define VIDEO_ALPHA_DISPLAY_CTRL_PLANE_DISABLE 0
#define VIDEO_ALPHA_DISPLAY_CTRL_PLANE_ENABLE 1
#define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT 1:0 #define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT 1:0
#define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_8 0 #define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_8 0
#define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_16 1 #define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_16 1
@ -1258,9 +1252,6 @@
#define ALPHA_DISPLAY_CTRL_CHROMA_KEY 3:3 #define ALPHA_DISPLAY_CTRL_CHROMA_KEY 3:3
#define ALPHA_DISPLAY_CTRL_CHROMA_KEY_DISABLE 0 #define ALPHA_DISPLAY_CTRL_CHROMA_KEY_DISABLE 0
#define ALPHA_DISPLAY_CTRL_CHROMA_KEY_ENABLE 1 #define ALPHA_DISPLAY_CTRL_CHROMA_KEY_ENABLE 1
#define ALPHA_DISPLAY_CTRL_PLANE 2:2
#define ALPHA_DISPLAY_CTRL_PLANE_DISABLE 0
#define ALPHA_DISPLAY_CTRL_PLANE_ENABLE 1
#define ALPHA_DISPLAY_CTRL_FORMAT 1:0 #define ALPHA_DISPLAY_CTRL_FORMAT 1:0
#define ALPHA_DISPLAY_CTRL_FORMAT_16 1 #define ALPHA_DISPLAY_CTRL_FORMAT_16 1
#define ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4 2 #define ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4 2
@ -1448,28 +1439,10 @@
#define CRT_DISPLAY_CTRL_FIFO_3 1 #define CRT_DISPLAY_CTRL_FIFO_3 1
#define CRT_DISPLAY_CTRL_FIFO_7 2 #define CRT_DISPLAY_CTRL_FIFO_7 2
#define CRT_DISPLAY_CTRL_FIFO_11 3 #define CRT_DISPLAY_CTRL_FIFO_11 3
#define CRT_DISPLAY_CTRL_CLOCK_PHASE 14:14
#define CRT_DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_HIGH 0
#define CRT_DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_LOW 1
#define CRT_DISPLAY_CTRL_VSYNC_PHASE 13:13
#define CRT_DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_HIGH 0
#define CRT_DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_LOW 1
#define CRT_DISPLAY_CTRL_HSYNC_PHASE 12:12
#define CRT_DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_HIGH 0
#define CRT_DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_LOW 1
#define CRT_DISPLAY_CTRL_BLANK 10:10 #define CRT_DISPLAY_CTRL_BLANK 10:10
#define CRT_DISPLAY_CTRL_BLANK_OFF 0 #define CRT_DISPLAY_CTRL_BLANK_OFF 0
#define CRT_DISPLAY_CTRL_BLANK_ON 1 #define CRT_DISPLAY_CTRL_BLANK_ON 1
#define CRT_DISPLAY_CTRL_TIMING 8:8
#define CRT_DISPLAY_CTRL_TIMING_DISABLE 0
#define CRT_DISPLAY_CTRL_TIMING_ENABLE 1
#define CRT_DISPLAY_CTRL_PIXEL 7:4 #define CRT_DISPLAY_CTRL_PIXEL 7:4
#define CRT_DISPLAY_CTRL_GAMMA 3:3
#define CRT_DISPLAY_CTRL_GAMMA_DISABLE 0
#define CRT_DISPLAY_CTRL_GAMMA_ENABLE 1
#define CRT_DISPLAY_CTRL_PLANE 2:2
#define CRT_DISPLAY_CTRL_PLANE_DISABLE 0
#define CRT_DISPLAY_CTRL_PLANE_ENABLE 1
#define CRT_DISPLAY_CTRL_FORMAT 1:0 #define CRT_DISPLAY_CTRL_FORMAT 1:0
#define CRT_DISPLAY_CTRL_FORMAT_8 0 #define CRT_DISPLAY_CTRL_FORMAT_8 0
#define CRT_DISPLAY_CTRL_FORMAT_16 1 #define CRT_DISPLAY_CTRL_FORMAT_16 1