pinctrl: renesas: r8a779g0: Add missing TPU0TOx_A
This patch adds missing TPU0TOx_A. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87r135sj9j.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Kuninori Morimoto
Geert Uytterhoeven
parent
c2b4b2cd63
commit
85a9cbe4c5
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@ -326,15 +326,15 @@
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/* IP3SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
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#define IP3SR1_3_0 FM(HRX3) FM(SCK3_A) FM(MSIOF4_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP3SR1_7_4 FM(HSCK3) FM(CTS3_N_A) FM(MSIOF4_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP3SR1_11_8 FM(HRTS3_N) FM(RTS3_N_A) FM(MSIOF4_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP3SR1_7_4 FM(HSCK3) FM(CTS3_N_A) FM(MSIOF4_SCK) FM(TPU0TO0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP3SR1_11_8 FM(HRTS3_N) FM(RTS3_N_A) FM(MSIOF4_TXD) FM(TPU0TO1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP3SR1_15_12 FM(HCTS3_N) FM(RX3_A) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP3SR1_19_16 FM(HTX3) FM(TX3_A) FM(MSIOF4_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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/* SR2 */
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/* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
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#define IP0SR2_3_0 FM(FXR_TXDA) FM(CANFD1_TX) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP0SR2_7_4 FM(FXR_TXENA_N) FM(CANFD1_RX) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP0SR2_3_0 FM(FXR_TXDA) FM(CANFD1_TX) FM(TPU0TO2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP0SR2_7_4 FM(FXR_TXENA_N) FM(CANFD1_RX) FM(TPU0TO3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP0SR2_11_8 FM(RXDA_EXTFXR) FM(CANFD5_TX) FM(IRQ5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP0SR2_15_12 FM(CLK_EXTFXR) FM(CANFD5_RX) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP0SR2_19_16 FM(RXDB_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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@ -889,10 +889,12 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_GPSR(IP3SR1_7_4, HSCK3),
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PINMUX_IPSR_GPSR(IP3SR1_7_4, CTS3_N_A),
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PINMUX_IPSR_GPSR(IP3SR1_7_4, MSIOF4_SCK),
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PINMUX_IPSR_GPSR(IP3SR1_7_4, TPU0TO0_A),
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PINMUX_IPSR_GPSR(IP3SR1_11_8, HRTS3_N),
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PINMUX_IPSR_GPSR(IP3SR1_11_8, RTS3_N_A),
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PINMUX_IPSR_GPSR(IP3SR1_11_8, MSIOF4_TXD),
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PINMUX_IPSR_GPSR(IP3SR1_11_8, TPU0TO1_A),
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PINMUX_IPSR_GPSR(IP3SR1_15_12, HCTS3_N),
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PINMUX_IPSR_GPSR(IP3SR1_15_12, RX3_A),
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@ -905,9 +907,11 @@ static const u16 pinmux_data[] = {
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/* IP0SR2 */
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PINMUX_IPSR_GPSR(IP0SR2_3_0, FXR_TXDA),
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PINMUX_IPSR_GPSR(IP0SR2_3_0, CANFD1_TX),
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PINMUX_IPSR_GPSR(IP0SR2_3_0, TPU0TO2_A),
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PINMUX_IPSR_GPSR(IP0SR2_7_4, FXR_TXENA_N),
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PINMUX_IPSR_GPSR(IP0SR2_7_4, CANFD1_RX),
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PINMUX_IPSR_GPSR(IP0SR2_7_4, TPU0TO3_A),
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PINMUX_IPSR_GPSR(IP0SR2_11_8, RXDA_EXTFXR),
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PINMUX_IPSR_GPSR(IP0SR2_11_8, CANFD5_TX),
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@ -2327,6 +2331,36 @@ static const unsigned int tpu_to3_mux[] = {
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TPU0TO3_MARK,
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};
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/* - TPU_A ------------------------------------------------------------------- */
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static const unsigned int tpu_to0_a_pins[] = {
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/* TPU0TO0_A */
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RCAR_GP_PIN(1, 25),
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};
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static const unsigned int tpu_to0_a_mux[] = {
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TPU0TO0_A_MARK,
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};
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static const unsigned int tpu_to1_a_pins[] = {
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/* TPU0TO1_A */
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RCAR_GP_PIN(1, 26),
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};
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static const unsigned int tpu_to1_a_mux[] = {
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TPU0TO1_A_MARK,
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};
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static const unsigned int tpu_to2_a_pins[] = {
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/* TPU0TO2_A */
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RCAR_GP_PIN(2, 0),
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};
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static const unsigned int tpu_to2_a_mux[] = {
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TPU0TO2_A_MARK,
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};
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static const unsigned int tpu_to3_a_pins[] = {
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/* TPU0TO3_A */
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RCAR_GP_PIN(2, 1),
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};
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static const unsigned int tpu_to3_a_mux[] = {
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TPU0TO3_A_MARK,
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};
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/* - TSN0 ------------------------------------------------ */
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static const unsigned int tsn0_link_pins[] = {
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/* TSN0_LINK */
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@ -2557,10 +2591,14 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
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SH_PFC_PIN_GROUP(scif4_ctrl),
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SH_PFC_PIN_GROUP(scif_clk),
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SH_PFC_PIN_GROUP(tpu_to0),
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SH_PFC_PIN_GROUP(tpu_to1),
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SH_PFC_PIN_GROUP(tpu_to2),
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SH_PFC_PIN_GROUP(tpu_to3),
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SH_PFC_PIN_GROUP(tpu_to0), /* suffix might be updated */
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SH_PFC_PIN_GROUP(tpu_to0_a), /* suffix might be updated */
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SH_PFC_PIN_GROUP(tpu_to1), /* suffix might be updated */
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SH_PFC_PIN_GROUP(tpu_to1_a), /* suffix might be updated */
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SH_PFC_PIN_GROUP(tpu_to2), /* suffix might be updated */
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SH_PFC_PIN_GROUP(tpu_to2_a), /* suffix might be updated */
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SH_PFC_PIN_GROUP(tpu_to3), /* suffix might be updated */
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SH_PFC_PIN_GROUP(tpu_to3_a), /* suffix might be updated */
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SH_PFC_PIN_GROUP(tsn0_link),
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SH_PFC_PIN_GROUP(tsn0_phy_int),
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@ -2860,10 +2898,15 @@ static const char * const scif_clk_groups[] = {
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};
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static const char * const tpu_groups[] = {
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/* suffix might be updated */
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"tpu_to0",
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"tpu_to0_a",
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"tpu_to1",
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"tpu_to1_a",
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"tpu_to2",
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"tpu_to2_a",
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"tpu_to3",
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"tpu_to3_a",
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};
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static const char * const tsn0_groups[] = {
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