diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2c406ddc6354..ad1d35526a8f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2079,31 +2079,23 @@ haswell_update_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	enum pipe pipe = intel_crtc->pipe;
 	struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
-	u32 temp;
+	u32 linetime, ips_linetime;
 
 	if (!intel_crtc_active(crtc)) {
 		I915_WRITE(PIPE_WM_LINETIME(pipe), 0);
 		return;
 	}
 
-	temp = I915_READ(PIPE_WM_LINETIME(pipe));
-	temp &= ~PIPE_WM_LINETIME_MASK;
-
 	/* The WM are computed with base on how long it takes to fill a single
 	 * row at the given clock rate, multiplied by 8.
 	 * */
-	temp |= PIPE_WM_LINETIME_TIME(
-		DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock));
+	linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock);
+	ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8,
+					 intel_ddi_get_cdclk_freq(dev_priv));
 
-	/* IPS watermarks are only used by pipe A, and are ignored by
-	 * pipes B and C.  They are calculated similarly to the common
-	 * linetime values, except that we are using CD clock frequency
-	 * in MHz instead of pixel rate for the division.
-	 *
-	 * This is a placeholder for the IPS watermark calculation code.
-	 */
-
-	I915_WRITE(PIPE_WM_LINETIME(pipe), temp);
+	I915_WRITE(PIPE_WM_LINETIME(pipe),
+		   PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
+		   PIPE_WM_LINETIME_TIME(linetime));
 }
 
 static void haswell_update_wm(struct drm_device *dev)