pata_hpt366: remove redundant code
There's no need to clear the fast interrupt bit in hpt366_set_mode() since we're doing it in hpt366_init_chipset() already. While at it, rename 'addr1' local variable to 'addr' and exclude 'ap->port_no' from its calculation as HPT36x are single-channel-per-function chips. Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
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@ -27,7 +27,7 @@
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#include <linux/libata.h>
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#define DRV_NAME "pata_hpt366"
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#define DRV_VERSION "0.6.7"
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#define DRV_VERSION "0.6.8"
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struct hpt_clock {
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u8 xfer_mode;
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@ -207,17 +207,8 @@ static void hpt366_set_mode(struct ata_port *ap, struct ata_device *adev,
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{
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struct hpt_clock *clocks = ap->host->private_data;
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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u32 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
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u32 addr2 = 0x51 + 4 * ap->port_no;
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u32 addr = 0x40 + 4 * adev->devno;
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u32 mask, reg;
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u8 fast;
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/* Fast interrupt prediction disable, hold off interrupt disable */
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pci_read_config_byte(pdev, addr2, &fast);
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if (fast & 0x80) {
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fast &= ~0x80;
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pci_write_config_byte(pdev, addr2, fast);
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}
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/* determine timing mask and find matching clock entry */
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if (mode < XFER_MW_DMA_0)
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@ -240,9 +231,9 @@ static void hpt366_set_mode(struct ata_port *ap, struct ata_device *adev,
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* on-chip PIO FIFO/buffer (and PIO MST mode as well) to avoid
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* problems handling I/O errors later.
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*/
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pci_read_config_dword(pdev, addr1, ®);
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pci_read_config_dword(pdev, addr, ®);
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reg = ((reg & ~mask) | (clocks->timing & mask)) & ~0xc0000000;
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pci_write_config_dword(pdev, addr1, reg);
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pci_write_config_dword(pdev, addr, reg);
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}
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/**
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