Second Round of Renesas ARM Based SoC DT Updates for v4.21
* RZ/G1N (r8a7744) SoC - Describe in DT: SYS-DMAC, GPIO, Ethernet AVB, SMP, [H]SCIF{A|B}, I2C, USB 2.0 and 3.0 hosts, USB-DMAC, HSUSB, RWDT, Audio, CAN, IRQC, thermal, CMT, VIN, VSP, IPMMU, PMU, TPU, QSPI MSIOF, and PCIE - iWave G20D-Q7 board - Initial support - Enable eMMC, SDHI and SPIO NOR support - Add camera daughterboard * RZ/G1M (r8a7743) SoC - Remove legacy "renesas,rcar-thermal" compatibility -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE4nzZofWswv9L/nKF189kaWo3T74FAlwJfHEACgkQ189kaWo3 T74jMxAAsdHY2LYOaNTJwuttITl1nuq8BxHfHyW4vM8VnVm/BL0DbTVibLgOUkP+ pUPAFwoJhXVvX3aM0n7miXk8BH+YHyX4+rBP5HWnbF79p4Z1f6tqLpUJ0s4xIfk6 foU6LiQiHgMgrImPolJmwGMvmZj4IzC+Od1Id34ElqMW5KZALmg4m3AEFUie7Kp7 3/qwDteKB9kiI26oRGRzj72LlBtA7+uVwdwnMIOce6SjFpyUFDgOelyIwF91gz37 r97wyeON6CfsAUbGOCR915JonuWoPtLPKaJweuTftsmgJqYbIm6X38G6V8u4eCui /AQwTrSFD5q9SrDOxW9e/KRFKEayFig4O9QkZIEBFpJDzLNgSseNydCidC9TznrA 11uK5ryPL1DLur/Fh5L5cxQ9VM+eaquS5TpvsPzZn/aNRHFtbPBfYY15we1Z9SJ1 NwTJZAtdaFjpKe7jOMM8iEUSqXKXMg6ue5EMBXVPqrhdld+JrTku9ju+/DlKDwM8 QrJwioeyY7Lrw/rRohO0cvbP98WYGfbEG6iPaW+nTTiNX0TgOMHw3qDNADKPUYYg LXdRnGASIOAT1yC4MwPTqh5u9r9cxjo086YD5ETvMNjg/NZHMDlN13LFOV6uHeXa nhP+4aq41+C9CbGYzP7iTtmFUf2BDJ6CE50I4Lx9C/F6i03T1Qk= =cq6J -----END PGP SIGNATURE----- Merge tag 'renesas-arm-dt2-for-v4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt Second Round of Renesas ARM Based SoC DT Updates for v4.21 * RZ/G1N (r8a7744) SoC - Describe in DT: SYS-DMAC, GPIO, Ethernet AVB, SMP, [H]SCIF{A|B}, I2C, USB 2.0 and 3.0 hosts, USB-DMAC, HSUSB, RWDT, Audio, CAN, IRQC, thermal, CMT, VIN, VSP, IPMMU, PMU, TPU, QSPI MSIOF, and PCIE - iWave G20D-Q7 board - Initial support - Enable eMMC, SDHI and SPIO NOR support - Add camera daughterboard * RZ/G1M (r8a7743) SoC - Remove legacy "renesas,rcar-thermal" compatibility * tag 'renesas-arm-dt2-for-v4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (34 commits) ARM: dts: r8a7744-iwg20m: Add SPI NOR support ARM: dts: iwg20d-q7-common: Move cmt/rwdt node out of RZ/G1M SOM ARM: dts: r8a7744: Add PCIe Controller device node ARM: dts: r8a7744: Add xhci support ARM: dts: r8a7744: Add MSIOF[012] support ARM: dts: r8a7744: Add QSPI support ARM: dts: r8a7744-iwg20d-q7-dbcm-ca: Add device tree for camera DB ARM: dts: r8a7744: Add TPU support ARM: dts: r8a7744: Add PWM SoC support ARM: dts: r8a7744: Add IPMMU DT nodes ARM: dts: r8a7744: Add VSP support ARM: dts: r8a7744: add VIN dt support ARM: dts: r8a7744: Add CMT SoC specific support ARM: dts: r8a7744: Add thermal device to DT ARM: dts: r8a7744: Add IRQC support ARM: dts: r8a7744: Add CAN support ARM: dts: r8a7744: Add audio support ARM: dts: r8a7744: Add RWDT node ARM: dts: r8a7744: Add USB-DMAC and HSUSB device nodes ARM: dts: r8a7744: USB 2.0 host support ... Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
commit
857f002133
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@ -836,6 +836,8 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
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r8a7743-iwg20d-q7.dtb \
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r8a7743-iwg20d-q7-dbcm-ca.dtb \
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r8a7743-sk-rzg1m.dtb \
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r8a7744-iwg20d-q7.dtb \
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r8a7744-iwg20d-q7-dbcm-ca.dtb \
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r8a7745-iwg22d-sodimm.dtb \
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r8a7745-iwg22d-sodimm-dbhd-ca.dtb \
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r8a7745-sk-rzg1e.dtb \
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@ -116,6 +116,10 @@
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status = "okay";
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};
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&cmt0 {
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status = "okay";
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};
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&hsusb {
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status = "okay";
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pinctrl-0 = <&usb0_pins>;
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@ -230,6 +234,11 @@
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};
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};
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&rwdt {
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timeout-sec = <60>;
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status = "okay";
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};
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&scif0 {
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pinctrl-0 = <&scif0_pins>;
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pinctrl-names = "default";
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@ -31,10 +31,6 @@
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};
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};
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&cmt0 {
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status = "okay";
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};
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&extal_clk {
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clock-frequency = <20000000>;
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};
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@ -88,11 +84,6 @@
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};
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};
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&rwdt {
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timeout-sec = <60>;
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status = "okay";
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};
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&sdhi0 {
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pinctrl-0 = <&sdhi0_pins>;
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pinctrl-names = "default";
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@ -348,8 +348,7 @@
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thermal: thermal@e61f0000 {
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compatible = "renesas,thermal-r8a7743",
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"renesas,rcar-gen2-thermal",
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"renesas,rcar-thermal";
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"renesas,rcar-gen2-thermal";
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reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
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interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 522>;
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@ -0,0 +1,17 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for the iWave Systems RZ/G1N Qseven board development
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* platform with camera daughter board
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*
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* Copyright (C) 2018 Renesas Electronics Corp.
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*/
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/dts-v1/;
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#include "r8a7744-iwg20m.dtsi"
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#include "iwg20d-q7-common.dtsi"
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#include "iwg20d-q7-dbcm-ca.dtsi"
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/ {
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model = "iWave Systems RZ/G1N Qseven development platform with camera add-on";
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compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7744";
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};
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@ -0,0 +1,15 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for the iWave-RZ/G1N Qseven board
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*
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* Copyright (C) 2018 Renesas Electronics Corp.
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*/
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/dts-v1/;
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#include "r8a7744-iwg20m.dtsi"
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#include "iwg20d-q7-common.dtsi"
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/ {
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model = "iWave Systems RainboW-G20D-Qseven board based on RZ/G1N";
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compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7744";
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};
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@ -0,0 +1,90 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for the iWave RZ/G1N Qseven SOM
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*
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* Copyright (C) 2018 Renesas Electronics Corp.
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*/
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#include "r8a7744.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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compatible = "iwave,g20m", "renesas,r8a7744";
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memory@40000000 {
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device_type = "memory";
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reg = <0 0x40000000 0 0x40000000>;
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};
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reg_3p3v: 3p3v {
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compatible = "regulator-fixed";
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regulator-name = "3P3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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regulator-boot-on;
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};
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};
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&extal_clk {
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clock-frequency = <20000000>;
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};
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&pfc {
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mmcif0_pins: mmc {
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groups = "mmc_data8_b", "mmc_ctrl";
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function = "mmc";
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};
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qspi_pins: qspi {
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groups = "qspi_ctrl", "qspi_data2";
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function = "qspi";
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};
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sdhi0_pins: sd0 {
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groups = "sdhi0_data4", "sdhi0_ctrl";
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function = "sdhi0";
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power-source = <3300>;
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};
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};
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&mmcif0 {
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pinctrl-0 = <&mmcif0_pins>;
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pinctrl-names = "default";
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vmmc-supply = <®_3p3v>;
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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&qspi {
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pinctrl-0 = <&qspi_pins>;
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pinctrl-names = "default";
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status = "okay";
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/* WARNING - This device contains the bootloader. Handle with care. */
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flash: flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <50000000>;
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spi-tx-bus-width = <2>;
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spi-rx-bus-width = <2>;
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m25p,fast-read;
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spi-cpol;
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spi-cpha;
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};
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};
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&sdhi0 {
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pinctrl-0 = <&sdhi0_pins>;
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pinctrl-names = "default";
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vmmc-supply = <®_3p3v>;
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vqmmc-supply = <®_3p3v>;
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cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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