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ath9k: reuse ar9003_hw_tx_power_regwrite for tx99 setup 

The same functionality as ar9003_hw_tx_power_regwrite is hardcoded in
ar9003_hw_tx99_set_txpower. Just reuse the existing ar9003_hw_tx_power_regwrite
for TX99 setup too.

Signed-off-by: Helmut Schaa <helmut.schaa@googlemail.com>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
This commit is contained in:
Helmut Schaa 2016-04-28 16:45:04 +02:00 committed by Kalle Valo
parent 9a5f91a1d6
commit 8569f59154
3 changed files with 5 additions and 58 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
View File

@ -4402,7 +4402,7 @@ static void ar9003_hw_selfgen_tpc_txpower(struct ath_hw *ah,
}
/* Set tx power registers to array of values passed in */
static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
{
#define POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
/* make sure forced gain is not set */

1
drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
View File

@ -355,5 +355,6 @@ unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
struct ath9k_channel *chan);
void ar9003_hw_internal_regulator_apply(struct ath_hw *ah);
int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray);
#endif

60
drivers/net/wireless/ath/ath9k/ar9003_phy.c
View File

@ -17,6 +17,7 @@
#include <linux/export.h>
#include "hw.h"
#include "ar9003_phy.h"
#include "ar9003_eeprom.h"
#define AR9300_OFDM_RATES 8
#define AR9300_HT_SS_RATES 8
@ -1840,7 +1841,7 @@ static void ar9003_hw_tx99_stop(struct ath_hw *ah)
static void ar9003_hw_tx99_set_txpower(struct ath_hw *ah, u8 txpower)
{
static s16 p_pwr_array[ar9300RateSize] = { 0 };
static u8 p_pwr_array[ar9300RateSize] = { 0 };
unsigned int i;
if (txpower <= MAX_RATE_POWER) {
@ -1851,62 +1852,7 @@ static void ar9003_hw_tx99_set_txpower(struct ath_hw *ah, u8 txpower)
p_pwr_array[i] = MAX_RATE_POWER;
}
REG_WRITE(ah, 0xa458, 0);
REG_WRITE(ah, 0xa3c0,
ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 24) |
ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 16) |
ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 8) |
ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0));
REG_WRITE(ah, 0xa3c4,
ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_54], 24) |
ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_48], 16) |
ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_36], 8) |
ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0));
REG_WRITE(ah, 0xa3c8,
ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 24) |
ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 16) |
ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0));
REG_WRITE(ah, 0xa3cc,
ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_11S], 24) |
ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_11L], 16) |
ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_5S], 8) |
ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0));
REG_WRITE(ah, 0xa3d0,
ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_5], 24) |
ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_4], 16) |
ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_1_3_9_11_17_19], 8)|
ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_0_8_16], 0));
REG_WRITE(ah, 0xa3d4,
ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_13], 24) |
ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_12], 16) |
ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_7], 8) |
ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_6], 0));
REG_WRITE(ah, 0xa3e4,
ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_21], 24) |
ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_20], 16) |
ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_15], 8) |
ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_14], 0));
REG_WRITE(ah, 0xa3e8,
ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_23], 24) |
ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_22], 16) |
ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_23], 8) |
ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_22], 0));
REG_WRITE(ah, 0xa3d8,
ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_5], 24) |
ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_4], 16) |
ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_0_8_16], 0));
REG_WRITE(ah, 0xa3dc,
ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_13], 24) |
ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_12], 16) |
ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_7], 8) |
ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_6], 0));
REG_WRITE(ah, 0xa3ec,
ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_21], 24) |
ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_20], 16) |
ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_15], 8) |
ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_14], 0));
ar9003_hw_tx_power_regwrite(ah, p_pwr_array);
}
static void ar9003_hw_init_txpower_cck(struct ath_hw *ah, u8 *rate_array)