ath9k_hw: Program correct PLL value for AR9565
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
parent
d43d04a9e1
commit
8565f8bf47
|
@ -918,7 +918,8 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
|
||||||
}
|
}
|
||||||
|
|
||||||
pll = ath9k_hw_compute_pll_control(ah, chan);
|
pll = ath9k_hw_compute_pll_control(ah, chan);
|
||||||
|
if (AR_SREV_9565(ah))
|
||||||
|
pll |= 0x40000;
|
||||||
REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
|
REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
|
||||||
|
|
||||||
if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
|
if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
|
||||||
|
|
Loading…
Reference in New Issue