drm/amd/pm/powerplay/hwmgr/vega10_hwmgr: Fix a bunch of kernel-doc formatting issues
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.c:5474:5: warning: no previous prototype for ‘vega10_hwmgr_init’ [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.c:551: warning: Function parameter or member 'hwmgr' not described in 'vega10_get_evv_voltages' drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.c:609: warning: Function parameter or member 'hwmgr' not described in 'vega10_patch_with_vdd_leakage' drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.c:609: warning: Function parameter or member 'voltage' not described in 'vega10_patch_with_vdd_leakage' drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.c:609: warning: Function parameter or member 'leakage_table' not described in 'vega10_patch_with_vdd_leakage' drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.c:637: warning: Function parameter or member 'hwmgr' not described in 'vega10_patch_lookup_table_with_leakage' drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.c:637: warning: Function parameter or member 'lookup_table' not described in 'vega10_patch_lookup_table_with_leakage' drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.c:637: warning: Function parameter or member 'leakage_table' not described in 'vega10_patch_lookup_table_with_leakage' drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.c:1013: warning: Function parameter or member 'hwmgr' not described in 'vega10_trim_voltage_table' drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.c:1013: warning: Function parameter or member 'vol_table' not described in 'vega10_trim_voltage_table' drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.c:1160: warning: Function parameter or member 'hwmgr' not described in 'vega10_construct_voltage_tables' drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.c:1558: warning: Function parameter or member 'hwmgr' not described in 'vega10_populate_single_gfx_level' drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.c:1558: warning: Function parameter or member 'gfx_clock' not described in 'vega10_populate_single_gfx_level' drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.c:1558: warning: Function parameter or member 'current_gfxclk_level' not described in 'vega10_populate_single_gfx_level' drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.c:1558: warning: Function parameter or member 'acg_freq' not described in 'vega10_populate_single_gfx_level' drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.c:1613: warning: Cannot understand * @brief Populates single SMC SOCCLK structure using the provided clock. drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.c:1667: warning: Function parameter or member 'hwmgr' not described in 'vega10_populate_all_graphic_levels' drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.c:1750: warning: Cannot understand * @brief Populates single SMC GFXCLK structure using the provided clock. drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.c:1811: warning: Cannot understand * @brief Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states. drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.c:2496: warning: Function parameter or member 'hwmgr' not described in 'vega10_init_smc_table' drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.c:2867: warning: Cannot understand * @brief Tell SMC to enabled the supported DPMs. Cc: Evan Quan <evan.quan@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Lee Jones
Alex Deucher
parent
eb315eb0bd
commit
8565db8087
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@ -542,11 +542,11 @@ static int vega10_get_socclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
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#define ATOM_VIRTUAL_VOLTAGE_ID0 0xff01
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/**
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* Get Leakage VDDC based on leakage ID.
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*
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* @param hwmgr the address of the powerplay hardware manager.
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* @return always 0.
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*/
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* Get Leakage VDDC based on leakage ID.
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*
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* @hwmgr: the address of the powerplay hardware manager.
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* return: always 0.
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*/
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static int vega10_get_evv_voltages(struct pp_hwmgr *hwmgr)
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{
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struct vega10_hwmgr *data = hwmgr->backend;
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@ -600,9 +600,9 @@ static int vega10_get_evv_voltages(struct pp_hwmgr *hwmgr)
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/**
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* Change virtual leakage voltage to actual value.
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*
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* @param hwmgr the address of the powerplay hardware manager.
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* @param pointer to changing voltage
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* @param pointer to leakage table
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* @hwmgr: the address of the powerplay hardware manager.
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* @voltage: pointer to changing voltage
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* @leakage_table: pointer to leakage table
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*/
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static void vega10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
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uint16_t *voltage, struct vega10_leakage_voltage *leakage_table)
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@ -624,13 +624,13 @@ static void vega10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
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}
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/**
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* Patch voltage lookup table by EVV leakages.
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*
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* @param hwmgr the address of the powerplay hardware manager.
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* @param pointer to voltage lookup table
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* @param pointer to leakage table
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* @return always 0
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*/
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* Patch voltage lookup table by EVV leakages.
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*
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* @hwmgr: the address of the powerplay hardware manager.
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* @lookup_table: pointer to voltage lookup table
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* @leakage_table: pointer to leakage table
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* return: always 0
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*/
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static int vega10_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
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phm_ppt_v1_voltage_lookup_table *lookup_table,
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struct vega10_leakage_voltage *leakage_table)
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@ -1001,13 +1001,12 @@ static int vega10_setup_asic_task(struct pp_hwmgr *hwmgr)
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}
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/**
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* Remove repeated voltage values and create table with unique values.
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*
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* @param hwmgr the address of the powerplay hardware manager.
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* @param vol_table the pointer to changing voltage table
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* @return 0 in success
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*/
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* Remove repeated voltage values and create table with unique values.
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*
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* @hwmgr: the address of the powerplay hardware manager.
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* @vol_table: the pointer to changing voltage table
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* return: 0 in success
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*/
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static int vega10_trim_voltage_table(struct pp_hwmgr *hwmgr,
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struct pp_atomfwctrl_voltage_table *vol_table)
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{
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@ -1151,11 +1150,11 @@ static void vega10_trim_voltage_table_to_fit_state_table(
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}
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/**
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* Create Voltage Tables.
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*
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* @param hwmgr the address of the powerplay hardware manager.
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* @return always 0
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*/
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* Create Voltage Tables.
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*
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* @hwmgr: the address of the powerplay hardware manager.
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* return: always 0
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*/
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static int vega10_construct_voltage_tables(struct pp_hwmgr *hwmgr)
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{
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struct vega10_hwmgr *data = hwmgr->backend;
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@ -1212,11 +1211,11 @@ static int vega10_construct_voltage_tables(struct pp_hwmgr *hwmgr)
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}
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/*
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* @fn vega10_init_dpm_state
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* @brief Function to initialize all Soft Min/Max and Hard Min/Max to 0xff.
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* vega10_init_dpm_state
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* Function to initialize all Soft Min/Max and Hard Min/Max to 0xff.
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*
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* @param dpm_state - the address of the DPM Table to initiailize.
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* @return None.
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* @dpm_state: - the address of the DPM Table to initiailize.
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* return: None.
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*/
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static void vega10_init_dpm_state(struct vega10_dpm_state *dpm_state)
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{
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@ -1460,11 +1459,11 @@ static int vega10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
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}
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/*
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* @fn vega10_populate_ulv_state
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* @brief Function to provide parameters for Utral Low Voltage state to SMC.
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* vega10_populate_ulv_state
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* Function to provide parameters for Utral Low Voltage state to SMC.
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*
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* @param hwmgr - the address of the hardware manager.
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* @return Always 0.
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* @hwmgr: - the address of the hardware manager.
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* return: Always 0.
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*/
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static int vega10_populate_ulv_state(struct pp_hwmgr *hwmgr)
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{
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@ -1545,13 +1544,12 @@ static int vega10_populate_smc_link_levels(struct pp_hwmgr *hwmgr)
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}
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/**
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* Populates single SMC GFXSCLK structure using the provided engine clock
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*
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* @param hwmgr the address of the hardware manager
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* @param gfx_clock the GFX clock to use to populate the structure.
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* @param current_gfxclk_level location in PPTable for the SMC GFXCLK structure.
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*/
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* Populates single SMC GFXSCLK structure using the provided engine clock
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*
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* @hwmgr: the address of the hardware manager
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* @gfx_clock: the GFX clock to use to populate the structure.
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* @current_gfxclk_level: location in PPTable for the SMC GFXCLK structure.
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*/
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static int vega10_populate_single_gfx_level(struct pp_hwmgr *hwmgr,
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uint32_t gfx_clock, PllSetting_t *current_gfxclk_level,
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uint32_t *acg_freq)
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@ -1610,12 +1608,12 @@ static int vega10_populate_single_gfx_level(struct pp_hwmgr *hwmgr,
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}
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/**
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* @brief Populates single SMC SOCCLK structure using the provided clock.
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* Populates single SMC SOCCLK structure using the provided clock.
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*
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* @param hwmgr - the address of the hardware manager.
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* @param soc_clock - the SOC clock to use to populate the structure.
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* @param current_socclk_level - location in PPTable for the SMC SOCCLK structure.
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* @return 0 on success..
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* @hwmgr: the address of the hardware manager.
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* @soc_clock: the SOC clock to use to populate the structure.
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* @current_socclk_level: location in PPTable for the SMC SOCCLK structure.
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* return: 0 on success
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*/
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static int vega10_populate_single_soc_level(struct pp_hwmgr *hwmgr,
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uint32_t soc_clock, uint8_t *current_soc_did,
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@ -1659,10 +1657,10 @@ static int vega10_populate_single_soc_level(struct pp_hwmgr *hwmgr,
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}
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/**
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* Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
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*
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* @param hwmgr the address of the hardware manager
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*/
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* Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
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*
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* @hwmgr: the address of the hardware manager
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*/
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static int vega10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
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{
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struct vega10_hwmgr *data = hwmgr->backend;
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@ -1747,11 +1745,11 @@ static void vega10_populate_vddc_soc_levels(struct pp_hwmgr *hwmgr)
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}
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/**
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* @brief Populates single SMC GFXCLK structure using the provided clock.
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* Populates single SMC GFXCLK structure using the provided clock.
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*
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* @param hwmgr - the address of the hardware manager.
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* @param mem_clock - the memory clock to use to populate the structure.
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* @return 0 on success..
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* @hwmgr: the address of the hardware manager.
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* @mem_clock: the memory clock to use to populate the structure.
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* return: 0 on success..
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*/
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static int vega10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
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uint32_t mem_clock, uint8_t *current_mem_vid,
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@ -1808,10 +1806,10 @@ static int vega10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
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}
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/**
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* @brief Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states.
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* Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states.
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*
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* @param pHwMgr - the address of the hardware manager.
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* @return PP_Result_OK on success.
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* @hwmgr: the address of the hardware manager.
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* return: PP_Result_OK on success.
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*/
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static int vega10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
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{
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@ -2486,12 +2484,11 @@ static void vega10_check_dpm_table_updated(struct pp_hwmgr *hwmgr)
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}
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/**
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* Initializes the SMC table and uploads it
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*
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* @param hwmgr the address of the powerplay hardware manager.
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* @param pInput the pointer to input data (PowerState)
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* @return always 0
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*/
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* Initializes the SMC table and uploads it
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*
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* @hwmgr: the address of the powerplay hardware manager.
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* return: always 0
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*/
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static int vega10_init_smc_table(struct pp_hwmgr *hwmgr)
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{
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int result;
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@ -2864,11 +2861,11 @@ static int vega10_stop_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
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}
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/**
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* @brief Tell SMC to enabled the supported DPMs.
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* Tell SMC to enabled the supported DPMs.
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*
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* @param hwmgr - the address of the powerplay hardware manager.
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* @Param bitmap - bitmap for the features to enabled.
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* @return 0 on at least one DPM is successfully enabled.
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* @hwmgr: the address of the powerplay hardware manager.
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* @bitmap bitmap for the features to enabled.
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* return: 0 on at least one DPM is successfully enabled.
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*/
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static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
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{
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