bus: mhi: Add MHI PCI support for WWAN modems
This is a generic MHI-over-PCI controller driver for MHI only devices such as QCOM modems. For now it supports registering of Qualcomm SDX55 based PCIe modules. The MHI channels have been extracted from mhi downstream driver. This driver is for MHI-only devices which have all functionalities exposed through MHI channels and accessed by the corresponding MHI device drivers (no out-of-band communication). Signed-off-by: Loic Poulain <loic.poulain@linaro.org> Reviewed-by: Bhaumik Bhatt <bbhatt@codeaurora.org> Reviewed-by: Hemant Kumar <hemantk@codeaurora.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> [mani: fixed up the Makefile rule] Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
This commit is contained in:
Loic Poulain
Manivannan Sadhasivam
parent
8ff3f7bdde
commit
855a70c120
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@ -20,3 +20,12 @@ config MHI_BUS_DEBUG
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Enable debugfs support for use with the MHI transport. Allows
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reading and/or modifying some values within the MHI controller
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for debug and test purposes.
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config MHI_BUS_PCI_GENERIC
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tristate "MHI PCI controller driver"
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depends on MHI_BUS
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depends on PCI
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help
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This driver provides MHI PCI controller driver for devices such as
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Qualcomm SDX55 based PCIe modems.
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@ -1,2 +1,6 @@
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# core layer
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obj-y += core/
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obj-$(CONFIG_MHI_BUS_PCI_GENERIC) += mhi_pci_generic.o
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mhi_pci_generic-y += pci_generic.o
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@ -0,0 +1,345 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* MHI PCI driver - MHI over PCI controller driver
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*
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* This module is a generic driver for registering MHI-over-PCI devices,
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* such as PCIe QCOM modems.
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*
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* Copyright (C) 2020 Linaro Ltd <loic.poulain@linaro.org>
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*/
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#include <linux/device.h>
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#include <linux/mhi.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#define MHI_PCI_DEFAULT_BAR_NUM 0
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/**
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* struct mhi_pci_dev_info - MHI PCI device specific information
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* @config: MHI controller configuration
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* @name: name of the PCI module
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* @fw: firmware path (if any)
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* @edl: emergency download mode firmware path (if any)
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* @bar_num: PCI base address register to use for MHI MMIO register space
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* @dma_data_width: DMA transfer word size (32 or 64 bits)
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*/
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struct mhi_pci_dev_info {
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const struct mhi_controller_config *config;
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const char *name;
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const char *fw;
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const char *edl;
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unsigned int bar_num;
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unsigned int dma_data_width;
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};
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#define MHI_CHANNEL_CONFIG_UL(ch_num, ch_name, el_count, ev_ring) \
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{ \
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.num = ch_num, \
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.name = ch_name, \
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.num_elements = el_count, \
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.event_ring = ev_ring, \
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.dir = DMA_TO_DEVICE, \
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.ee_mask = BIT(MHI_EE_AMSS), \
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.pollcfg = 0, \
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.doorbell = MHI_DB_BRST_DISABLE, \
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.lpm_notify = false, \
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.offload_channel = false, \
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.doorbell_mode_switch = false, \
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} \
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#define MHI_CHANNEL_CONFIG_DL(ch_num, ch_name, el_count, ev_ring) \
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{ \
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.num = ch_num, \
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.name = ch_name, \
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.num_elements = el_count, \
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.event_ring = ev_ring, \
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.dir = DMA_FROM_DEVICE, \
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.ee_mask = BIT(MHI_EE_AMSS), \
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.pollcfg = 0, \
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.doorbell = MHI_DB_BRST_DISABLE, \
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.lpm_notify = false, \
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.offload_channel = false, \
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.doorbell_mode_switch = false, \
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}
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#define MHI_EVENT_CONFIG_CTRL(ev_ring) \
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{ \
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.num_elements = 64, \
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.irq_moderation_ms = 0, \
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.irq = (ev_ring) + 1, \
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.priority = 1, \
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.mode = MHI_DB_BRST_DISABLE, \
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.data_type = MHI_ER_CTRL, \
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.hardware_event = false, \
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.client_managed = false, \
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.offload_channel = false, \
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}
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#define MHI_EVENT_CONFIG_DATA(ev_ring) \
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{ \
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.num_elements = 128, \
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.irq_moderation_ms = 5, \
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.irq = (ev_ring) + 1, \
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.priority = 1, \
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.mode = MHI_DB_BRST_DISABLE, \
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.data_type = MHI_ER_DATA, \
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.hardware_event = false, \
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.client_managed = false, \
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.offload_channel = false, \
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}
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#define MHI_EVENT_CONFIG_HW_DATA(ev_ring, ch_num) \
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{ \
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.num_elements = 128, \
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.irq_moderation_ms = 5, \
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.irq = (ev_ring) + 1, \
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.priority = 1, \
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.mode = MHI_DB_BRST_DISABLE, \
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.data_type = MHI_ER_DATA, \
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.hardware_event = true, \
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.client_managed = false, \
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.offload_channel = false, \
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.channel = ch_num, \
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}
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static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = {
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MHI_CHANNEL_CONFIG_UL(12, "MBIM", 4, 0),
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MHI_CHANNEL_CONFIG_DL(13, "MBIM", 4, 0),
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MHI_CHANNEL_CONFIG_UL(14, "QMI", 4, 0),
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MHI_CHANNEL_CONFIG_DL(15, "QMI", 4, 0),
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MHI_CHANNEL_CONFIG_UL(20, "IPCR", 8, 0),
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MHI_CHANNEL_CONFIG_DL(21, "IPCR", 8, 0),
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MHI_CHANNEL_CONFIG_UL(100, "IP_HW0", 128, 1),
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MHI_CHANNEL_CONFIG_DL(101, "IP_HW0", 128, 2),
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};
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static const struct mhi_event_config modem_qcom_v1_mhi_events[] = {
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/* first ring is control+data ring */
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MHI_EVENT_CONFIG_CTRL(0),
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/* Hardware channels request dedicated hardware event rings */
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MHI_EVENT_CONFIG_HW_DATA(1, 100),
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MHI_EVENT_CONFIG_HW_DATA(2, 101)
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};
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static const struct mhi_controller_config modem_qcom_v1_mhiv_config = {
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.max_channels = 128,
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.timeout_ms = 5000,
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.num_channels = ARRAY_SIZE(modem_qcom_v1_mhi_channels),
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.ch_cfg = modem_qcom_v1_mhi_channels,
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.num_events = ARRAY_SIZE(modem_qcom_v1_mhi_events),
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.event_cfg = modem_qcom_v1_mhi_events,
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};
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static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = {
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.name = "qcom-sdx55m",
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.fw = "qcom/sdx55m/sbl1.mbn",
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.edl = "qcom/sdx55m/edl.mbn",
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.config = &modem_qcom_v1_mhiv_config,
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.bar_num = MHI_PCI_DEFAULT_BAR_NUM,
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.dma_data_width = 32
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};
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static const struct pci_device_id mhi_pci_id_table[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0306),
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.driver_data = (kernel_ulong_t) &mhi_qcom_sdx55_info },
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{ }
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};
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MODULE_DEVICE_TABLE(pci, mhi_pci_id_table);
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static int mhi_pci_read_reg(struct mhi_controller *mhi_cntrl,
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void __iomem *addr, u32 *out)
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{
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*out = readl(addr);
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return 0;
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}
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static void mhi_pci_write_reg(struct mhi_controller *mhi_cntrl,
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void __iomem *addr, u32 val)
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{
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writel(val, addr);
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}
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static void mhi_pci_status_cb(struct mhi_controller *mhi_cntrl,
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enum mhi_callback cb)
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{
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/* Nothing to do for now */
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}
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static int mhi_pci_claim(struct mhi_controller *mhi_cntrl,
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unsigned int bar_num, u64 dma_mask)
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{
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struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev);
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int err;
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err = pci_assign_resource(pdev, bar_num);
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if (err)
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return err;
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err = pcim_enable_device(pdev);
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if (err) {
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dev_err(&pdev->dev, "failed to enable pci device: %d\n", err);
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return err;
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}
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err = pcim_iomap_regions(pdev, 1 << bar_num, pci_name(pdev));
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if (err) {
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dev_err(&pdev->dev, "failed to map pci region: %d\n", err);
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return err;
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}
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mhi_cntrl->regs = pcim_iomap_table(pdev)[bar_num];
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err = pci_set_dma_mask(pdev, dma_mask);
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if (err) {
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dev_err(&pdev->dev, "Cannot set proper DMA mask\n");
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return err;
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}
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err = pci_set_consistent_dma_mask(pdev, dma_mask);
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if (err) {
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dev_err(&pdev->dev, "set consistent dma mask failed\n");
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return err;
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}
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pci_set_master(pdev);
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return 0;
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}
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static int mhi_pci_get_irqs(struct mhi_controller *mhi_cntrl,
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const struct mhi_controller_config *mhi_cntrl_config)
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{
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struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev);
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int nr_vectors, i;
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int *irq;
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/*
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* Alloc one MSI vector for BHI + one vector per event ring, ideally...
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* No explicit pci_free_irq_vectors required, done by pcim_release.
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*/
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mhi_cntrl->nr_irqs = 1 + mhi_cntrl_config->num_events;
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nr_vectors = pci_alloc_irq_vectors(pdev, 1, mhi_cntrl->nr_irqs, PCI_IRQ_MSI);
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if (nr_vectors < 0) {
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dev_err(&pdev->dev, "Error allocating MSI vectors %d\n",
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nr_vectors);
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return nr_vectors;
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}
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if (nr_vectors < mhi_cntrl->nr_irqs) {
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dev_warn(&pdev->dev, "Not enough MSI vectors (%d/%d), use shared MSI\n",
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nr_vectors, mhi_cntrl_config->num_events);
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}
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irq = devm_kcalloc(&pdev->dev, mhi_cntrl->nr_irqs, sizeof(int), GFP_KERNEL);
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if (!irq)
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return -ENOMEM;
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for (i = 0; i < mhi_cntrl->nr_irqs; i++) {
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int vector = i >= nr_vectors ? (nr_vectors - 1) : i;
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irq[i] = pci_irq_vector(pdev, vector);
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}
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mhi_cntrl->irq = irq;
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return 0;
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}
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static int mhi_pci_runtime_get(struct mhi_controller *mhi_cntrl)
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{
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/* no PM for now */
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return 0;
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}
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static void mhi_pci_runtime_put(struct mhi_controller *mhi_cntrl)
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{
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/* no PM for now */
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}
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static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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{
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const struct mhi_pci_dev_info *info = (struct mhi_pci_dev_info *) id->driver_data;
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const struct mhi_controller_config *mhi_cntrl_config;
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struct mhi_controller *mhi_cntrl;
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int err;
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dev_dbg(&pdev->dev, "MHI PCI device found: %s\n", info->name);
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mhi_cntrl = mhi_alloc_controller();
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if (!mhi_cntrl)
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return -ENOMEM;
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mhi_cntrl_config = info->config;
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mhi_cntrl->cntrl_dev = &pdev->dev;
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mhi_cntrl->iova_start = 0;
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mhi_cntrl->iova_stop = DMA_BIT_MASK(info->dma_data_width);
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mhi_cntrl->fw_image = info->fw;
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mhi_cntrl->edl_image = info->edl;
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mhi_cntrl->read_reg = mhi_pci_read_reg;
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mhi_cntrl->write_reg = mhi_pci_write_reg;
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mhi_cntrl->status_cb = mhi_pci_status_cb;
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mhi_cntrl->runtime_get = mhi_pci_runtime_get;
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mhi_cntrl->runtime_put = mhi_pci_runtime_put;
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err = mhi_pci_claim(mhi_cntrl, info->bar_num, DMA_BIT_MASK(info->dma_data_width));
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if (err)
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goto err_release;
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err = mhi_pci_get_irqs(mhi_cntrl, mhi_cntrl_config);
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if (err)
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goto err_release;
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pci_set_drvdata(pdev, mhi_cntrl);
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err = mhi_register_controller(mhi_cntrl, mhi_cntrl_config);
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if (err)
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goto err_release;
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/* MHI bus does not power up the controller by default */
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err = mhi_prepare_for_power_up(mhi_cntrl);
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if (err) {
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dev_err(&pdev->dev, "failed to prepare MHI controller\n");
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goto err_unregister;
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}
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err = mhi_sync_power_up(mhi_cntrl);
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if (err) {
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dev_err(&pdev->dev, "failed to power up MHI controller\n");
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goto err_unprepare;
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}
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return 0;
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err_unprepare:
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mhi_unprepare_after_power_down(mhi_cntrl);
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err_unregister:
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mhi_unregister_controller(mhi_cntrl);
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err_release:
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mhi_free_controller(mhi_cntrl);
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return err;
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}
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static void mhi_pci_remove(struct pci_dev *pdev)
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{
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struct mhi_controller *mhi_cntrl = pci_get_drvdata(pdev);
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mhi_power_down(mhi_cntrl, true);
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mhi_unprepare_after_power_down(mhi_cntrl);
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mhi_unregister_controller(mhi_cntrl);
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mhi_free_controller(mhi_cntrl);
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}
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static struct pci_driver mhi_pci_driver = {
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.name = "mhi-pci-generic",
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.id_table = mhi_pci_id_table,
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.probe = mhi_pci_probe,
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.remove = mhi_pci_remove
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};
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module_pci_driver(mhi_pci_driver);
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MODULE_AUTHOR("Loic Poulain <loic.poulain@linaro.org>");
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MODULE_DESCRIPTION("Modem Host Interface (MHI) PCI controller driver");
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MODULE_LICENSE("GPL");
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