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ARM: vexpress: Make the debug UART detection more specific 

Base the UART detection heuristic on architecturally defined
MIDR register instead of implementation dependent CBAR. The
only tile using the original memory map is V2P-CA9 with Cortex
A9 r0p1, which MIDR contains value 0x410fc091.

Signed-off-by: Pawel Moll <pawel.moll@arm.com>
This commit is contained in:
Pawel Moll 2012-09-04 17:06:20 +01:00
parent ddffeb8c4d
commit 852663d94f
1 changed files with 6 additions and 4 deletions
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10
arch/arm/include/debug/vexpress.S
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@ -23,12 +23,14 @@
.macro addruart,rp,rv,tmp
@ Make an educated guess regarding the memory map:
@ - the original A9 core tile, which has MPCore peripherals
@ located at 0x1e000000, should use UART at 0x10009000
@ - the original A9 core tile (based on ARM Cortex-A9 r0p1)
@ should use UART at 0x10009000
@ - all other (RS1 complaint) tiles use UART mapped
@ at 0x1c090000
mrc p15, 4, \tmp, c15, c0, 0
cmp \tmp, #0x1e000000
mrc p15, 0, \rp, c0, c0, 0
movw \rv, #0xc091
movt \rv, #0x410f
cmp \rp, \rv
@ Original memory map
moveq \rp, #DEBUG_LL_UART_OFFSET