net: axienet: Fix comments blocks
There is rule for network drivers with comments blocks which is newly checked by checkpatch.pl script. Let's fix it. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Michal Simek
David S. Miller
parent
c81a97b5ca
commit
850a7503b0
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@ -38,18 +38,21 @@
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#define XAE_OPTION_FLOW_CONTROL (1 << 4)
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/* Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not
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* stripped. Default: disabled (set) */
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* stripped. Default: disabled (set)
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*/
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#define XAE_OPTION_FCS_STRIP (1 << 5)
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/* Generate FCS field and add PAD automatically for outgoing frames.
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* Default: enabled (set) */
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* Default: enabled (set)
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*/
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#define XAE_OPTION_FCS_INSERT (1 << 6)
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/* Enable Length/Type error checking for incoming frames. When this option is
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* set, the MAC will filter frames that have a mismatched type/length field
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* and if XAE_OPTION_REPORT_RXERR is set, the user is notified when these
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* types of frames are encountered. When this option is cleared, the MAC will
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* allow these types of frames to be received. Default: enabled (set) */
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* allow these types of frames to be received. Default: enabled (set)
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*/
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#define XAE_OPTION_LENTYPE_ERR (1 << 7)
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/* Enable the transmitter. Default: enabled (set) */
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@ -159,12 +162,12 @@
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#define XAE_MDIO_MWD_OFFSET 0x00000508 /* MII Management Write Data */
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#define XAE_MDIO_MRD_OFFSET 0x0000050C /* MII Management Read Data */
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#define XAE_MDIO_MIS_OFFSET 0x00000600 /* MII Management Interrupt Status */
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#define XAE_MDIO_MIP_OFFSET 0x00000620 /* MII Mgmt Interrupt Pending
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* register offset */
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#define XAE_MDIO_MIE_OFFSET 0x00000640 /* MII Management Interrupt Enable
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* register offset */
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#define XAE_MDIO_MIC_OFFSET 0x00000660 /* MII Management Interrupt Clear
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* register offset. */
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/* MII Mgmt Interrupt Pending register offset */
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#define XAE_MDIO_MIP_OFFSET 0x00000620
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/* MII Management Interrupt Enable register offset */
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#define XAE_MDIO_MIE_OFFSET 0x00000640
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/* MII Management Interrupt Clear register offset. */
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#define XAE_MDIO_MIC_OFFSET 0x00000660
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#define XAE_UAW0_OFFSET 0x00000700 /* Unicast address word 0 */
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#define XAE_UAW1_OFFSET 0x00000704 /* Unicast address word 1 */
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#define XAE_FMI_OFFSET 0x00000708 /* Filter Mask Index */
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@ -176,18 +179,17 @@
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#define XAE_MCAST_TABLE_OFFSET 0x00020000 /* Multicast table address */
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/* Bit Masks for Axi Ethernet RAF register */
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#define XAE_RAF_MCSTREJ_MASK 0x00000002 /* Reject receive multicast
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* destination address */
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#define XAE_RAF_BCSTREJ_MASK 0x00000004 /* Reject receive broadcast
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* destination address */
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/* Reject receive multicast destination address */
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#define XAE_RAF_MCSTREJ_MASK 0x00000002
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/* Reject receive broadcast destination address */
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#define XAE_RAF_BCSTREJ_MASK 0x00000004
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#define XAE_RAF_TXVTAGMODE_MASK 0x00000018 /* Tx VLAN TAG mode */
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#define XAE_RAF_RXVTAGMODE_MASK 0x00000060 /* Rx VLAN TAG mode */
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#define XAE_RAF_TXVSTRPMODE_MASK 0x00000180 /* Tx VLAN STRIP mode */
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#define XAE_RAF_RXVSTRPMODE_MASK 0x00000600 /* Rx VLAN STRIP mode */
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#define XAE_RAF_NEWFNCENBL_MASK 0x00000800 /* New function mode */
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#define XAE_RAF_EMULTIFLTRENBL_MASK 0x00001000 /* Exteneded Multicast
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* Filtering mode
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*/
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/* Exteneded Multicast Filtering mode */
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#define XAE_RAF_EMULTIFLTRENBL_MASK 0x00001000
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#define XAE_RAF_STATSRST_MASK 0x00002000 /* Stats. Counter Reset */
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#define XAE_RAF_RXBADFRMEN_MASK 0x00004000 /* Recv Bad Frame Enable */
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#define XAE_RAF_TXVTAGMODE_SHIFT 3 /* Tx Tag mode shift bits */
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@ -197,15 +199,16 @@
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/* Bit Masks for Axi Ethernet TPF and IFGP registers */
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#define XAE_TPF_TPFV_MASK 0x0000FFFF /* Tx pause frame value */
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#define XAE_IFGP0_IFGP_MASK 0x0000007F /* Transmit inter-frame
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* gap adjustment value */
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/* Transmit inter-frame gap adjustment value */
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#define XAE_IFGP0_IFGP_MASK 0x0000007F
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/* Bit Masks for Axi Ethernet IS, IE and IP registers, Same masks apply
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* for all 3 registers. */
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#define XAE_INT_HARDACSCMPLT_MASK 0x00000001 /* Hard register access
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* complete */
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#define XAE_INT_AUTONEG_MASK 0x00000002 /* Auto negotiation
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* complete */
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* for all 3 registers.
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*/
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/* Hard register access complete */
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#define XAE_INT_HARDACSCMPLT_MASK 0x00000001
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/* Auto negotiation complete */
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#define XAE_INT_AUTONEG_MASK 0x00000002
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#define XAE_INT_RXCMPIT_MASK 0x00000004 /* Rx complete */
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#define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */
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#define XAE_INT_RXFIFOOVR_MASK 0x00000010 /* Rx fifo overrun */
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@ -215,10 +218,9 @@
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#define XAE_INT_PHYRSTCMPLT_MASK 0x00000100 /* Phy Reset complete */
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#define XAE_INT_ALL_MASK 0x0000003F /* All the ints */
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/* INT bits that indicate receive errors */
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#define XAE_INT_RECV_ERROR_MASK \
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(XAE_INT_RXRJECT_MASK | XAE_INT_RXFIFOOVR_MASK) /* INT bits that
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* indicate receive
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* errors */
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(XAE_INT_RXRJECT_MASK | XAE_INT_RXFIFOOVR_MASK)
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/* Bit masks for Axi Ethernet VLAN TPID Word 0 register */
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#define XAE_TPID_0_MASK 0x0000FFFF /* TPID 0 */
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@ -231,27 +233,28 @@
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/* Bit masks for Axi Ethernet RCW1 register */
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#define XAE_RCW1_RST_MASK 0x80000000 /* Reset */
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#define XAE_RCW1_JUM_MASK 0x40000000 /* Jumbo frame enable */
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#define XAE_RCW1_FCS_MASK 0x20000000 /* In-Band FCS enable
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* (FCS not stripped) */
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/* In-Band FCS enable (FCS not stripped) */
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#define XAE_RCW1_FCS_MASK 0x20000000
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#define XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */
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#define XAE_RCW1_VLAN_MASK 0x08000000 /* VLAN frame enable */
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#define XAE_RCW1_LT_DIS_MASK 0x02000000 /* Length/type field valid check
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* disable */
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#define XAE_RCW1_CL_DIS_MASK 0x01000000 /* Control frame Length check
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* disable */
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#define XAE_RCW1_PAUSEADDR_MASK 0x0000FFFF /* Pause frame source address
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* bits [47:32]. Bits [31:0] are
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* stored in register RCW0 */
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/* Length/type field valid check disable */
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#define XAE_RCW1_LT_DIS_MASK 0x02000000
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/* Control frame Length check disable */
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#define XAE_RCW1_CL_DIS_MASK 0x01000000
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/* Pause frame source address bits [47:32]. Bits [31:0] are
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* stored in register RCW0
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*/
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#define XAE_RCW1_PAUSEADDR_MASK 0x0000FFFF
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/* Bit masks for Axi Ethernet TC register */
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#define XAE_TC_RST_MASK 0x80000000 /* Reset */
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#define XAE_TC_JUM_MASK 0x40000000 /* Jumbo frame enable */
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#define XAE_TC_FCS_MASK 0x20000000 /* In-Band FCS enable
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* (FCS not generated) */
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/* In-Band FCS enable (FCS not generated) */
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#define XAE_TC_FCS_MASK 0x20000000
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#define XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */
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#define XAE_TC_VLAN_MASK 0x08000000 /* VLAN frame enable */
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#define XAE_TC_IFG_MASK 0x02000000 /* Inter-frame gap adjustment
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* enable */
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/* Inter-frame gap adjustment enable */
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#define XAE_TC_IFG_MASK 0x02000000
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/* Bit masks for Axi Ethernet FCC register */
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#define XAE_FCC_FCRX_MASK 0x20000000 /* Rx flow control enable */
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@ -301,10 +304,10 @@
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#define XAE_MDIO_INT_MIIM_RDY_MASK 0x00000001 /* MIIM Interrupt */
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/* Bit masks for Axi Ethernet UAW1 register */
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#define XAE_UAW1_UNICASTADDR_MASK 0x0000FFFF /* Station address bits
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* [47:32]; Station address
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* bits [31:0] are stored in
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* register UAW0 */
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/* Station address bits [47:32]; Station address
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* bits [31:0] are stored in register UAW0
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*/
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#define XAE_UAW1_UNICASTADDR_MASK 0x0000FFFF
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/* Bit masks for Axi Ethernet FMI register */
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#define XAE_FMI_PM_MASK 0x80000000 /* Promis. mode enable */
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@ -320,8 +323,8 @@
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#define XAE_PHY_TYPE_SGMII 4
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#define XAE_PHY_TYPE_1000BASE_X 5
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#define XAE_MULTICAST_CAM_TABLE_NUM 4 /* Total number of entries in the
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* hardware multicast table. */
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/* Total number of entries in the hardware multicast table. */
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#define XAE_MULTICAST_CAM_TABLE_NUM 4
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/* Axi Ethernet Synthesis features */
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#define XAE_FEATURE_PARTIAL_RX_CSUM (1 << 0)
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@ -198,9 +198,7 @@ static int axienet_dma_bd_init(struct net_device *ndev)
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lp->tx_bd_tail = 0;
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lp->rx_bd_ci = 0;
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/*
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* Allocate the Tx and Rx buffer descriptors.
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*/
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/* Allocate the Tx and Rx buffer descriptors. */
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lp->tx_bd_v = dma_zalloc_coherent(ndev->dev.parent,
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sizeof(*lp->tx_bd_v) * TX_BD_NUM,
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&lp->tx_bd_p, GFP_KERNEL);
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@ -263,7 +261,8 @@ static int axienet_dma_bd_init(struct net_device *ndev)
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axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
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/* Populate the tail pointer and bring the Rx Axi DMA engine out of
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* halted state. This will make the Rx side ready for reception.*/
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* halted state. This will make the Rx side ready for reception.
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*/
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axienet_dma_out32(lp, XAXIDMA_RX_CDESC_OFFSET, lp->rx_bd_p);
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cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
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axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET,
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@ -273,7 +272,8 @@ static int axienet_dma_bd_init(struct net_device *ndev)
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/* Write to the RS (Run-stop) bit in the Tx channel control register.
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* Tx channel is now ready to run. But only after we write to the
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* tail pointer register that the Tx channel will start transmitting */
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* tail pointer register that the Tx channel will start transmitting.
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*/
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axienet_dma_out32(lp, XAXIDMA_TX_CDESC_OFFSET, lp->tx_bd_p);
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cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
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axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET,
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@ -354,7 +354,8 @@ static void axienet_set_multicast_list(struct net_device *ndev)
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netdev_mc_count(ndev) > XAE_MULTICAST_CAM_TABLE_NUM) {
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/* We must make the kernel realize we had to move into
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* promiscuous mode. If it was a promiscuous mode request
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* the flag is already set. If not we set it. */
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* the flag is already set. If not we set it.
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*/
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ndev->flags |= IFF_PROMISC;
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reg = axienet_ior(lp, XAE_FMI_OFFSET);
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reg |= XAE_FMI_PM_MASK;
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@ -438,7 +439,8 @@ static void __axienet_device_reset(struct axienet_local *lp,
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/* Reset Axi DMA. This would reset Axi Ethernet core as well. The reset
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* process of Axi DMA takes a while to complete as all pending
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* commands/transfers will be flushed or completed during this
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* reset process. */
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* reset process.
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*/
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axienet_dma_out32(lp, offset, XAXIDMA_CR_RESET_MASK);
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timeout = DELAY_OF_ONE_MILLISEC;
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while (axienet_dma_in32(lp, offset) & XAXIDMA_CR_RESET_MASK) {
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@ -499,7 +501,8 @@ static void axienet_device_reset(struct net_device *ndev)
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axienet_iow(lp, XAE_FCC_OFFSET, XAE_FCC_FCRX_MASK);
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/* Sync default options with HW but leave receiver and
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* transmitter disabled.*/
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* transmitter disabled.
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*/
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axienet_setoptions(ndev, lp->options &
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~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));
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axienet_set_mac_address(ndev, NULL);
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@ -919,7 +922,8 @@ static int axienet_open(struct net_device *ndev)
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/* Disable the MDIO interface till Axi Ethernet Reset is completed.
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* When we do an Axi Ethernet reset, it resets the complete core
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* including the MDIO. If MDIO is not disabled when the reset
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* process is started, MDIO will be broken afterwards. */
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* process is started, MDIO will be broken afterwards.
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*/
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axienet_iow(lp, XAE_MDIO_MC_OFFSET,
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(mdio_mcreg & (~XAE_MDIO_MC_MDIOEN_MASK)));
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axienet_device_reset(ndev);
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@ -1365,7 +1369,8 @@ static void axienet_dma_err_handler(unsigned long data)
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/* Disable the MDIO interface till Axi Ethernet Reset is completed.
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* When we do an Axi Ethernet reset, it resets the complete core
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* including the MDIO. So if MDIO is not disabled when the reset
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* process is started, MDIO will be broken afterwards. */
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* process is started, MDIO will be broken afterwards.
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*/
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axienet_iow(lp, XAE_MDIO_MC_OFFSET, (mdio_mcreg &
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~XAE_MDIO_MC_MDIOEN_MASK));
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@ -1436,7 +1441,8 @@ static void axienet_dma_err_handler(unsigned long data)
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axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
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/* Populate the tail pointer and bring the Rx Axi DMA engine out of
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* halted state. This will make the Rx side ready for reception.*/
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* halted state. This will make the Rx side ready for reception.
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*/
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axienet_dma_out32(lp, XAXIDMA_RX_CDESC_OFFSET, lp->rx_bd_p);
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cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
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axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET,
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@ -1446,7 +1452,8 @@ static void axienet_dma_err_handler(unsigned long data)
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/* Write to the RS (Run-stop) bit in the Tx channel control register.
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* Tx channel is now ready to run. But only after we write to the
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* tail pointer register that the Tx channel will start transmitting */
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* tail pointer register that the Tx channel will start transmitting
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*/
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axienet_dma_out32(lp, XAXIDMA_TX_CDESC_OFFSET, lp->tx_bd_p);
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cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
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axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET,
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@ -1462,7 +1469,8 @@ static void axienet_dma_err_handler(unsigned long data)
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axienet_iow(lp, XAE_FCC_OFFSET, XAE_FCC_FCRX_MASK);
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/* Sync default options with HW but leave receiver and
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* transmitter disabled.*/
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* transmitter disabled.
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*/
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axienet_setoptions(ndev, lp->options &
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~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));
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axienet_set_mac_address(ndev, NULL);
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@ -183,7 +183,8 @@ int axienet_mdio_setup(struct axienet_local *lp, struct device_node *np)
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clk_div = (host_clock / (MAX_MDIO_FREQ * 2)) - 1;
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/* If there is any remainder from the division of
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* fHOST / (MAX_MDIO_FREQ * 2), then we need to add
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* 1 to the clock divisor or we will surely be above 2.5 MHz */
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* 1 to the clock divisor or we will surely be above 2.5 MHz
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*/
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if (host_clock % (MAX_MDIO_FREQ * 2))
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clk_div++;
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