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drm/i915/tgl: Implement WA_16011163337 

Set GS Timer to 224. Combine with Wa_1604555607 due to register FF_MODE2
not being able to be read.

V2: Math issue fixed

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Caz Yokoyama <caz.yokoyama@intel.com>
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20200603221150.14745-1-clinton.a.taylor@intel.com
This commit is contained in:
Clint Taylor 2020-06-03 15:11:50 -07:00 committed by Chris Wilson
parent d61345f342
commit 84f9cbf335
2 changed files with 9 additions and 4 deletions
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11
drivers/gpu/drm/i915/gt/intel_workarounds.c
View File

@ -609,11 +609,14 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
* Wa_1604555607:gen12 and Wa_1608008084:gen12
* FF_MODE2 register will return the wrong value when read. The default
* value for this register is zero for all fields and there are no bit
* masks. So instead of doing a RMW we should just write the TDS timer
* value for Wa_1604555607.
* masks. So instead of doing a RMW we should just write the GS Timer
* and TDS timer values for Wa_1604555607 and Wa_16011163337.
*/
wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK,
FF_MODE2_TDS_TIMER_128, 0);
wa_add(wal,
FF_MODE2,
FF_MODE2_GS_TIMER_MASK | FF_MODE2_TDS_TIMER_MASK,
FF_MODE2_GS_TIMER_224 | FF_MODE2_TDS_TIMER_128,
0);
/* WaDisableGPGPUMidThreadPreemption:tgl */
WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,

2
drivers/gpu/drm/i915/i915_reg.h
View File

@ -8004,6 +8004,8 @@ enum {
#define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7)
#define FF_MODE2 _MMIO(0x6604)
#define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24)
#define FF_MODE2_GS_TIMER_224 REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224)
#define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16)
#define FF_MODE2_TDS_TIMER_128 REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)