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Renesas ARM Based SoC Updates for v4.15 

* Prepare to enable SMP on R-Car E2 (r8a7794).
 
   Geert Uytterhoeven says:
   "The main hurdle here is that R-Car Gen2 boot loaders do not initialize
    the arch_timer CNTVOFF register, which thus needs workarounds on Linux.
 
    - The first patch adds a definition for MON_MODE, as suggested by Marc
      Zyngier,
    - The second patch makes sure CNTVOFF is initialized for boot and
      secondary Cortex-A15 and Cortex-A7 CPU cores, like is already done for
      the boot Cortex-A7 CPU core.  Without this, the ARM arch timer does
      not work on secondary CPU cores."
 
    A follow-up patch to enable SMP in DT on R-Car E2 (r8a7794) is currently
    deferred unto v4.16 as it depends on the above.
 
 * Enable low-level debugging support for RZ/G1E (r8a7745).
 
   Fabrizio Castro says, "RZ/G1E uses SCIF4 for the debug console."
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Merge tag 'renesas-soc-for-v4.15' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc

Pull "Renesas ARM Based SoC Updates for v4.15" from Simon Horman:

* Prepare to enable SMP on R-Car E2 (r8a7794).

  Geert Uytterhoeven says:
  "The main hurdle here is that R-Car Gen2 boot loaders do not initialize
   the arch_timer CNTVOFF register, which thus needs workarounds on Linux.

   - The first patch adds a definition for MON_MODE, as suggested by Marc
     Zyngier,
   - The second patch makes sure CNTVOFF is initialized for boot and
     secondary Cortex-A15 and Cortex-A7 CPU cores, like is already done for
     the boot Cortex-A7 CPU core.  Without this, the ARM arch timer does
     not work on secondary CPU cores."

   A follow-up patch to enable SMP in DT on R-Car E2 (r8a7794) is currently
   deferred unto v4.16 as it depends on the above.

* Enable low-level debugging support for RZ/G1E (r8a7745).

  Fabrizio Castro says, "RZ/G1E uses SCIF4 for the debug console."

* tag 'renesas-soc-for-v4.15' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: shmobile: rcar-gen2: Make sure CNTVOFF is initialized on CA7/15
  ARM: Add definition for monitor mode
  ARM: debug-ll: Add support for r8a7745
This commit is contained in:
Arnd Bergmann 2017-10-19 17:59:50 +02:00
parent e7b14ccd55 3fd45a136f
commit 84dbf97808
7 changed files with 54 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
arch/arm/Kconfig.debug
View File

@ -911,6 +911,13 @@ choice
Say Y here if you want kernel low-level debugging support
via SCIF2 on Renesas R-Car E2 (R8A7794).
config DEBUG_RCAR_GEN2_SCIF4
bool "Kernel low-level debugging messages via SCIF4 on R8A7745"
depends on ARCH_R8A7745
help
Say Y here if you want kernel low-level debugging support
via SCIF4 on Renesas RZ/G1E (R8A7745).
config DEBUG_RMOBILE_SCIFA0
bool "Kernel low-level debugging messages via SCIFA0 on R8A73A4"
depends on ARCH_R8A73A4
@ -1451,6 +1458,7 @@ config DEBUG_LL_INCLUDE
default "debug/renesas-scif.S" if DEBUG_RCAR_GEN1_SCIF2
default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF0
default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF2
default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF4
default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA0
default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA1
default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA4
@ -1570,6 +1578,7 @@ config DEBUG_UART_PHYS
default 0xe6c80000 if DEBUG_RMOBILE_SCIFA4
default 0xe6e58000 if DEBUG_RCAR_GEN2_SCIF2
default 0xe6e60000 if DEBUG_RCAR_GEN2_SCIF0
default 0xe6ee0000 if DEBUG_RCAR_GEN2_SCIF4
default 0xe8008000 if DEBUG_R7S72100_SCIF2
default 0xf0000be0 if ARCH_EBSA110
default 0xf1012000 if DEBUG_MVEBU_UART0_ALTERNATE
@ -1604,6 +1613,7 @@ config DEBUG_UART_PHYS
DEBUG_QCOM_UARTDM || DEBUG_R7S72100_SCIF2 || \
DEBUG_RCAR_GEN1_SCIF0 || DEBUG_RCAR_GEN1_SCIF2 || \
DEBUG_RCAR_GEN2_SCIF0 || DEBUG_RCAR_GEN2_SCIF2 || \
DEBUG_RCAR_GEN2_SCIF4 || \
DEBUG_RMOBILE_SCIFA0 || DEBUG_RMOBILE_SCIFA1 || \
DEBUG_RMOBILE_SCIFA4 || DEBUG_S3C24XX_UART || \
DEBUG_S3C64XX_UART || \

1
arch/arm/include/uapi/asm/ptrace.h
View File

@ -53,6 +53,7 @@
#endif
#define FIQ_MODE 0x00000011
#define IRQ_MODE 0x00000012
#define MON_MODE 0x00000016
#define ABT_MODE 0x00000017
#define HYP_MODE 0x0000001a
#define UND_MODE 0x0000001b

1
arch/arm/mach-shmobile/Makefile
View File

@ -22,6 +22,7 @@ cpu-y := platsmp.o headsmp.o
# Shared SoC family objects
obj-$(CONFIG_ARCH_RCAR_GEN2) += setup-rcar-gen2.o platsmp-apmu.o $(cpu-y)
CFLAGS_setup-rcar-gen2.o += -march=armv7-a
obj-$(CONFIG_ARCH_RCAR_GEN2) += headsmp-apmu.o
obj-$(CONFIG_ARCH_R8A7790) += regulator-quirk-rcar-gen2.o
obj-$(CONFIG_ARCH_R8A7791) += regulator-quirk-rcar-gen2.o
obj-$(CONFIG_ARCH_R8A7793) += regulator-quirk-rcar-gen2.o

2
arch/arm/mach-shmobile/common.h
View File

@ -1,6 +1,7 @@
#ifndef __ARCH_MACH_COMMON_H
#define __ARCH_MACH_COMMON_H
extern void shmobile_init_cntvoff(void);
extern void shmobile_init_delay(void);
extern void shmobile_boot_vector(void);
extern unsigned long shmobile_boot_fn;
@ -11,6 +12,7 @@ extern void shmobile_smp_hook(unsigned int cpu, unsigned long fn,
unsigned long arg);
extern bool shmobile_smp_cpu_can_disable(unsigned int cpu);
extern bool shmobile_smp_init_fallback_ops(void);
extern void shmobile_boot_apmu(void);
extern void shmobile_boot_scu(void);
extern void shmobile_smp_scu_prepare_cpus(phys_addr_t scu_base_phys,
unsigned int max_cpus);

37
arch/arm/mach-shmobile/headsmp-apmu.S Normal file
View File

@ -0,0 +1,37 @@
/*
* SMP support for APMU based systems with Cortex A7/A15
*
* Copyright (C) 2014 Renesas Electronics Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
ENTRY(shmobile_init_cntvoff)
/*
* CNTVOFF has to be initialized either from non-secure Hypervisor
* mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled
* then it should be handled by the secure code
*/
cps #MON_MODE
mrc p15, 0, r1, c1, c1, 0 /* Get Secure Config */
orr r0, r1, #1
mcr p15, 0, r0, c1, c1, 0 /* Set Non Secure bit */
instr_sync
mov r0, #0
mcrr p15, 4, r0, r0, c14 /* CNTVOFF = 0 */
instr_sync
mcr p15, 0, r1, c1, c1, 0 /* Set Secure bit */
instr_sync
cps #SVC_MODE
ret lr
ENDPROC(shmobile_init_cntvoff)
ENTRY(shmobile_boot_apmu)
bl shmobile_init_cntvoff
b secondary_startup
ENDPROC(shmobile_boot_apmu)

2
arch/arm/mach-shmobile/platsmp-apmu.c
View File

@ -204,7 +204,7 @@ void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus,
int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
/* For this particular CPU register boot vector */
shmobile_smp_hook(cpu, __pa_symbol(secondary_startup), 0);
shmobile_smp_hook(cpu, __pa_symbol(shmobile_boot_apmu), 0);
return apmu_wrap(cpu, apmu_power_on);
}

20
arch/arm/mach-shmobile/setup-rcar-gen2.c
View File

@ -70,28 +70,12 @@ void __init rcar_gen2_timer_init(void)
void __iomem *base;
u32 freq;
shmobile_init_cntvoff();
if (of_machine_is_compatible("renesas,r8a7745") ||
of_machine_is_compatible("renesas,r8a7792") ||
of_machine_is_compatible("renesas,r8a7794")) {
freq = 260000000 / 8; /* ZS / 8 */
/* CNTVOFF has to be initialized either from non-secure
* Hypervisor mode or secure Monitor mode with SCR.NS==1.
* If TrustZone is enabled then it should be handled by the
* secure code.
*/
asm volatile(
" cps 0x16\n"
" mrc p15, 0, r1, c1, c1, 0\n"
" orr r0, r1, #1\n"
" mcr p15, 0, r0, c1, c1, 0\n"
" isb\n"
" mov r0, #0\n"
" mcrr p15, 4, r0, r0, c14\n"
" isb\n"
" mcr p15, 0, r1, c1, c1, 0\n"
" isb\n"
" cps 0x13\n"
: : : "r0", "r1");
} else {
/* At Linux boot time the r8a7790 arch timer comes up
* with the counter disabled. Moreover, it may also report