crypto: hisilicon/zip - add controller reset support for zip
Register controller reset handle with PCIe AER. Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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@ -62,6 +62,7 @@
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#define HZIP_CORE_INT_SOURCE 0x3010A0
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#define HZIP_CORE_INT_MASK_REG 0x3010A4
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#define HZIP_CORE_INT_SET 0x3010A8
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#define HZIP_CORE_INT_STATUS 0x3010AC
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#define HZIP_CORE_INT_STATUS_M_ECC BIT(1)
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#define HZIP_CORE_SRAM_ECC_ERR_INFO 0x301148
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@ -83,6 +84,9 @@
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#define HZIP_SOFT_CTRL_CNT_CLR_CE 0x301000
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#define SOFT_CTRL_CNT_CLR_CE_BIT BIT(0)
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#define HZIP_SOFT_CTRL_ZIP_CONTROL 0x30100C
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#define HZIP_AXI_SHUTDOWN_ENABLE BIT(14)
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#define HZIP_WR_PORT BIT(11)
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#define HZIP_BUF_SIZE 22
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@ -254,9 +258,9 @@ int zip_create_qps(struct hisi_qp **qps, int qp_num)
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return hisi_qm_alloc_qps_node(&zip_devices, qp_num, 0, node, qps);
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}
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static void hisi_zip_set_user_domain_and_cache(struct hisi_zip *hisi_zip)
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static int hisi_zip_set_user_domain_and_cache(struct hisi_qm *qm)
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{
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void __iomem *base = hisi_zip->qm.io_base;
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void __iomem *base = qm->io_base;
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/* qm user domain */
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writel(AXUSER_BASE, base + QM_ARUSER_M_CFG_1);
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@ -283,7 +287,7 @@ static void hisi_zip_set_user_domain_and_cache(struct hisi_zip *hisi_zip)
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writel(AXUSER_BASE, base + HZIP_SGL_RUSER_32_63);
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writel(AXUSER_BASE, base + HZIP_BD_WUSER_32_63);
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if (hisi_zip->qm.use_sva) {
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if (qm->use_sva) {
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writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_RUSER_32_63);
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writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_WUSER_32_63);
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} else {
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@ -299,6 +303,8 @@ static void hisi_zip_set_user_domain_and_cache(struct hisi_zip *hisi_zip)
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writel(SQC_CACHE_ENABLE | CQC_CACHE_ENABLE | SQC_CACHE_WB_ENABLE |
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CQC_CACHE_WB_ENABLE | FIELD_PREP(SQC_CACHE_WB_THRD, 1) |
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FIELD_PREP(CQC_CACHE_WB_THRD, 1), base + QM_CACHE_CTL);
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return 0;
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}
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static void hisi_zip_hw_error_enable(struct hisi_qm *qm)
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@ -601,8 +607,6 @@ static void hisi_zip_log_hw_error(struct hisi_qm *qm, u32 err_sts)
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}
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err++;
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}
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writel(err_sts, qm->io_base + HZIP_CORE_INT_SOURCE);
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}
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static u32 hisi_zip_get_hw_err_status(struct hisi_qm *qm)
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@ -610,17 +614,56 @@ static u32 hisi_zip_get_hw_err_status(struct hisi_qm *qm)
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return readl(qm->io_base + HZIP_CORE_INT_STATUS);
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}
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static void hisi_zip_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts)
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{
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writel(err_sts, qm->io_base + HZIP_CORE_INT_SOURCE);
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}
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static void hisi_zip_open_axi_master_ooo(struct hisi_qm *qm)
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{
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u32 val;
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val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
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writel(val & ~HZIP_AXI_SHUTDOWN_ENABLE,
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qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
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writel(val | HZIP_AXI_SHUTDOWN_ENABLE,
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qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
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}
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static void hisi_zip_close_axi_master_ooo(struct hisi_qm *qm)
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{
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u32 nfe_enb;
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/* Disable ECC Mbit error report. */
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nfe_enb = readl(qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);
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writel(nfe_enb & ~HZIP_CORE_INT_STATUS_M_ECC,
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qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);
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/* Inject zip ECC Mbit error to block master ooo. */
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writel(HZIP_CORE_INT_STATUS_M_ECC,
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qm->io_base + HZIP_CORE_INT_SET);
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}
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static const struct hisi_qm_err_ini hisi_zip_err_ini = {
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.hw_init = hisi_zip_set_user_domain_and_cache,
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.hw_err_enable = hisi_zip_hw_error_enable,
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.hw_err_disable = hisi_zip_hw_error_disable,
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.get_dev_hw_err_status = hisi_zip_get_hw_err_status,
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.clear_dev_hw_err_status = hisi_zip_clear_hw_err_status,
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.log_dev_hw_err = hisi_zip_log_hw_error,
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.open_axi_master_ooo = hisi_zip_open_axi_master_ooo,
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.close_axi_master_ooo = hisi_zip_close_axi_master_ooo,
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.err_info = {
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.ce = QM_BASE_CE,
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.nfe = QM_BASE_NFE |
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QM_ACC_WB_NOT_READY_TIMEOUT,
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.fe = 0,
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.msi = QM_DB_RANDOM_INVALID,
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.ecc_2bits_mask = HZIP_CORE_INT_STATUS_M_ECC,
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.msi_wr_port = HZIP_WR_PORT,
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.acpi_rst = "ZRST",
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}
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};
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@ -651,7 +694,7 @@ static int hisi_zip_pf_probe_init(struct hisi_zip *hisi_zip)
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qm->err_ini = &hisi_zip_err_ini;
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hisi_zip_set_user_domain_and_cache(hisi_zip);
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hisi_zip_set_user_domain_and_cache(qm);
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hisi_qm_dev_err_init(qm);
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hisi_zip_debug_regs_clear(hisi_zip);
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@ -697,6 +740,7 @@ static int hisi_zip_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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qm->qp_base = HZIP_PF_DEF_Q_BASE;
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qm->qp_num = pf_q_num;
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qm->qm_list = &zip_devices;
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} else if (qm->fun_type == QM_HW_VF) {
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/*
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* have no way to get qm configure in VM in v1 hardware,
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@ -764,6 +808,7 @@ static void hisi_zip_remove(struct pci_dev *pdev)
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static const struct pci_error_handlers hisi_zip_err_handler = {
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.error_detected = hisi_qm_dev_err_detected,
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.slot_reset = hisi_qm_dev_slot_reset,
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};
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static struct pci_driver hisi_zip_pci_driver = {
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