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clk: renesas: r9a07g043: Add clock and reset entries for ADC 

Add clock and reset entries for ADC block in CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220501083450.26541-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Biju Das 2022-05-01 09:34:50 +01:00 committed by Geert Uytterhoeven
parent b676853004
commit 84c9829d16
1 changed files with 6 additions and 0 deletions
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6
drivers/clk/renesas/r9a07g043-cpg.c
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@ -243,6 +243,10 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
0x594, 0), 0x594, 0),
DEF_MOD("gpio", R9A07G043_GPIO_HCLK, R9A07G043_OSCCLK, DEF_MOD("gpio", R9A07G043_GPIO_HCLK, R9A07G043_OSCCLK,
0x598, 0), 0x598, 0),
DEF_MOD("adc_adclk", R9A07G043_ADC_ADCLK, R9A07G043_CLK_TSU,
0x5a8, 0),
DEF_MOD("adc_pclk", R9A07G043_ADC_PCLK, R9A07G043_CLK_P0,
0x5a8, 1),
DEF_MOD("tsu_pclk", R9A07G043_TSU_PCLK, R9A07G043_CLK_TSU, DEF_MOD("tsu_pclk", R9A07G043_TSU_PCLK, R9A07G043_CLK_TSU,
0x5ac, 0), 0x5ac, 0),
}; };
@ -290,6 +294,8 @@ static struct rzg2l_reset r9a07g043_resets[] = {
DEF_RST(R9A07G043_GPIO_RSTN, 0x898, 0), DEF_RST(R9A07G043_GPIO_RSTN, 0x898, 0),
DEF_RST(R9A07G043_GPIO_PORT_RESETN, 0x898, 1), DEF_RST(R9A07G043_GPIO_PORT_RESETN, 0x898, 1),
DEF_RST(R9A07G043_GPIO_SPARE_RESETN, 0x898, 2), DEF_RST(R9A07G043_GPIO_SPARE_RESETN, 0x898, 2),
DEF_RST(R9A07G043_ADC_PRESETN, 0x8a8, 0),
DEF_RST(R9A07G043_ADC_ADRST_N, 0x8a8, 1),
DEF_RST(R9A07G043_TSU_PRESETN, 0x8ac, 0), DEF_RST(R9A07G043_TSU_PRESETN, 0x8ac, 0),
}; };