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MIPS: Octeon: Expose support for mips32r1, mips32r2 and mips64r1 

Define Cavium Octeon as a CPU that has support for mips32r1, mips32r2 and
mips64r1. This will affect show_cpuinfo() that will now correctly expose
mips32r1, mips32r2 and mips64r1 as supported ISAs.

Signed-off-by: Petar Jovanovic <petar.jovanovic@rt-rk.com>
Reviewed-by: Maciej W. Rozycki <macro@imgtec.com>
Acked-by: David Daney <david.daney@cavium.com>
Cc: petar.jovanovic@imgtec.com
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/15749/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Petar Jovanovic 2017-03-15 18:59:11 +01:00 committed by Ralf Baechle
parent b123718b10
commit 846fbcfe6f
1 changed files with 3 additions and 3 deletions
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6
arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
View File

@ -46,9 +46,9 @@
#define cpu_has_64bits 1
#define cpu_has_octeon_cache 1
#define cpu_has_saa octeon_has_saa()
#define cpu_has_mips32r1 0
#define cpu_has_mips32r2 0
#define cpu_has_mips64r1 0
#define cpu_has_mips32r1 1
#define cpu_has_mips32r2 1
#define cpu_has_mips64r1 1
#define cpu_has_mips64r2 1
#define cpu_has_dsp 0
#define cpu_has_dsp2 0