drm/nouveau/secboot: put HS code loading code into own file
We will also need to load HS blobs outside of acr_r352 (for instance, to run the NVDEC VPR scrubber), so make this code reusable. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Alexandre Courbot
Ben Skeggs
parent
717bad8273
commit
84074e5b10
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@ -1,4 +1,5 @@
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nvkm-y += nvkm/subdev/secboot/base.o
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nvkm-y += nvkm/subdev/secboot/hs_ucode.o
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nvkm-y += nvkm/subdev/secboot/ls_ucode_gr.o
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nvkm-y += nvkm/subdev/secboot/ls_ucode_msgqueue.o
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nvkm-y += nvkm/subdev/secboot/acr.o
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@ -21,6 +21,7 @@
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*/
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#include "acr_r352.h"
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#include "hs_ucode.h"
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#include <core/gpuobj.h>
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#include <core/firmware.h>
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@ -31,31 +32,6 @@
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#include <core/msgqueue.h>
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#include <engine/sec2.h>
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/**
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* struct hsf_fw_header - HS firmware descriptor
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* @sig_dbg_offset: offset of the debug signature
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* @sig_dbg_size: size of the debug signature
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* @sig_prod_offset: offset of the production signature
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* @sig_prod_size: size of the production signature
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* @patch_loc: offset of the offset (sic) of where the signature is
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* @patch_sig: offset of the offset (sic) to add to sig_*_offset
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* @hdr_offset: offset of the load header (see struct hs_load_header)
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* @hdr_size: size of above header
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*
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* This structure is embedded in the HS firmware image at
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* hs_bin_hdr.header_offset.
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*/
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struct hsf_fw_header {
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u32 sig_dbg_offset;
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u32 sig_dbg_size;
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u32 sig_prod_offset;
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u32 sig_prod_size;
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u32 patch_loc;
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u32 patch_sig;
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u32 hdr_offset;
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u32 hdr_size;
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};
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/**
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* struct acr_r352_flcn_bl_desc - DMEM bootloader descriptor
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* @signature: 16B signature for secure code. 0s if no secure code
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@ -599,47 +575,6 @@ cleanup:
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/**
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* acr_r352_hsf_patch_signature() - patch HS blob with correct signature for
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* specified falcon.
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*/
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static void
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acr_r352_hsf_patch_signature(const struct nvkm_falcon *falcon, void *acr_image,
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bool new_format)
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{
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struct fw_bin_header *hsbin_hdr = acr_image;
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struct hsf_fw_header *fw_hdr = acr_image + hsbin_hdr->header_offset;
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void *hs_data = acr_image + hsbin_hdr->data_offset;
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void *sig;
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u32 sig_size;
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u32 patch_loc, patch_sig;
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/*
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* I had the brilliant idea to "improve" the binary format by
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* removing this useless indirection. However to make NVIDIA files
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* directly compatible, let's support both format.
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*/
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if (new_format) {
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patch_loc = fw_hdr->patch_loc;
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patch_sig = fw_hdr->patch_sig;
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} else {
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patch_loc = *(u32 *)(acr_image + fw_hdr->patch_loc);
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patch_sig = *(u32 *)(acr_image + fw_hdr->patch_sig);
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}
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/* Falcon in debug or production mode? */
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if (falcon->debug) {
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sig = acr_image + fw_hdr->sig_dbg_offset;
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sig_size = fw_hdr->sig_dbg_size;
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} else {
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sig = acr_image + fw_hdr->sig_prod_offset;
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sig_size = fw_hdr->sig_prod_size;
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}
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/* Patch signature */
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memcpy(hs_data + patch_loc, sig + patch_sig, sig_size);
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}
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void
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acr_r352_fixup_hs_desc(struct acr_r352 *acr, struct nvkm_secboot *sb,
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void *_desc)
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@ -687,37 +622,6 @@ acr_r352_generate_hs_bl_desc(const struct hsf_load_header *hdr, void *_bl_desc,
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bl_desc->data_size = hdr->data_size;
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}
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void *
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acr_r352_load_hs_blob(struct nvkm_secboot *sb, const struct nvkm_falcon *falcon,
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const char *fw)
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{
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struct nvkm_subdev *subdev = &sb->subdev;
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void *acr_image;
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bool new_format;
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acr_image = nvkm_acr_load_firmware(subdev, fw, 0);
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if (IS_ERR(acr_image))
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return acr_image;
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/* detect the format to define how signature should be patched */
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switch (((u32 *)acr_image)[0]) {
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case 0x3b1d14f0:
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new_format = true;
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break;
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case 0x000010de:
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new_format = false;
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break;
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default:
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nvkm_error(subdev, "unknown header for HS blob %s\n", fw);
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return ERR_PTR(-EINVAL);
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}
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/* Patch signature */
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acr_r352_hsf_patch_signature(falcon, acr_image, new_format);
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return acr_image;
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}
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/**
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* acr_r352_prepare_hs_blob - load and prepare a HS blob and BL descriptor
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*
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@ -740,7 +644,7 @@ acr_r352_prepare_hs_blob(struct acr_r352 *acr, struct nvkm_secboot *sb,
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void *acr_data;
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int ret;
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acr_image = acr_r352_load_hs_blob(sb, sb->boot_falcon, fw);
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acr_image = hs_ucode_load_blob(subdev, sb->boot_falcon, fw);
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if (IS_ERR(acr_image))
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return PTR_ERR(acr_image);
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@ -24,6 +24,7 @@
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#include "acr.h"
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#include "ls_ucode.h"
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#include "hs_ucode.h"
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struct ls_ucode_img;
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@ -33,32 +34,6 @@ struct ls_ucode_img;
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#define LSF_FLAG_DMACTL_REQ_CTX 4
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#define LSF_FLAG_FORCE_PRIV_LOAD 8
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/*
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* HS blob structures
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*/
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/**
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* struct hsf_load_header - HS firmware load header
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*/
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struct hsf_load_header {
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u32 non_sec_code_off;
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u32 non_sec_code_size;
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u32 data_dma_base;
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u32 data_size;
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u32 num_apps;
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/*
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* Organized as follows:
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* - app0_code_off
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* - app1_code_off
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* - ...
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* - appn_code_off
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* - app0_code_size
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* - app1_code_size
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* - ...
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*/
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u32 apps[0];
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};
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static inline u32
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hsf_load_header_app_off(const struct hsf_load_header *hdr, u32 app)
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{
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@ -0,0 +1,97 @@
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/*
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* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "hs_ucode.h"
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#include "ls_ucode.h"
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#include "acr.h"
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#include <engine/falcon.h>
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/**
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* hs_ucode_patch_signature() - patch HS blob with correct signature for
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* specified falcon.
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*/
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static void
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hs_ucode_patch_signature(const struct nvkm_falcon *falcon, void *acr_image,
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bool new_format)
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{
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struct fw_bin_header *hsbin_hdr = acr_image;
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struct hsf_fw_header *fw_hdr = acr_image + hsbin_hdr->header_offset;
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void *hs_data = acr_image + hsbin_hdr->data_offset;
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void *sig;
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u32 sig_size;
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u32 patch_loc, patch_sig;
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/*
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* I had the brilliant idea to "improve" the binary format by
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* removing this useless indirection. However to make NVIDIA files
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* directly compatible, let's support both format.
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*/
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if (new_format) {
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patch_loc = fw_hdr->patch_loc;
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patch_sig = fw_hdr->patch_sig;
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} else {
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patch_loc = *(u32 *)(acr_image + fw_hdr->patch_loc);
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patch_sig = *(u32 *)(acr_image + fw_hdr->patch_sig);
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}
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/* Falcon in debug or production mode? */
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if (falcon->debug) {
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sig = acr_image + fw_hdr->sig_dbg_offset;
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sig_size = fw_hdr->sig_dbg_size;
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} else {
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sig = acr_image + fw_hdr->sig_prod_offset;
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sig_size = fw_hdr->sig_prod_size;
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}
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/* Patch signature */
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memcpy(hs_data + patch_loc, sig + patch_sig, sig_size);
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}
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void *
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hs_ucode_load_blob(struct nvkm_subdev *subdev, const struct nvkm_falcon *falcon,
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const char *fw)
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{
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void *acr_image;
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bool new_format;
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acr_image = nvkm_acr_load_firmware(subdev, fw, 0);
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if (IS_ERR(acr_image))
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return acr_image;
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/* detect the format to define how signature should be patched */
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switch (((u32 *)acr_image)[0]) {
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case 0x3b1d14f0:
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new_format = true;
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break;
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case 0x000010de:
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new_format = false;
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break;
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default:
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nvkm_error(subdev, "unknown header for HS blob %s\n", fw);
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return ERR_PTR(-EINVAL);
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}
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hs_ucode_patch_signature(falcon, acr_image, new_format);
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return acr_image;
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}
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@ -0,0 +1,81 @@
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/*
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* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __NVKM_SECBOOT_HS_UCODE_H__
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#define __NVKM_SECBOOT_HS_UCODE_H__
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#include <core/os.h>
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#include <core/subdev.h>
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struct nvkm_falcon;
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/**
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* struct hsf_fw_header - HS firmware descriptor
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* @sig_dbg_offset: offset of the debug signature
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* @sig_dbg_size: size of the debug signature
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* @sig_prod_offset: offset of the production signature
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* @sig_prod_size: size of the production signature
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* @patch_loc: offset of the offset (sic) of where the signature is
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* @patch_sig: offset of the offset (sic) to add to sig_*_offset
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* @hdr_offset: offset of the load header (see struct hs_load_header)
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* @hdr_size: size of above header
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*
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* This structure is embedded in the HS firmware image at
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* hs_bin_hdr.header_offset.
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*/
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struct hsf_fw_header {
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u32 sig_dbg_offset;
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u32 sig_dbg_size;
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u32 sig_prod_offset;
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u32 sig_prod_size;
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u32 patch_loc;
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u32 patch_sig;
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u32 hdr_offset;
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u32 hdr_size;
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};
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/**
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* struct hsf_load_header - HS firmware load header
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*/
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struct hsf_load_header {
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u32 non_sec_code_off;
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u32 non_sec_code_size;
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u32 data_dma_base;
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u32 data_size;
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u32 num_apps;
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/*
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* Organized as follows:
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* - app0_code_off
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* - app1_code_off
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* - ...
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* - appn_code_off
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* - app0_code_size
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* - app1_code_size
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* - ...
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*/
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u32 apps[0];
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};
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void *hs_ucode_load_blob(struct nvkm_subdev *, const struct nvkm_falcon *,
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const char *);
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#endif
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