ixgbe: register defines cleanup
Remove duplicates. Fix incorrect defines. Fix/Update comments. Fix whitespace. Add new register defines. Signed-off-by: Emil Tantilov <emil.s.tantilov@intel.com> Tested-by: Evan Swanson <evan.swanson@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
This commit is contained in:
Emil Tantilov
Jeff Kirsher
parent
50c022e793
commit
83dfde4053
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@ -36,9 +36,6 @@
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#define IXGBE_VFMAILBOX 0x002FC
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#define IXGBE_VFMBMEM 0x00200
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#define IXGBE_PFMAILBOX(x) (0x04B00 + (4 * x))
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#define IXGBE_PFMBMEM(vfn) (0x13000 + (64 * vfn))
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#define IXGBE_PFMAILBOX_STS 0x00000001 /* Initiate message send to VF */
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#define IXGBE_PFMAILBOX_ACK 0x00000002 /* Ack message recv'd from VF */
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#define IXGBE_PFMAILBOX_VFU 0x00000004 /* VF owns the mailbox buffer */
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@ -164,6 +164,9 @@
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(0x0D018 + ((_i - 64) * 0x40)))
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#define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \
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(0x0D028 + ((_i - 64) * 0x40)))
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#define IXGBE_RSCCTL(_i) (((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \
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(0x0D02C + ((_i - 64) * 0x40)))
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#define IXGBE_RSCDBU 0x03028
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#define IXGBE_RDDCC 0x02F20
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#define IXGBE_RXMEMWRAP 0x03190
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#define IXGBE_STARCTRL 0x03024
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@ -228,17 +231,23 @@
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#define IXGBE_VLVF(_i) (0x0F100 + ((_i) * 4)) /* 64 of these (0-63) */
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#define IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4)) /* 128 of these (0-127) */
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#define IXGBE_VMVIR(_i) (0x08000 + ((_i) * 4)) /* 64 of these (0-63) */
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#define IXGBE_VT_CTL 0x051B0
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#define IXGBE_VFRE(_i) (0x051E0 + ((_i) * 4))
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#define IXGBE_VFTE(_i) (0x08110 + ((_i) * 4))
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#define IXGBE_VMECM(_i) (0x08790 + ((_i) * 4))
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#define IXGBE_QDE 0x2F04
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#define IXGBE_VMOLR(_i) (0x0F000 + ((_i) * 4)) /* 64 total */
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#define IXGBE_UTA(_i) (0x0F400 + ((_i) * 4))
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#define IXGBE_VMRCTL(_i) (0x0F600 + ((_i) * 4))
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#define IXGBE_VMRVLAN(_i) (0x0F610 + ((_i) * 4))
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#define IXGBE_VMRVM(_i) (0x0F630 + ((_i) * 4))
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#define IXGBE_L34T_IMIR(_i) (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/
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#define IXGBE_VT_CTL 0x051B0
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#define IXGBE_PFMAILBOX(_i) (0x04B00 + (4 * (_i))) /* 64 total */
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#define IXGBE_PFMBMEM(_i) (0x13000 + (64 * (_i))) /* 64 Mailboxes, 16 DW each */
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#define IXGBE_PFMBICR(_i) (0x00710 + (4 * (_i))) /* 4 total */
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#define IXGBE_PFMBIMR(_i) (0x00720 + (4 * (_i))) /* 4 total */
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#define IXGBE_VFRE(_i) (0x051E0 + ((_i) * 4))
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#define IXGBE_VFTE(_i) (0x08110 + ((_i) * 4))
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#define IXGBE_VMECM(_i) (0x08790 + ((_i) * 4))
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#define IXGBE_QDE 0x2F04
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#define IXGBE_VMTXSW(_i) (0x05180 + ((_i) * 4)) /* 2 total */
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#define IXGBE_VMOLR(_i) (0x0F000 + ((_i) * 4)) /* 64 total */
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#define IXGBE_UTA(_i) (0x0F400 + ((_i) * 4))
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#define IXGBE_MRCTL(_i) (0x0F600 + ((_i) * 4))
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#define IXGBE_VMRVLAN(_i) (0x0F610 + ((_i) * 4))
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#define IXGBE_VMRVM(_i) (0x0F630 + ((_i) * 4))
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#define IXGBE_L34T_IMIR(_i) (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/
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#define IXGBE_RXFECCERR0 0x051B8
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#define IXGBE_LLITHRESH 0x0EC90
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#define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */
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#define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */
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@ -365,7 +374,7 @@
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#define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */
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#define IXGBE_WUFC_FLX_FILTERS 0x000F0000 /* Mask for 4 flex filters */
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#define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000 /* Mask for Ext. flex filters */
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#define IXGBE_WUFC_ALL_FILTERS 0x003F00FF /* Mask for all 6 wakeup filters*/
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#define IXGBE_WUFC_ALL_FILTERS 0x003F00FF /* Mask for all wakeup filters */
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#define IXGBE_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
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/* Wake Up Status */
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@ -407,7 +416,6 @@
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#define IXGBE_SECTXSTAT 0x08804
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#define IXGBE_SECTXBUFFAF 0x08808
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#define IXGBE_SECTXMINIFG 0x08810
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#define IXGBE_SECTXSTAT 0x08804
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#define IXGBE_SECRXCTRL 0x08D00
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#define IXGBE_SECRXSTAT 0x08D04
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@ -500,21 +508,6 @@
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#define IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE 0x4
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/* HW RSC registers */
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#define IXGBE_RSCCTL(_i) (((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \
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(0x0D02C + ((_i - 64) * 0x40)))
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#define IXGBE_RSCDBU 0x03028
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#define IXGBE_RSCCTL_RSCEN 0x01
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#define IXGBE_RSCCTL_MAXDESC_1 0x00
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#define IXGBE_RSCCTL_MAXDESC_4 0x04
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#define IXGBE_RSCCTL_MAXDESC_8 0x08
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#define IXGBE_RSCCTL_MAXDESC_16 0x0C
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#define IXGBE_RXDADV_RSCCNT_SHIFT 17
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#define IXGBE_GPIE_RSC_DELAY_SHIFT 11
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#define IXGBE_RXDADV_RSCCNT_MASK 0x001E0000
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#define IXGBE_RSCDBU_RSCACKDIS 0x00000080
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#define IXGBE_RDRXCTL_RSCFRSTSIZE 0x003E0000
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/* DCB registers */
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#define IXGBE_RTRPCS 0x02430
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#define IXGBE_RTTDCS 0x04900
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@ -523,6 +516,7 @@
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#define IXGBE_RTRUP2TC 0x03020
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#define IXGBE_RTTUP2TC 0x0C800
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#define IXGBE_RTRPT4C(_i) (0x02140 + ((_i) * 4)) /* 8 of these (0-7) */
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#define IXGBE_TXLLQ(_i) (0x082E0 + ((_i) * 4)) /* 4 of these (0-3) */
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#define IXGBE_RTRPT4S(_i) (0x02160 + ((_i) * 4)) /* 8 of these (0-7) */
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#define IXGBE_RTTDT2C(_i) (0x04910 + ((_i) * 4)) /* 8 of these (0-7) */
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#define IXGBE_RTTDT2S(_i) (0x04930 + ((_i) * 4)) /* 8 of these (0-7) */
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@ -541,7 +535,7 @@
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(IXGBE_RTTBCNRC_RF_DEC_MASK << IXGBE_RTTBCNRC_RF_INT_SHIFT)
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/* FCoE registers */
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/* FCoE DMA Context Registers */
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#define IXGBE_FCPTRL 0x02410 /* FC User Desc. PTR Low */
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#define IXGBE_FCPTRH 0x02414 /* FC USer Desc. PTR High */
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#define IXGBE_FCBUFF 0x02418 /* FC Buffer Control */
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@ -743,17 +737,10 @@
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#define IXGBE_PBACLR_82599 0x11068
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#define IXGBE_CIAA_82599 0x11088
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#define IXGBE_CIAD_82599 0x1108C
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#define IXGBE_PCIE_DIAG_0_82599 0x11090
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#define IXGBE_PCIE_DIAG_1_82599 0x11094
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#define IXGBE_PCIE_DIAG_2_82599 0x11098
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#define IXGBE_PCIE_DIAG_3_82599 0x1109C
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#define IXGBE_PCIE_DIAG_4_82599 0x110A0
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#define IXGBE_PCIE_DIAG_5_82599 0x110A4
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#define IXGBE_PCIE_DIAG_6_82599 0x110A8
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#define IXGBE_PCIE_DIAG_7_82599 0x110C0
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#define IXGBE_INTRPT_CSR_82599 0x110B0
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#define IXGBE_INTRPT_MASK_82599 0x110B8
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#define IXGBE_PICAUSE 0x110B0
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#define IXGBE_PIENA 0x110B8
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#define IXGBE_CDQ_MBR_82599 0x110B4
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#define IXGBE_PCIESPARE 0x110BC
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#define IXGBE_MISC_REG_82599 0x110F0
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#define IXGBE_ECC_CTRL_0_82599 0x11100
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#define IXGBE_ECC_CTRL_1_82599 0x11104
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@ -786,7 +773,19 @@
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#define IXGBE_SYSTIML 0x08C0C /* System time register Low - RO */
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#define IXGBE_SYSTIMH 0x08C10 /* System time register High - RO */
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#define IXGBE_TIMINCA 0x08C14 /* Increment attributes register - RW */
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#define IXGBE_RXUDP 0x08C1C /* Time Sync Rx UDP Port - RW */
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#define IXGBE_TIMADJL 0x08C18 /* Time Adjustment Offset register Low - RW */
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#define IXGBE_TIMADJH 0x08C1C /* Time Adjustment Offset register High - RW */
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#define IXGBE_TSAUXC 0x08C20 /* TimeSync Auxiliary Control register - RW */
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#define IXGBE_TRGTTIML0 0x08C24 /* Target Time Register 0 Low - RW */
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#define IXGBE_TRGTTIMH0 0x08C28 /* Target Time Register 0 High - RW */
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#define IXGBE_TRGTTIML1 0x08C2C /* Target Time Register 1 Low - RW */
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#define IXGBE_TRGTTIMH1 0x08C30 /* Target Time Register 1 High - RW */
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#define IXGBE_FREQOUT0 0x08C34 /* Frequency Out 0 Control register - RW */
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#define IXGBE_FREQOUT1 0x08C38 /* Frequency Out 1 Control register - RW */
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#define IXGBE_AUXSTMPL0 0x08C3C /* Auxiliary Time Stamp 0 register Low - RO */
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#define IXGBE_AUXSTMPH0 0x08C40 /* Auxiliary Time Stamp 0 register High - RO */
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#define IXGBE_AUXSTMPL1 0x08C44 /* Auxiliary Time Stamp 1 register Low - RO */
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#define IXGBE_AUXSTMPH1 0x08C48 /* Auxiliary Time Stamp 1 register High - RO */
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/* Diagnostic Registers */
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#define IXGBE_RDSTATCTL 0x02C20
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@ -830,8 +829,20 @@
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#define IXGBE_TXDATARDPTR(_i) (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/
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#define IXGBE_TXDESCRDPTR(_i) (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/
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#define IXGBE_PCIEECCCTL 0x1106C
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#define IXGBE_RXWRPTR(_i) (0x03100 + ((_i) * 4)) /* 8 of these 3100-310C*/
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#define IXGBE_RXUSED(_i) (0x03120 + ((_i) * 4)) /* 8 of these 3120-312C*/
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#define IXGBE_RXRDPTR(_i) (0x03140 + ((_i) * 4)) /* 8 of these 3140-314C*/
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#define IXGBE_RXRDWRPTR(_i) (0x03160 + ((_i) * 4)) /* 8 of these 3160-310C*/
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#define IXGBE_TXWRPTR(_i) (0x0C100 + ((_i) * 4)) /* 8 of these C100-C10C*/
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#define IXGBE_TXUSED(_i) (0x0C120 + ((_i) * 4)) /* 8 of these C120-C12C*/
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#define IXGBE_TXRDPTR(_i) (0x0C140 + ((_i) * 4)) /* 8 of these C140-C14C*/
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#define IXGBE_TXRDWRPTR(_i) (0x0C160 + ((_i) * 4)) /* 8 of these C160-C10C*/
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#define IXGBE_PCIEECCCTL0 0x11100
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#define IXGBE_PCIEECCCTL1 0x11104
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#define IXGBE_RXDBUECC 0x03F70
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#define IXGBE_TXDBUECC 0x0CF70
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#define IXGBE_RXDBUEST 0x03F74
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#define IXGBE_TXDBUEST 0x0CF74
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#define IXGBE_PBTXECC 0x0C300
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#define IXGBE_PBRXECC 0x03300
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#define IXGBE_GHECCR 0x110B0
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@ -872,6 +883,7 @@
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#define IXGBE_AUTOC3 0x042AC
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#define IXGBE_ANLP1 0x042B0
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#define IXGBE_ANLP2 0x042B4
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#define IXGBE_MACC 0x04330
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#define IXGBE_ATLASCTL 0x04800
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#define IXGBE_MMNGC 0x042D0
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#define IXGBE_ANLPNP1 0x042D4
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@ -884,14 +896,49 @@
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#define IXGBE_MPVC 0x04318
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#define IXGBE_SGMIIC 0x04314
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/* Statistics Registers */
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#define IXGBE_RXNFGPC 0x041B0
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#define IXGBE_RXNFGBCL 0x041B4
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#define IXGBE_RXNFGBCH 0x041B8
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#define IXGBE_RXDGPC 0x02F50
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#define IXGBE_RXDGBCL 0x02F54
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#define IXGBE_RXDGBCH 0x02F58
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#define IXGBE_RXDDGPC 0x02F5C
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#define IXGBE_RXDDGBCL 0x02F60
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#define IXGBE_RXDDGBCH 0x02F64
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#define IXGBE_RXLPBKGPC 0x02F68
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#define IXGBE_RXLPBKGBCL 0x02F6C
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#define IXGBE_RXLPBKGBCH 0x02F70
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#define IXGBE_RXDLPBKGPC 0x02F74
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#define IXGBE_RXDLPBKGBCL 0x02F78
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#define IXGBE_RXDLPBKGBCH 0x02F7C
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#define IXGBE_TXDGPC 0x087A0
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#define IXGBE_TXDGBCL 0x087A4
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#define IXGBE_TXDGBCH 0x087A8
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#define IXGBE_RXDSTATCTRL 0x02F40
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/* Copper Pond 2 link timeout */
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#define IXGBE_VALIDATE_LINK_READY_TIMEOUT 50
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/* Omer CORECTL */
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#define IXGBE_CORECTL 0x014F00
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/* BARCTRL */
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#define IXGBE_BARCTRL 0x110F4
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#define IXGBE_BARCTRL_FLSIZE 0x0700
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#define IXGBE_BARCTRL_CSRSIZE 0x2000
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#define IXGBE_BARCTRL 0x110F4
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#define IXGBE_BARCTRL_FLSIZE 0x0700
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#define IXGBE_BARCTRL_FLSIZE_SHIFT 8
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#define IXGBE_BARCTRL_CSRSIZE 0x2000
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/* RSCCTL Bit Masks */
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#define IXGBE_RSCCTL_RSCEN 0x01
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#define IXGBE_RSCCTL_MAXDESC_1 0x00
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#define IXGBE_RSCCTL_MAXDESC_4 0x04
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#define IXGBE_RSCCTL_MAXDESC_8 0x08
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#define IXGBE_RSCCTL_MAXDESC_16 0x0C
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/* RSCDBU Bit Masks */
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#define IXGBE_RSCDBU_RSCSMALDIS_MASK 0x0000007F
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#define IXGBE_RSCDBU_RSCACKDIS 0x00000080
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/* RDRXCTL Bit Masks */
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#define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000 /* Rx Desc Min Threshold Size */
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@ -899,6 +946,8 @@
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#define IXGBE_RDRXCTL_MVMEN 0x00000020
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#define IXGBE_RDRXCTL_DMAIDONE 0x00000008 /* DMA init cycle done */
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#define IXGBE_RDRXCTL_AGGDIS 0x00010000 /* Aggregation disable */
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#define IXGBE_RDRXCTL_RSCFRSTSIZE 0x003E0000 /* RSC First packet size */
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#define IXGBE_RDRXCTL_RSCLLIDIS 0x00800000 /* Disable RSC compl on LLI */
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#define IXGBE_RDRXCTL_RSCACKC 0x02000000 /* must set 1 when RSC enabled */
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#define IXGBE_RDRXCTL_FCOE_WRFIX 0x04000000 /* must set 1 when RSC enabled */
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@ -970,8 +1019,8 @@
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#define IXGBE_MSCA_OP_CODE_SHIFT 26 /* OP CODE shift */
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#define IXGBE_MSCA_ADDR_CYCLE 0x00000000 /* OP CODE 00 (addr cycle) */
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#define IXGBE_MSCA_WRITE 0x04000000 /* OP CODE 01 (write) */
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#define IXGBE_MSCA_READ 0x08000000 /* OP CODE 10 (read) */
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#define IXGBE_MSCA_READ_AUTOINC 0x0C000000 /* OP CODE 11 (read, auto inc)*/
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#define IXGBE_MSCA_READ 0x0C000000 /* OP CODE 11 (read) */
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#define IXGBE_MSCA_READ_AUTOINC 0x08000000 /* OP CODE 10 (read, auto inc)*/
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#define IXGBE_MSCA_ST_CODE_MASK 0x30000000 /* ST Code mask */
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#define IXGBE_MSCA_ST_CODE_SHIFT 28 /* ST Code shift */
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#define IXGBE_MSCA_NEW_PROTOCOL 0x00000000 /* ST CODE 00 (new protocol) */
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@ -1058,6 +1107,7 @@
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#define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */
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#define IXGBE_GPIE_EIAME 0x40000000
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#define IXGBE_GPIE_PBA_SUPPORT 0x80000000
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#define IXGBE_GPIE_RSC_DELAY_SHIFT 11
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#define IXGBE_GPIE_VTMODE_MASK 0x0000C000 /* VT Mode Mask */
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#define IXGBE_GPIE_VTMODE_16 0x00004000 /* 16 VFs 8 queues per VF */
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#define IXGBE_GPIE_VTMODE_32 0x00008000 /* 32 VFs 4 queues per VF */
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@ -1292,6 +1342,11 @@
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#define IXGBE_FTQF_POOL_SHIFT 8
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#define IXGBE_FTQF_5TUPLE_MASK_MASK 0x0000001F
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#define IXGBE_FTQF_5TUPLE_MASK_SHIFT 25
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#define IXGBE_FTQF_SOURCE_ADDR_MASK 0x1E
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#define IXGBE_FTQF_DEST_ADDR_MASK 0x1D
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#define IXGBE_FTQF_SOURCE_PORT_MASK 0x1B
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#define IXGBE_FTQF_DEST_PORT_MASK 0x17
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#define IXGBE_FTQF_PROTOCOL_COMP_MASK 0x0F
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#define IXGBE_FTQF_POOL_MASK_EN 0x40000000
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#define IXGBE_FTQF_QUEUE_ENABLE 0x80000000
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@ -1334,11 +1389,11 @@
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*
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* Current filters:
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* EAPOL 802.1x (0x888e): Filter 0
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* BCN (0x8904): Filter 1
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* FCoE (0x8906): Filter 2
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* 1588 (0x88f7): Filter 3
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* FIP (0x8914): Filter 4
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*/
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#define IXGBE_ETQF_FILTER_EAPOL 0
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#define IXGBE_ETQF_FILTER_BCN 1
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#define IXGBE_ETQF_FILTER_FCOE 2
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#define IXGBE_ETQF_FILTER_1588 3
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#define IXGBE_ETQF_FILTER_FIP 4
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@ -1449,6 +1504,11 @@
|
|||
#define IXGBE_AUTOC2_10G_XFI (0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
|
||||
#define IXGBE_AUTOC2_10G_SFI (0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
|
||||
|
||||
#define IXGBE_MACC_FLU 0x00000001
|
||||
#define IXGBE_MACC_FSV_10G 0x00030000
|
||||
#define IXGBE_MACC_FS 0x00040000
|
||||
#define IXGBE_MAC_RX2TX_LPBK 0x00000002
|
||||
|
||||
/* LINKS Bit Masks */
|
||||
#define IXGBE_LINKS_KX_AN_COMP 0x80000000
|
||||
#define IXGBE_LINKS_UP 0x40000000
|
||||
|
|
@ -1502,7 +1562,6 @@
|
|||
#define IXGBE_ANLP1_ASM_PAUSE 0x0800
|
||||
#define IXGBE_ANLP1_AN_STATE_MASK 0x000f0000
|
||||
|
||||
|
||||
/* SW Semaphore Register bitmasks */
|
||||
#define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
|
||||
#define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
|
||||
|
|
@ -1515,6 +1574,10 @@
|
|||
#define IXGBE_GSSR_PHY1_SM 0x0004
|
||||
#define IXGBE_GSSR_MAC_CSR_SM 0x0008
|
||||
#define IXGBE_GSSR_FLASH_SM 0x0010
|
||||
#define IXGBE_GSSR_SW_MNG_SM 0x0400
|
||||
|
||||
/* FW Status register bitmask */
|
||||
#define IXGBE_FWSTS_FWRI 0x00000200 /* Firmware Reset Indication */
|
||||
|
||||
/* EEC Register */
|
||||
#define IXGBE_EEC_SK 0x00000001 /* EEPROM Clock */
|
||||
|
|
@ -1535,6 +1598,7 @@
|
|||
/* EEPROM Addressing bits based on type (0-small, 1-large) */
|
||||
#define IXGBE_EEC_ADDR_SIZE 0x00000400
|
||||
#define IXGBE_EEC_SIZE 0x00007800 /* EEPROM Size */
|
||||
#define IXGBE_EERD_MAX_ADDR 0x00003FFF /* EERD alows 14 bits for addr. */
|
||||
|
||||
#define IXGBE_EEC_SIZE_SHIFT 11
|
||||
#define IXGBE_EEPROM_WORD_SIZE_SHIFT 6
|
||||
|
|
@ -1564,8 +1628,10 @@
|
|||
#define IXGBE_FW_PTR 0x0F
|
||||
#define IXGBE_PBANUM0_PTR 0x15
|
||||
#define IXGBE_PBANUM1_PTR 0x16
|
||||
#define IXGBE_DEVICE_CAPS 0x2C
|
||||
#define IXGBE_FREE_SPACE_PTR 0X3E
|
||||
#define IXGBE_SAN_MAC_ADDR_PTR 0x28
|
||||
#define IXGBE_DEVICE_CAPS 0x2C
|
||||
#define IXGBE_SERIAL_NUMBER_MAC_ADDR 0x11
|
||||
#define IXGBE_PCIE_MSIX_82599_CAPS 0x72
|
||||
#define IXGBE_PCIE_MSIX_82598_CAPS 0x62
|
||||
|
||||
|
|
@ -1630,9 +1696,12 @@
|
|||
#define IXGBE_FW_LESM_STATE_1 0x1
|
||||
#define IXGBE_FW_LESM_STATE_ENABLED 0x8000 /* LESM Enable bit */
|
||||
#define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4
|
||||
#define IXGBE_FW_PATCH_VERSION_4 0x7
|
||||
|
||||
/* Alternative SAN MAC Address Block */
|
||||
#define IXGBE_FW_PATCH_VERSION_4 0x7
|
||||
#define IXGBE_FCOE_IBA_CAPS_BLK_PTR 0x33 /* iSCSI/FCOE block */
|
||||
#define IXGBE_FCOE_IBA_CAPS_FCOE 0x20 /* FCOE flags */
|
||||
#define IXGBE_ISCSI_FCOE_BLK_PTR 0x17 /* iSCSI/FCOE block */
|
||||
#define IXGBE_ISCSI_FCOE_FLAGS_OFFSET 0x0 /* FCOE flags */
|
||||
#define IXGBE_ISCSI_FCOE_FLAGS_ENABLE 0x1 /* FCOE flags enable bit */
|
||||
#define IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR 0x27 /* Alt. SAN MAC block */
|
||||
#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET 0x0 /* Alt. SAN MAC capability */
|
||||
#define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET 0x1 /* Alt. SAN MAC 0 offset */
|
||||
|
|
@ -1697,6 +1766,7 @@
|
|||
/* Transmit Config masks */
|
||||
#define IXGBE_TXDCTL_ENABLE 0x02000000 /* Enable specific Tx Queue */
|
||||
#define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. write-back flushing */
|
||||
#define IXGBE_TXDCTL_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */
|
||||
/* Enable short packet padding to 64 bytes */
|
||||
#define IXGBE_TX_PAD_ENABLE 0x00000400
|
||||
#define IXGBE_JUMBO_FRAME_ENABLE 0x00000004 /* Allow jumbo frames */
|
||||
|
|
@ -1710,9 +1780,9 @@
|
|||
#define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */
|
||||
#define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Descriptor Monitor Bypass */
|
||||
#define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */
|
||||
#define IXGBE_RXDCTL_VME 0x40000000 /* VLAN mode enable */
|
||||
#define IXGBE_RXDCTL_RLPMLMASK 0x00003FFF /* Only supported on the X540 */
|
||||
#define IXGBE_RXDCTL_RLPML_EN 0x00008000
|
||||
#define IXGBE_RXDCTL_VME 0x40000000 /* VLAN mode enable */
|
||||
|
||||
#define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */
|
||||
#define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/
|
||||
|
|
@ -1870,6 +1940,8 @@
|
|||
#define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0
|
||||
#define IXGBE_RXDADV_PKTTYPE_MASK_EX 0x0001FFF0
|
||||
#define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0
|
||||
#define IXGBE_RXDADV_RSCCNT_MASK 0x001E0000
|
||||
#define IXGBE_RXDADV_RSCCNT_SHIFT 17
|
||||
#define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5
|
||||
#define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000
|
||||
#define IXGBE_RXDADV_SPH 0x8000
|
||||
|
|
@ -1945,15 +2017,6 @@
|
|||
#define IXGBE_VFLRE(_i) (((_i & 1) ? 0x001C0 : 0x00600))
|
||||
#define IXGBE_VFLREC(_i) (0x00700 + (_i * 4))
|
||||
|
||||
/* Little Endian defines */
|
||||
#ifndef __le32
|
||||
#define __le32 u32
|
||||
#endif
|
||||
#ifndef __le64
|
||||
#define __le64 u64
|
||||
|
||||
#endif
|
||||
|
||||
enum ixgbe_fdir_pballoc_type {
|
||||
IXGBE_FDIR_PBALLOC_64K = 0,
|
||||
IXGBE_FDIR_PBALLOC_128K,
|
||||
|
|
@ -2152,8 +2215,6 @@ typedef u32 ixgbe_link_speed;
|
|||
IXGBE_LINK_SPEED_1GB_FULL | \
|
||||
IXGBE_LINK_SPEED_10GB_FULL)
|
||||
|
||||
#define IXGBE_PCIE_DEV_CTRL_2 0xC8
|
||||
#define PCIE_COMPL_TO_VALUE 0x05
|
||||
|
||||
/* Physical layer type */
|
||||
typedef u32 ixgbe_physical_layer;
|
||||
|
|
|
|||
Loading…
Reference in New Issue