spi: Add support for Renesas CSI
The RZ/V2M SoC comes with the Clocked Serial Interface (CSI) IP, which is a master/slave SPI controller. This commit adds a driver to support CSI master mode. Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Link: https://lore.kernel.org/r/Message-Id: <20230622113341.657842-4-fabrizio.castro.jz@renesas.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Fabrizio Castro
Mark Brown
parent
14dde0746e
commit
83c624d884
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@ -825,6 +825,12 @@ config SPI_RSPI
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help
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SPI driver for Renesas RSPI and QSPI blocks.
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config SPI_RZV2M_CSI
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tristate "Renesas RZV2M CSI controller"
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depends on ARCH_RENESAS || COMPILE_TEST
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help
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SPI driver for Renesas RZ/V2M Clocked Serial Interface (CSI)
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config SPI_QCOM_QSPI
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tristate "QTI QSPI controller"
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depends on ARCH_QCOM || COMPILE_TEST
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@ -113,6 +113,7 @@ obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o
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obj-$(CONFIG_MACH_REALTEK_RTL) += spi-realtek-rtl.o
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obj-$(CONFIG_SPI_RPCIF) += spi-rpc-if.o
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obj-$(CONFIG_SPI_RSPI) += spi-rspi.o
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obj-$(CONFIG_SPI_RZV2M_CSI) += spi-rzv2m-csi.o
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obj-$(CONFIG_SPI_S3C64XX) += spi-s3c64xx.o
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obj-$(CONFIG_SPI_SC18IS602) += spi-sc18is602.o
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obj-$(CONFIG_SPI_SH) += spi-sh.o
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@ -0,0 +1,667 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Renesas RZ/V2M Clocked Serial Interface (CSI) driver
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*
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* Copyright (C) 2023 Renesas Electronics Corporation
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*/
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#include <linux/clk.h>
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#include <linux/count_zeros.h>
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#include <linux/interrupt.h>
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#include <linux/iopoll.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <linux/spi/spi.h>
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/* Registers */
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#define CSI_MODE 0x00 /* CSI mode control */
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#define CSI_CLKSEL 0x04 /* CSI clock select */
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#define CSI_CNT 0x08 /* CSI control */
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#define CSI_INT 0x0C /* CSI interrupt status */
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#define CSI_IFIFOL 0x10 /* CSI receive FIFO level display */
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#define CSI_OFIFOL 0x14 /* CSI transmit FIFO level display */
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#define CSI_IFIFO 0x18 /* CSI receive window */
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#define CSI_OFIFO 0x1C /* CSI transmit window */
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#define CSI_FIFOTRG 0x20 /* CSI FIFO trigger level */
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/* CSI_MODE */
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#define CSI_MODE_CSIE BIT(7)
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#define CSI_MODE_TRMD BIT(6)
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#define CSI_MODE_CCL BIT(5)
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#define CSI_MODE_DIR BIT(4)
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#define CSI_MODE_CSOT BIT(0)
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#define CSI_MODE_SETUP 0x00000040
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/* CSI_CLKSEL */
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#define CSI_CLKSEL_CKP BIT(17)
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#define CSI_CLKSEL_DAP BIT(16)
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#define CSI_CLKSEL_SLAVE BIT(15)
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#define CSI_CLKSEL_CKS GENMASK(14, 1)
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/* CSI_CNT */
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#define CSI_CNT_CSIRST BIT(28)
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#define CSI_CNT_R_TRGEN BIT(19)
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#define CSI_CNT_UNDER_E BIT(13)
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#define CSI_CNT_OVERF_E BIT(12)
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#define CSI_CNT_TREND_E BIT(9)
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#define CSI_CNT_CSIEND_E BIT(8)
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#define CSI_CNT_T_TRGR_E BIT(4)
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#define CSI_CNT_R_TRGR_E BIT(0)
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/* CSI_INT */
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#define CSI_INT_UNDER BIT(13)
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#define CSI_INT_OVERF BIT(12)
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#define CSI_INT_TREND BIT(9)
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#define CSI_INT_CSIEND BIT(8)
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#define CSI_INT_T_TRGR BIT(4)
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#define CSI_INT_R_TRGR BIT(0)
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/* CSI_FIFOTRG */
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#define CSI_FIFOTRG_R_TRG GENMASK(2, 0)
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#define CSI_FIFO_SIZE_BYTES 32
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#define CSI_FIFO_HALF_SIZE 16
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#define CSI_EN_DIS_TIMEOUT_US 100
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#define CSI_CKS_MAX 0x3FFF
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#define UNDERRUN_ERROR BIT(0)
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#define OVERFLOW_ERROR BIT(1)
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#define TX_TIMEOUT_ERROR BIT(2)
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#define RX_TIMEOUT_ERROR BIT(3)
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#define CSI_MAX_SPI_SCKO 8000000
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struct rzv2m_csi_priv {
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void __iomem *base;
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struct clk *csiclk;
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struct clk *pclk;
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struct device *dev;
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struct spi_controller *controller;
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const u8 *txbuf;
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u8 *rxbuf;
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int buffer_len;
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int bytes_sent;
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int bytes_received;
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int bytes_to_transfer;
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int words_to_transfer;
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unsigned char bytes_per_word;
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wait_queue_head_t wait;
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u8 errors;
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u32 status;
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};
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static const unsigned char x_trg[] = {
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0, 1, 1, 2, 2, 2, 2, 3,
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3, 3, 3, 3, 3, 3, 3, 4,
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4, 4, 4, 4, 4, 4, 4, 4,
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4, 4, 4, 4, 4, 4, 4, 5
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};
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static const unsigned char x_trg_words[] = {
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1, 2, 2, 4, 4, 4, 4, 8,
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8, 8, 8, 8, 8, 8, 8, 16,
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16, 16, 16, 16, 16, 16, 16, 16,
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16, 16, 16, 16, 16, 16, 16, 32
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};
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static void rzv2m_csi_reg_write_bit(const struct rzv2m_csi_priv *csi,
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int reg_offs, int bit_mask, u32 value)
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{
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int nr_zeros;
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u32 tmp;
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nr_zeros = count_trailing_zeros(bit_mask);
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value <<= nr_zeros;
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tmp = (readl(csi->base + reg_offs) & ~bit_mask) | value;
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writel(tmp, csi->base + reg_offs);
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}
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static int rzv2m_csi_sw_reset(struct rzv2m_csi_priv *csi, int assert)
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{
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u32 reg;
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rzv2m_csi_reg_write_bit(csi, CSI_CNT, CSI_CNT_CSIRST, assert);
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if (assert) {
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return readl_poll_timeout(csi->base + CSI_MODE, reg,
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!(reg & CSI_MODE_CSOT), 0,
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CSI_EN_DIS_TIMEOUT_US);
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}
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return 0;
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}
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static int rzv2m_csi_start_stop_operation(const struct rzv2m_csi_priv *csi,
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int enable, bool wait)
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{
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u32 reg;
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rzv2m_csi_reg_write_bit(csi, CSI_MODE, CSI_MODE_CSIE, enable);
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if (!enable && wait)
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return readl_poll_timeout(csi->base + CSI_MODE, reg,
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!(reg & CSI_MODE_CSOT), 0,
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CSI_EN_DIS_TIMEOUT_US);
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return 0;
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}
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static int rzv2m_csi_fill_txfifo(struct rzv2m_csi_priv *csi)
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{
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int i;
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if (readl(csi->base + CSI_OFIFOL))
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return -EIO;
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if (csi->bytes_per_word == 2) {
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u16 *buf = (u16 *)csi->txbuf;
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for (i = 0; i < csi->words_to_transfer; i++)
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writel(buf[i], csi->base + CSI_OFIFO);
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} else {
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u8 *buf = (u8 *)csi->txbuf;
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for (i = 0; i < csi->words_to_transfer; i++)
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writel(buf[i], csi->base + CSI_OFIFO);
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}
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csi->txbuf += csi->bytes_to_transfer;
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csi->bytes_sent += csi->bytes_to_transfer;
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return 0;
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}
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static int rzv2m_csi_read_rxfifo(struct rzv2m_csi_priv *csi)
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{
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int i;
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if (readl(csi->base + CSI_IFIFOL) != csi->bytes_to_transfer)
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return -EIO;
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if (csi->bytes_per_word == 2) {
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u16 *buf = (u16 *)csi->rxbuf;
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for (i = 0; i < csi->words_to_transfer; i++)
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buf[i] = (u16)readl(csi->base + CSI_IFIFO);
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} else {
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u8 *buf = (u8 *)csi->rxbuf;
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for (i = 0; i < csi->words_to_transfer; i++)
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buf[i] = (u8)readl(csi->base + CSI_IFIFO);
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}
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csi->rxbuf += csi->bytes_to_transfer;
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csi->bytes_received += csi->bytes_to_transfer;
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return 0;
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}
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static inline void rzv2m_csi_calc_current_transfer(struct rzv2m_csi_priv *csi)
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{
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int bytes_transferred = max_t(int, csi->bytes_received, csi->bytes_sent);
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int bytes_remaining = csi->buffer_len - bytes_transferred;
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int to_transfer;
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if (csi->txbuf)
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/*
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* Leaving a little bit of headroom in the FIFOs makes it very
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* hard to raise an overflow error (which is only possible
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* when IP transmits and receives at the same time).
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*/
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to_transfer = min_t(int, CSI_FIFO_HALF_SIZE, bytes_remaining);
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else
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to_transfer = min_t(int, CSI_FIFO_SIZE_BYTES, bytes_remaining);
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if (csi->bytes_per_word == 2)
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to_transfer >>= 1;
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/*
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* We can only choose a trigger level from a predefined set of values.
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* This will pick a value that is the greatest possible integer that's
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* less than or equal to the number of bytes we need to transfer.
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* This may result in multiple smaller transfers.
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*/
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csi->words_to_transfer = x_trg_words[to_transfer - 1];
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if (csi->bytes_per_word == 2)
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csi->bytes_to_transfer = csi->words_to_transfer << 1;
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else
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csi->bytes_to_transfer = csi->words_to_transfer;
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}
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static inline void rzv2m_csi_set_rx_fifo_trigger_level(struct rzv2m_csi_priv *csi)
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{
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rzv2m_csi_reg_write_bit(csi, CSI_FIFOTRG, CSI_FIFOTRG_R_TRG,
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x_trg[csi->words_to_transfer - 1]);
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}
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static inline void rzv2m_csi_enable_rx_trigger(struct rzv2m_csi_priv *csi,
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bool enable)
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{
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rzv2m_csi_reg_write_bit(csi, CSI_CNT, CSI_CNT_R_TRGEN, enable);
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}
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static void rzv2m_csi_disable_irqs(const struct rzv2m_csi_priv *csi,
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u32 enable_bits)
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{
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u32 cnt = readl(csi->base + CSI_CNT);
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writel(cnt & ~enable_bits, csi->base + CSI_CNT);
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}
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static void rzv2m_csi_disable_all_irqs(struct rzv2m_csi_priv *csi)
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{
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rzv2m_csi_disable_irqs(csi, CSI_CNT_R_TRGR_E | CSI_CNT_T_TRGR_E |
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CSI_CNT_CSIEND_E | CSI_CNT_TREND_E |
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CSI_CNT_OVERF_E | CSI_CNT_UNDER_E);
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}
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static inline void rzv2m_csi_clear_irqs(struct rzv2m_csi_priv *csi, u32 irqs)
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{
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writel(irqs, csi->base + CSI_INT);
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}
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static void rzv2m_csi_clear_all_irqs(struct rzv2m_csi_priv *csi)
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{
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rzv2m_csi_clear_irqs(csi, CSI_INT_UNDER | CSI_INT_OVERF |
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CSI_INT_TREND | CSI_INT_CSIEND | CSI_INT_T_TRGR |
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CSI_INT_R_TRGR);
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}
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static void rzv2m_csi_enable_irqs(struct rzv2m_csi_priv *csi, u32 enable_bits)
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{
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u32 cnt = readl(csi->base + CSI_CNT);
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writel(cnt | enable_bits, csi->base + CSI_CNT);
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}
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static int rzv2m_csi_wait_for_interrupt(struct rzv2m_csi_priv *csi,
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u32 wait_mask, u32 enable_bits)
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{
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int ret;
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rzv2m_csi_enable_irqs(csi, enable_bits);
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ret = wait_event_timeout(csi->wait,
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((csi->status & wait_mask) == wait_mask) ||
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csi->errors, HZ);
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rzv2m_csi_disable_irqs(csi, enable_bits);
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if (csi->errors)
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return -EIO;
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if (!ret)
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return -ETIMEDOUT;
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return 0;
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}
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static int rzv2m_csi_wait_for_tx_empty(struct rzv2m_csi_priv *csi)
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{
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int ret;
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if (readl(csi->base + CSI_OFIFOL) == 0)
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return 0;
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ret = rzv2m_csi_wait_for_interrupt(csi, CSI_INT_TREND, CSI_CNT_TREND_E);
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if (ret == -ETIMEDOUT)
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csi->errors |= TX_TIMEOUT_ERROR;
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return ret;
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}
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static inline int rzv2m_csi_wait_for_rx_ready(struct rzv2m_csi_priv *csi)
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{
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int ret;
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if (readl(csi->base + CSI_IFIFOL) == csi->bytes_to_transfer)
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return 0;
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ret = rzv2m_csi_wait_for_interrupt(csi, CSI_INT_R_TRGR,
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CSI_CNT_R_TRGR_E);
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if (ret == -ETIMEDOUT)
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csi->errors |= RX_TIMEOUT_ERROR;
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return ret;
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}
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static irqreturn_t rzv2m_csi_irq_handler(int irq, void *data)
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{
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struct rzv2m_csi_priv *csi = (struct rzv2m_csi_priv *)data;
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csi->status = readl(csi->base + CSI_INT);
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rzv2m_csi_disable_irqs(csi, csi->status);
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if (csi->status & CSI_INT_OVERF)
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csi->errors |= OVERFLOW_ERROR;
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if (csi->status & CSI_INT_UNDER)
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csi->errors |= UNDERRUN_ERROR;
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wake_up(&csi->wait);
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return IRQ_HANDLED;
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}
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static void rzv2m_csi_setup_clock(struct rzv2m_csi_priv *csi, u32 spi_hz)
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{
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unsigned long csiclk_rate = clk_get_rate(csi->csiclk);
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unsigned long pclk_rate = clk_get_rate(csi->pclk);
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unsigned long csiclk_rate_limit = pclk_rate >> 1;
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u32 cks;
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/*
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* There is a restriction on the frequency of CSICLK, it has to be <=
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* PCLK / 2.
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*/
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if (csiclk_rate > csiclk_rate_limit) {
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clk_set_rate(csi->csiclk, csiclk_rate >> 1);
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csiclk_rate = clk_get_rate(csi->csiclk);
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} else if ((csiclk_rate << 1) <= csiclk_rate_limit) {
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clk_set_rate(csi->csiclk, csiclk_rate << 1);
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csiclk_rate = clk_get_rate(csi->csiclk);
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}
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spi_hz = spi_hz > CSI_MAX_SPI_SCKO ? CSI_MAX_SPI_SCKO : spi_hz;
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cks = DIV_ROUND_UP(csiclk_rate, spi_hz << 1);
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if (cks > CSI_CKS_MAX)
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cks = CSI_CKS_MAX;
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dev_dbg(csi->dev, "SPI clk rate is %ldHz\n", csiclk_rate / (cks << 1));
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rzv2m_csi_reg_write_bit(csi, CSI_CLKSEL, CSI_CLKSEL_CKS, cks);
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}
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static void rzv2m_csi_setup_operating_mode(struct rzv2m_csi_priv *csi,
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struct spi_transfer *t)
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{
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if (t->rx_buf && !t->tx_buf)
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/* Reception-only mode */
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rzv2m_csi_reg_write_bit(csi, CSI_MODE, CSI_MODE_TRMD, 0);
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else
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/* Send and receive mode */
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rzv2m_csi_reg_write_bit(csi, CSI_MODE, CSI_MODE_TRMD, 1);
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csi->bytes_per_word = t->bits_per_word / 8;
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rzv2m_csi_reg_write_bit(csi, CSI_MODE, CSI_MODE_CCL,
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csi->bytes_per_word == 2);
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}
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static int rzv2m_csi_setup(struct spi_device *spi)
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{
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struct rzv2m_csi_priv *csi = spi_controller_get_devdata(spi->controller);
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int ret;
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||||
|
||||
rzv2m_csi_sw_reset(csi, 0);
|
||||
|
||||
writel(CSI_MODE_SETUP, csi->base + CSI_MODE);
|
||||
|
||||
/* Setup clock polarity and phase timing */
|
||||
rzv2m_csi_reg_write_bit(csi, CSI_CLKSEL, CSI_CLKSEL_CKP,
|
||||
!(spi->mode & SPI_CPOL));
|
||||
rzv2m_csi_reg_write_bit(csi, CSI_CLKSEL, CSI_CLKSEL_DAP,
|
||||
!(spi->mode & SPI_CPHA));
|
||||
|
||||
/* Setup serial data order */
|
||||
rzv2m_csi_reg_write_bit(csi, CSI_MODE, CSI_MODE_DIR,
|
||||
!!(spi->mode & SPI_LSB_FIRST));
|
||||
|
||||
/* Set the operation mode as master */
|
||||
rzv2m_csi_reg_write_bit(csi, CSI_CLKSEL, CSI_CLKSEL_SLAVE, 0);
|
||||
|
||||
/* Give the IP a SW reset */
|
||||
ret = rzv2m_csi_sw_reset(csi, 1);
|
||||
if (ret)
|
||||
return ret;
|
||||
rzv2m_csi_sw_reset(csi, 0);
|
||||
|
||||
/*
|
||||
* We need to enable the communication so that the clock will settle
|
||||
* for the right polarity before enabling the CS.
|
||||
*/
|
||||
rzv2m_csi_start_stop_operation(csi, 1, false);
|
||||
udelay(10);
|
||||
rzv2m_csi_start_stop_operation(csi, 0, false);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rzv2m_csi_pio_transfer(struct rzv2m_csi_priv *csi)
|
||||
{
|
||||
bool tx_completed = csi->txbuf ? false : true;
|
||||
bool rx_completed = csi->rxbuf ? false : true;
|
||||
int ret = 0;
|
||||
|
||||
/* Make sure the TX FIFO is empty */
|
||||
writel(0, csi->base + CSI_OFIFOL);
|
||||
|
||||
csi->bytes_sent = 0;
|
||||
csi->bytes_received = 0;
|
||||
csi->errors = 0;
|
||||
|
||||
rzv2m_csi_disable_all_irqs(csi);
|
||||
rzv2m_csi_clear_all_irqs(csi);
|
||||
rzv2m_csi_enable_rx_trigger(csi, true);
|
||||
|
||||
while (!tx_completed || !rx_completed) {
|
||||
/*
|
||||
* Decide how many words we are going to transfer during
|
||||
* this cycle (for both TX and RX), then set the RX FIFO trigger
|
||||
* level accordingly. No need to set a trigger level for the
|
||||
* TX FIFO, as this IP comes with an interrupt that fires when
|
||||
* the TX FIFO is empty.
|
||||
*/
|
||||
rzv2m_csi_calc_current_transfer(csi);
|
||||
rzv2m_csi_set_rx_fifo_trigger_level(csi);
|
||||
|
||||
rzv2m_csi_enable_irqs(csi, CSI_INT_OVERF | CSI_INT_UNDER);
|
||||
|
||||
/* Make sure the RX FIFO is empty */
|
||||
writel(0, csi->base + CSI_IFIFOL);
|
||||
|
||||
writel(readl(csi->base + CSI_INT), csi->base + CSI_INT);
|
||||
csi->status = 0;
|
||||
|
||||
rzv2m_csi_start_stop_operation(csi, 1, false);
|
||||
|
||||
/* TX */
|
||||
if (csi->txbuf) {
|
||||
ret = rzv2m_csi_fill_txfifo(csi);
|
||||
if (ret)
|
||||
break;
|
||||
|
||||
ret = rzv2m_csi_wait_for_tx_empty(csi);
|
||||
if (ret)
|
||||
break;
|
||||
|
||||
if (csi->bytes_sent == csi->buffer_len)
|
||||
tx_completed = true;
|
||||
}
|
||||
|
||||
/*
|
||||
* Make sure the RX FIFO contains the desired number of words.
|
||||
* We then either flush its content, or we copy it onto
|
||||
* csi->rxbuf.
|
||||
*/
|
||||
ret = rzv2m_csi_wait_for_rx_ready(csi);
|
||||
if (ret)
|
||||
break;
|
||||
|
||||
/* RX */
|
||||
if (csi->rxbuf) {
|
||||
rzv2m_csi_start_stop_operation(csi, 0, false);
|
||||
|
||||
ret = rzv2m_csi_read_rxfifo(csi);
|
||||
if (ret)
|
||||
break;
|
||||
|
||||
if (csi->bytes_received == csi->buffer_len)
|
||||
rx_completed = true;
|
||||
}
|
||||
|
||||
ret = rzv2m_csi_start_stop_operation(csi, 0, true);
|
||||
if (ret)
|
||||
goto pio_quit;
|
||||
|
||||
if (csi->errors) {
|
||||
ret = -EIO;
|
||||
goto pio_quit;
|
||||
}
|
||||
}
|
||||
|
||||
rzv2m_csi_start_stop_operation(csi, 0, true);
|
||||
|
||||
pio_quit:
|
||||
rzv2m_csi_disable_all_irqs(csi);
|
||||
rzv2m_csi_enable_rx_trigger(csi, false);
|
||||
rzv2m_csi_clear_all_irqs(csi);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rzv2m_csi_transfer_one(struct spi_controller *controller,
|
||||
struct spi_device *spi,
|
||||
struct spi_transfer *transfer)
|
||||
{
|
||||
struct rzv2m_csi_priv *csi = spi_controller_get_devdata(controller);
|
||||
struct device *dev = csi->dev;
|
||||
int ret;
|
||||
|
||||
csi->txbuf = transfer->tx_buf;
|
||||
csi->rxbuf = transfer->rx_buf;
|
||||
csi->buffer_len = transfer->len;
|
||||
|
||||
rzv2m_csi_setup_operating_mode(csi, transfer);
|
||||
|
||||
rzv2m_csi_setup_clock(csi, transfer->speed_hz);
|
||||
|
||||
ret = rzv2m_csi_pio_transfer(csi);
|
||||
if (ret) {
|
||||
if (csi->errors & UNDERRUN_ERROR)
|
||||
dev_err(dev, "Underrun error\n");
|
||||
if (csi->errors & OVERFLOW_ERROR)
|
||||
dev_err(dev, "Overflow error\n");
|
||||
if (csi->errors & TX_TIMEOUT_ERROR)
|
||||
dev_err(dev, "TX timeout error\n");
|
||||
if (csi->errors & RX_TIMEOUT_ERROR)
|
||||
dev_err(dev, "RX timeout error\n");
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rzv2m_csi_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct spi_controller *controller;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct rzv2m_csi_priv *csi;
|
||||
struct reset_control *rstc;
|
||||
int irq;
|
||||
int ret;
|
||||
|
||||
controller = devm_spi_alloc_master(dev, sizeof(*csi));
|
||||
if (!controller)
|
||||
return -ENOMEM;
|
||||
|
||||
csi = spi_controller_get_devdata(controller);
|
||||
platform_set_drvdata(pdev, csi);
|
||||
|
||||
csi->dev = dev;
|
||||
csi->controller = controller;
|
||||
|
||||
csi->base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(csi->base))
|
||||
return PTR_ERR(csi->base);
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0)
|
||||
return irq;
|
||||
|
||||
csi->csiclk = devm_clk_get(dev, "csiclk");
|
||||
if (IS_ERR(csi->csiclk))
|
||||
return dev_err_probe(dev, PTR_ERR(csi->csiclk),
|
||||
"could not get csiclk\n");
|
||||
|
||||
csi->pclk = devm_clk_get(dev, "pclk");
|
||||
if (IS_ERR(csi->pclk))
|
||||
return dev_err_probe(dev, PTR_ERR(csi->pclk),
|
||||
"could not get pclk\n");
|
||||
|
||||
rstc = devm_reset_control_get_shared(dev, NULL);
|
||||
if (IS_ERR(rstc))
|
||||
return dev_err_probe(dev, PTR_ERR(rstc), "Missing reset ctrl\n");
|
||||
|
||||
init_waitqueue_head(&csi->wait);
|
||||
|
||||
controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
|
||||
controller->dev.of_node = pdev->dev.of_node;
|
||||
controller->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8);
|
||||
controller->setup = rzv2m_csi_setup;
|
||||
controller->transfer_one = rzv2m_csi_transfer_one;
|
||||
controller->use_gpio_descriptors = true;
|
||||
|
||||
ret = devm_request_irq(dev, irq, rzv2m_csi_irq_handler, 0,
|
||||
dev_name(dev), csi);
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret, "cannot request IRQ\n");
|
||||
|
||||
/*
|
||||
* The reset also affects other HW that is not under the control
|
||||
* of Linux. Therefore, all we can do is make sure the reset is
|
||||
* deasserted.
|
||||
*/
|
||||
reset_control_deassert(rstc);
|
||||
|
||||
/* Make sure the IP is in SW reset state */
|
||||
ret = rzv2m_csi_sw_reset(csi, 1);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = clk_prepare_enable(csi->csiclk);
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret, "could not enable csiclk\n");
|
||||
|
||||
ret = spi_register_controller(controller);
|
||||
if (ret) {
|
||||
clk_disable_unprepare(csi->csiclk);
|
||||
return dev_err_probe(dev, ret, "register controller failed\n");
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rzv2m_csi_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct rzv2m_csi_priv *csi = platform_get_drvdata(pdev);
|
||||
|
||||
spi_unregister_controller(csi->controller);
|
||||
rzv2m_csi_sw_reset(csi, 1);
|
||||
clk_disable_unprepare(csi->csiclk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id rzv2m_csi_match[] = {
|
||||
{ .compatible = "renesas,rzv2m-csi" },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, rzv2m_csi_match);
|
||||
|
||||
static struct platform_driver rzv2m_csi_drv = {
|
||||
.probe = rzv2m_csi_probe,
|
||||
.remove = rzv2m_csi_remove,
|
||||
.driver = {
|
||||
.name = "rzv2m_csi",
|
||||
.of_match_table = rzv2m_csi_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(rzv2m_csi_drv);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_AUTHOR("Fabrizio Castro <castro.fabrizio.jz@renesas.com>");
|
||||
MODULE_DESCRIPTION("Clocked Serial Interface Driver");
|
||||
Loading…
Reference in New Issue