clk: mediatek: mt7622: Move infracfg to clk-mt7622-infracfg.c
The infracfg driver cannot be converted to clk_mtk_simple_probe() as it registers cpumuxes, which is not supported on the common probing mechanism: for this reason, move it to its own file. While at it, also convert it to be a platform driver instead; to do so, also add a .remove() callback for this driver. During the conversion, error handling was added to the infracfg probe function. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-27-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
AngeloGioacchino Del Regno
Stephen Boyd
parent
c50e2ea650
commit
838b86331c
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@ -46,7 +46,8 @@ obj-$(CONFIG_COMMON_CLK_MT2712_MFGCFG) += clk-mt2712-mfg.o
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obj-$(CONFIG_COMMON_CLK_MT2712_MMSYS) += clk-mt2712-mm.o
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obj-$(CONFIG_COMMON_CLK_MT2712_VDECSYS) += clk-mt2712-vdec.o
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obj-$(CONFIG_COMMON_CLK_MT2712_VENCSYS) += clk-mt2712-venc.o
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obj-$(CONFIG_COMMON_CLK_MT7622) += clk-mt7622-apmixedsys.o clk-mt7622.o
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obj-$(CONFIG_COMMON_CLK_MT7622) += clk-mt7622-apmixedsys.o clk-mt7622.o \
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clk-mt7622-infracfg.o
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obj-$(CONFIG_COMMON_CLK_MT7622_ETHSYS) += clk-mt7622-eth.o
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obj-$(CONFIG_COMMON_CLK_MT7622_HIFSYS) += clk-mt7622-hif.o
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obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) += clk-mt7622-aud.o
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@ -0,0 +1,127 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2017 MediaTek Inc.
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* Copyright (c) 2023 Collabora, Ltd.
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* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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*/
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#include <dt-bindings/clock/mt7622-clk.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include "clk-cpumux.h"
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#include "clk-gate.h"
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#include "clk-mtk.h"
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#include "reset.h"
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#define GATE_INFRA(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
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static const struct mtk_gate_regs infra_cg_regs = {
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.set_ofs = 0x40,
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.clr_ofs = 0x44,
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.sta_ofs = 0x48,
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};
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static const char * const infra_mux1_parents[] = {
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"clkxtal",
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"armpll",
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"main_core_en",
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"armpll"
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};
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static const struct mtk_composite cpu_muxes[] = {
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MUX(CLK_INFRA_MUX1_SEL, "infra_mux1_sel", infra_mux1_parents, 0x000, 2, 2),
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};
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static const struct mtk_gate infra_clks[] = {
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GATE_INFRA(CLK_INFRA_DBGCLK_PD, "infra_dbgclk_pd", "axi_sel", 0),
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GATE_INFRA(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 2),
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GATE_INFRA(CLK_INFRA_AUDIO_PD, "infra_audio_pd", "aud_intbus_sel", 5),
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GATE_INFRA(CLK_INFRA_IRRX_PD, "infra_irrx_pd", "irrx_sel", 16),
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GATE_INFRA(CLK_INFRA_APXGPT_PD, "infra_apxgpt_pd", "f10m_ref_sel", 18),
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GATE_INFRA(CLK_INFRA_PMIC_PD, "infra_pmic_pd", "pmicspi_sel", 22),
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};
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static u16 infrasys_rst_ofs[] = { 0x30 };
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static const struct mtk_clk_rst_desc clk_rst_desc = {
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.version = MTK_RST_SIMPLE,
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.rst_bank_ofs = infrasys_rst_ofs,
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.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
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};
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static const struct of_device_id of_match_clk_mt7622_infracfg[] = {
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{ .compatible = "mediatek,mt7622-infracfg" },
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{ /* sentinel */ }
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};
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static int clk_mt7622_infracfg_probe(struct platform_device *pdev)
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{
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struct clk_hw_onecell_data *clk_data;
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struct device_node *node = pdev->dev.of_node;
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void __iomem *base;
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int ret;
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base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(base))
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return PTR_ERR(base);
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clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
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if (!clk_data)
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return -ENOMEM;
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ret = mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
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if (ret)
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goto free_clk_data;
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ret = mtk_clk_register_gates(&pdev->dev, node, infra_clks,
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ARRAY_SIZE(infra_clks), clk_data);
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if (ret)
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goto free_clk_data;
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ret = mtk_clk_register_cpumuxes(&pdev->dev, node, cpu_muxes,
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ARRAY_SIZE(cpu_muxes), clk_data);
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if (ret)
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goto unregister_gates;
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ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
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if (ret)
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goto unregister_cpumuxes;
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return 0;
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unregister_cpumuxes:
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mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data);
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unregister_gates:
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mtk_clk_unregister_gates(infra_clks, ARRAY_SIZE(infra_clks), clk_data);
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free_clk_data:
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mtk_free_clk_data(clk_data);
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return ret;
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}
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static int clk_mt7622_infracfg_remove(struct platform_device *pdev)
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{
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struct device_node *node = pdev->dev.of_node;
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struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
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of_clk_del_provider(node);
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mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data);
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mtk_clk_unregister_gates(infra_clks, ARRAY_SIZE(infra_clks), clk_data);
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mtk_free_clk_data(clk_data);
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return 0;
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}
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static struct platform_driver clk_mt7622_infracfg_drv = {
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.driver = {
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.name = "clk-mt7622-infracfg",
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.of_match_table = of_match_clk_mt7622_infracfg,
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},
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.probe = clk_mt7622_infracfg_probe,
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.remove = clk_mt7622_infracfg_remove,
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};
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module_platform_driver(clk_mt7622_infracfg_drv);
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MODULE_DESCRIPTION("MediaTek MT7622 infracfg clocks driver");
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MODULE_LICENSE("GPL");
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@ -18,9 +18,6 @@
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#include <dt-bindings/clock/mt7622-clk.h>
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#include <linux/clk.h> /* for consumer */
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#define GATE_INFRA(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
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#define GATE_TOP0(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
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@ -39,13 +36,6 @@
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static DEFINE_SPINLOCK(mt7622_clk_lock);
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static const char * const infra_mux1_parents[] = {
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"clkxtal",
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"armpll",
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"main_core_en",
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"armpll"
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};
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static const char * const axi_parents[] = {
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"clkxtal",
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"syspll1_d2",
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@ -225,12 +215,6 @@ static const char * const peribus_ck_parents[] = {
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"syspll1_d4"
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};
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static const struct mtk_gate_regs infra_cg_regs = {
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.set_ofs = 0x40,
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.clr_ofs = 0x44,
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.sta_ofs = 0x48,
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};
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static const struct mtk_gate_regs top0_cg_regs = {
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.set_ofs = 0x120,
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.clr_ofs = 0x120,
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@ -255,15 +239,6 @@ static const struct mtk_gate_regs peri1_cg_regs = {
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.sta_ofs = 0x1C,
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};
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static const struct mtk_gate infra_clks[] = {
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GATE_INFRA(CLK_INFRA_DBGCLK_PD, "infra_dbgclk_pd", "axi_sel", 0),
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GATE_INFRA(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 2),
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GATE_INFRA(CLK_INFRA_AUDIO_PD, "infra_audio_pd", "aud_intbus_sel", 5),
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GATE_INFRA(CLK_INFRA_IRRX_PD, "infra_irrx_pd", "irrx_sel", 16),
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GATE_INFRA(CLK_INFRA_APXGPT_PD, "infra_apxgpt_pd", "f10m_ref_sel", 18),
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GATE_INFRA(CLK_INFRA_PMIC_PD, "infra_pmic_pd", "pmicspi_sel", 22),
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};
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static const struct mtk_fixed_clk top_fixed_clks[] = {
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FIXED_CLK(CLK_TOP_TO_U2_PHY, "to_u2_phy", "clkxtal",
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31250000),
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@ -408,11 +383,6 @@ static const struct mtk_gate peri_clks[] = {
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GATE_PERI1(CLK_PERI_IRTX_PD, "peri_irtx_pd", "irtx_sel", 2),
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};
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static struct mtk_composite infra_muxes[] = {
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MUX(CLK_INFRA_MUX1_SEL, "infra_mux1_sel", infra_mux1_parents,
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0x000, 2, 2),
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};
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static struct mtk_composite top_muxes[] = {
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/* CLK_CFG_0 */
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MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
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@ -512,22 +482,12 @@ static struct mtk_composite peri_muxes[] = {
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MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1),
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};
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static u16 infrasys_rst_ofs[] = { 0x30, };
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static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };
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static const struct mtk_clk_rst_desc clk_rst_desc[] = {
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/* infrasys */
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{
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.version = MTK_RST_SIMPLE,
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.rst_bank_ofs = infrasys_rst_ofs,
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.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
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},
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/* pericfg */
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{
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static const struct mtk_clk_rst_desc clk_rst_desc = {
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.version = MTK_RST_SIMPLE,
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.rst_bank_ofs = pericfg_rst_ofs,
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.rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),
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},
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};
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static int mtk_topckgen_init(struct platform_device *pdev)
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@ -561,31 +521,6 @@ static int mtk_topckgen_init(struct platform_device *pdev)
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return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
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}
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static int mtk_infrasys_init(struct platform_device *pdev)
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{
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struct device_node *node = pdev->dev.of_node;
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struct clk_hw_onecell_data *clk_data;
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int r;
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clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
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mtk_clk_register_gates(&pdev->dev, node, infra_clks,
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ARRAY_SIZE(infra_clks), clk_data);
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mtk_clk_register_cpumuxes(&pdev->dev, node, infra_muxes,
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ARRAY_SIZE(infra_muxes), clk_data);
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r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
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clk_data);
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if (r)
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return r;
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mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]);
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return 0;
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}
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static int mtk_pericfg_init(struct platform_device *pdev)
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{
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struct clk_hw_onecell_data *clk_data;
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@ -610,16 +545,13 @@ static int mtk_pericfg_init(struct platform_device *pdev)
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if (r)
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return r;
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mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);
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mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
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return 0;
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}
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static const struct of_device_id of_match_clk_mt7622[] = {
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{
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.compatible = "mediatek,mt7622-infracfg",
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.data = mtk_infrasys_init,
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}, {
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.compatible = "mediatek,mt7622-topckgen",
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.data = mtk_topckgen_init,
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}, {
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