ARM: dts: tegra20: paz00: Add memory timings
PAZ00 board has two variants of DDR2 SDRAM devices for External Memory: one is Hynix HY5PS1G831CLFP-Y5 and the other is Micron MT47H128M8CF-25:H. The Micron variant doesn't have official timings in the wild, hence only timings for the Hynix are added. The memory frequency-scaling was tested using the Tegra20 devfreq driver. Tested-by: Marc Dietrich <marvin24@gmx.de> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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@ -311,6 +311,52 @@
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reset-names = "i2c";
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};
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memory-controller@7000f400 {
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nvidia,use-ram-code;
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emc-tables@hynix {
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nvidia,ram-code = <0x0>;
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#address-cells = <1>;
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#size-cells = <0>;
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emc-table@166500 {
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reg = <166500>;
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compatible = "nvidia,tegra20-emc-table";
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clock-frequency = <166500>;
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nvidia,emc-registers = <0x0000000a 0x00000016
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0x00000008 0x00000003 0x00000004 0x00000004
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0x00000002 0x0000000c 0x00000003 0x00000003
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0x00000002 0x00000001 0x00000004 0x00000005
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0x00000004 0x00000009 0x0000000d 0x000004df
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0x00000000 0x00000003 0x00000003 0x00000003
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0x00000003 0x00000001 0x0000000a 0x000000c8
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0x00000003 0x00000006 0x00000004 0x00000008
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0x00000002 0x00000000 0x00000000 0x00000002
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0x00000000 0x00000000 0x00000083 0xe03b0323
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0x007fe010 0x00001414 0x00000000 0x00000000
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0x00000000 0x00000000 0x00000000 0x00000000>;
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};
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emc-table@333000 {
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reg = <333000>;
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compatible = "nvidia,tegra20-emc-table";
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clock-frequency = <333000>;
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nvidia,emc-registers = <0x00000018 0x00000033
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0x00000012 0x00000004 0x00000004 0x00000005
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0x00000003 0x0000000c 0x00000006 0x00000006
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0x00000003 0x00000001 0x00000004 0x00000005
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0x00000004 0x00000009 0x0000000d 0x00000bff
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0x00000000 0x00000003 0x00000003 0x00000006
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0x00000006 0x00000001 0x00000011 0x000000c8
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0x00000003 0x0000000e 0x00000007 0x00000008
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0x00000002 0x00000000 0x00000000 0x00000002
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0x00000000 0x00000000 0x00000083 0xf0440303
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0x007fe010 0x00001414 0x00000000 0x00000000
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0x00000000 0x00000000 0x00000000 0x00000000>;
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};
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};
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};
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i2c@7000d000 {
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status = "okay";
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clock-frequency = <400000>;
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