ARM: shmobile: sh73a0: add DMAEngine support for MPDMAC
Current shdmac can support MPDMAC (= sound DMA) on sh73a0. This support reduce CPU load when sound was playback. On v2.0 manual, MPDMAC MID/RID number were wrong. This patch is using the number which seems correct. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
This commit is contained in:
Kuninori Morimoto
Rafael J. Wysocki
parent
12a7cfef56
commit
832290b25e
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@ -475,7 +475,7 @@ static struct clk *late_main_clks[] = {
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enum { MSTP001,
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MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP100,
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MSTP219, MSTP218,
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MSTP219, MSTP218, MSTP217,
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MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
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MSTP331, MSTP329, MSTP328, MSTP325, MSTP323, MSTP322,
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MSTP314, MSTP313, MSTP312, MSTP311,
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@ -498,6 +498,7 @@ static struct clk mstp_clks[MSTP_NR] = {
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[MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
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[MSTP219] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 19, 0), /* SCIFA7 */
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[MSTP218] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* SY-DMAC */
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[MSTP217] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 17, 0), /* MP-DMAC */
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[MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
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[MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
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[MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
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@ -555,6 +556,7 @@ static struct clk_lookup lookups[] = {
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CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */
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CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP219]), /* SCIFA7 */
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CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), /* SY-DMAC */
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CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP217]), /* MP-DMAC */
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CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
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CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), /* SCIFB */
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CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
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@ -516,6 +516,13 @@ enum {
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SHDMA_SLAVE_SDHI2_RX,
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SHDMA_SLAVE_MMCIF_TX,
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SHDMA_SLAVE_MMCIF_RX,
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SHDMA_SLAVE_FSI2A_TX,
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SHDMA_SLAVE_FSI2A_RX,
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SHDMA_SLAVE_FSI2B_TX,
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SHDMA_SLAVE_FSI2B_RX,
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SHDMA_SLAVE_FSI2C_TX,
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SHDMA_SLAVE_FSI2C_RX,
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SHDMA_SLAVE_FSI2D_RX,
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};
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/*
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@ -651,6 +651,116 @@ static struct platform_device dma0_device = {
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},
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};
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/* MPDMAC */
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static const struct sh_dmae_slave_config sh73a0_mpdma_slaves[] = {
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{
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.slave_id = SHDMA_SLAVE_FSI2A_RX,
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.addr = 0xec230020,
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.chcr = CHCR_RX(XMIT_SZ_32BIT),
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.mid_rid = 0xd6, /* CHECK ME */
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}, {
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.slave_id = SHDMA_SLAVE_FSI2A_TX,
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.addr = 0xec230024,
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.chcr = CHCR_TX(XMIT_SZ_32BIT),
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.mid_rid = 0xd5, /* CHECK ME */
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}, {
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.slave_id = SHDMA_SLAVE_FSI2C_RX,
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.addr = 0xec230060,
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.chcr = CHCR_RX(XMIT_SZ_32BIT),
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.mid_rid = 0xda, /* CHECK ME */
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}, {
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.slave_id = SHDMA_SLAVE_FSI2C_TX,
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.addr = 0xec230064,
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.chcr = CHCR_TX(XMIT_SZ_32BIT),
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.mid_rid = 0xd9, /* CHECK ME */
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}, {
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.slave_id = SHDMA_SLAVE_FSI2B_RX,
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.addr = 0xec240020,
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.chcr = CHCR_RX(XMIT_SZ_32BIT),
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.mid_rid = 0x8e, /* CHECK ME */
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}, {
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.slave_id = SHDMA_SLAVE_FSI2B_TX,
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.addr = 0xec240024,
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.chcr = CHCR_RX(XMIT_SZ_32BIT),
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.mid_rid = 0x8d, /* CHECK ME */
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}, {
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.slave_id = SHDMA_SLAVE_FSI2D_RX,
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.addr = 0xec240060,
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.chcr = CHCR_RX(XMIT_SZ_32BIT),
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.mid_rid = 0x9a, /* CHECK ME */
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},
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};
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#define MPDMA_CHANNEL(a, b, c) \
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{ \
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.offset = a, \
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.dmars = b, \
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.dmars_bit = c, \
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.chclr_offset = (0x220 - 0x20) + a \
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}
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static const struct sh_dmae_channel sh73a0_mpdma_channels[] = {
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MPDMA_CHANNEL(0x00, 0, 0),
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MPDMA_CHANNEL(0x10, 0, 8),
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MPDMA_CHANNEL(0x20, 4, 0),
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MPDMA_CHANNEL(0x30, 4, 8),
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MPDMA_CHANNEL(0x50, 8, 0),
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MPDMA_CHANNEL(0x70, 8, 8),
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};
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static struct sh_dmae_pdata sh73a0_mpdma_platform_data = {
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.slave = sh73a0_mpdma_slaves,
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.slave_num = ARRAY_SIZE(sh73a0_mpdma_slaves),
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.channel = sh73a0_mpdma_channels,
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.channel_num = ARRAY_SIZE(sh73a0_mpdma_channels),
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.ts_low_shift = 3,
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.ts_low_mask = 0x18,
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.ts_high_shift = (20 - 2), /* 2 bits for shifted low TS */
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.ts_high_mask = 0x00300000,
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.ts_shift = ts_shift,
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.ts_shift_num = ARRAY_SIZE(ts_shift),
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.dmaor_init = DMAOR_DME,
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.chclr_present = 1,
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};
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/* Resource order important! */
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static struct resource sh73a0_mpdma_resources[] = {
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{
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/* Channel registers and DMAOR */
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.start = 0xec618020,
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.end = 0xec61828f,
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.flags = IORESOURCE_MEM,
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},
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{
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/* DMARSx */
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.start = 0xec619000,
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.end = 0xec61900b,
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.flags = IORESOURCE_MEM,
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},
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{
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.name = "error_irq",
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.start = gic_spi(181),
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.end = gic_spi(181),
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.flags = IORESOURCE_IRQ,
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},
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{
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/* IRQ for channels 0-5 */
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.start = gic_spi(175),
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.end = gic_spi(180),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device mpdma0_device = {
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.name = "sh-dma-engine",
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.id = 1,
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.resource = sh73a0_mpdma_resources,
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.num_resources = ARRAY_SIZE(sh73a0_mpdma_resources),
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.dev = {
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.platform_data = &sh73a0_mpdma_platform_data,
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},
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};
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static struct platform_device *sh73a0_early_devices[] __initdata = {
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&scif0_device,
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&scif1_device,
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@ -673,6 +783,7 @@ static struct platform_device *sh73a0_late_devices[] __initdata = {
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&i2c3_device,
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&i2c4_device,
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&dma0_device,
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&mpdma0_device,
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};
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#define SRCR2 0xe61580b0
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