Merge branches 'clk-qcom' and 'clk-microchip' into clk-next
* clk-qcom: (63 commits) clk: qcom: gcc-sc8280xp: Add runtime PM clk: qcom: gpucc-sc8280xp: Add runtime PM clk: qcom: mmcc-msm8974: fix MDSS_GDSC power flags clk: qcom: gpucc-sm6375: Enable runtime pm dt-bindings: clock: sm6375-gpucc: Add VDD_GX clk: qcom: gcc-sm6115: Add missing PLL config properties clk: qcom: clk-alpha-pll: Add a way to update some bits of test_ctl(_hi) clk: qcom: gcc-ipq6018: remove duplicate initializers clk: qcom: gcc-ipq9574: Enable crypto clocks dt-bindings: clock: Add crypto clock and reset definitions clk: qcom: Add lpass audio clock controller driver for SC8280XP clk: qcom: Add lpass clock controller driver for SC8280XP dt-bindings: clock: Add LPASS AUDIOCC and reset controller for SC8280XP dt-bindings: clock: Add LPASSCC and reset controller for SC8280XP dt-bindings: clock: qcom,mmcc: define clocks/clock-names for MSM8226 clk: qcom: gpucc-sm8550: Add support for graphics clock controller clk: qcom: Add support for SM8450 GPUCC clk: qcom: gcc-sm8450: Enable hw_clk_ctrl clk: qcom: rcg2: Make hw_clk_ctrl toggleable dt-bindings: clock: qcom: Add SM8550 graphics clock controller ... * clk-microchip: clk: at91: sama7g5: s/ep_chg_chg_id/ep_chg_id clk: at91: sama7g5: switch to parent_hw and parent_data clk: at91: sckc: switch to parent_data/parent_hw clk: at91: clk-sam9x60-pll: add support for parent_hw clk: at91: clk-utmi: add support for parent_hw clk: at91: clk-system: add support for parent_hw clk: at91: clk-programmable: add support for parent_hw clk: at91: clk-peripheral: add support for parent_hw clk: at91: clk-master: add support for parent_hw clk: at91: clk-generated: add support for parent_hw clk: at91: clk-main: add support for parent_data/parent_hw
This commit is contained in:
Stephen Boyd
commit
82e58e69d7
|
|
@ -19,6 +19,7 @@ properties:
|
|||
- qcom,ipq5332-a53pll
|
||||
- qcom,ipq6018-a53pll
|
||||
- qcom,ipq8074-a53pll
|
||||
- qcom,ipq9574-a73pll
|
||||
- qcom,msm8916-a53pll
|
||||
- qcom,msm8939-a53pll
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,73 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8953.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller on MSM8953
|
||||
|
||||
maintainers:
|
||||
- Adam Skladowski <a_skl39@protonmail.com>
|
||||
- Sireesh Kodali <sireeshkodali@protonmail.com>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on MSM8953.
|
||||
|
||||
See also: include/dt-bindings/clock/qcom,gcc-msm8953.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-msm8953
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Sleep clock source
|
||||
- description: Byte clock from DSI PHY0
|
||||
- description: Pixel clock from DSI PHY0
|
||||
- description: Byte clock from DSI PHY1
|
||||
- description: Pixel clock from DSI PHY1
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||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xo
|
||||
- const: sleep
|
||||
- const: dsi0pll
|
||||
- const: dsi0pllbyte
|
||||
- const: dsi1pll
|
||||
- const: dsi1pllbyte
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
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|
||||
clock-controller@1800000 {
|
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compatible = "qcom,gcc-msm8953";
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||||
reg = <0x01800000 0x80000>;
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clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
|
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<&sleep_clk>,
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||||
<&dsi0_phy 1>,
|
||||
<&dsi0_phy 0>,
|
||||
<&dsi1_phy 1>,
|
||||
<&dsi1_phy 0>;
|
||||
clock-names = "xo",
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"sleep",
|
||||
"dsi0pll",
|
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"dsi0pllbyte",
|
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"dsi1pll",
|
||||
"dsi1pllbyte";
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#clock-cells = <1>;
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#reset-cells = <1>;
|
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#power-domain-cells = <1>;
|
||||
};
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||||
|
|
@ -30,7 +30,6 @@ properties:
|
|||
enum:
|
||||
- qcom,gcc-ipq6018
|
||||
- qcom,gcc-mdm9607
|
||||
- qcom,gcc-msm8953
|
||||
- qcom,gcc-mdm9615
|
||||
|
||||
required:
|
||||
|
|
|
|||
|
|
@ -32,6 +32,10 @@ properties:
|
|||
- const: bi_tcxo_ao
|
||||
- const: sleep_clk
|
||||
|
||||
power-domains:
|
||||
items:
|
||||
- description: CX domain
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
|
|
@ -45,6 +49,8 @@ unevaluatedProperties: false
|
|||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,gcc-sc7180";
|
||||
reg = <0x00100000 0x1f0000>;
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||||
|
|
@ -52,6 +58,7 @@ examples:
|
|||
<&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&sleep_clk>;
|
||||
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
|
||||
power-domains = <&rpmhpd SC7180_CX>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -43,6 +43,10 @@ properties:
|
|||
- const: ufs_phy_tx_symbol_0_clk
|
||||
- const: usb3_phy_wrapper_gcc_usb30_pipe_clk
|
||||
|
||||
power-domains:
|
||||
items:
|
||||
- description: CX domain
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
|
|
@ -56,6 +60,8 @@ unevaluatedProperties: false
|
|||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,gcc-sc7280";
|
||||
reg = <0x00100000 0x1f0000>;
|
||||
|
|
@ -71,6 +77,7 @@ examples:
|
|||
"pcie_1_pipe_clk", "ufs_phy_rx_symbol_0_clk",
|
||||
"ufs_phy_rx_symbol_1_clk", "ufs_phy_tx_symbol_0_clk",
|
||||
"usb3_phy_wrapper_gcc_usb30_pipe_clk";
|
||||
power-domains = <&rpmhpd SC7280_CX>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -23,11 +23,13 @@ properties:
|
|||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Board active XO source
|
||||
- description: Sleep clock source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: bi_tcxo_ao
|
||||
- const: sleep_clk
|
||||
|
||||
required:
|
||||
|
|
@ -47,8 +49,9 @@ examples:
|
|||
compatible = "qcom,gcc-sm8250";
|
||||
reg = <0x00100000 0x1f0000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&sleep_clk>;
|
||||
clock-names = "bi_tcxo", "sleep_clk";
|
||||
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -50,6 +50,9 @@ properties:
|
|||
- const: gcc_gpu_gpll0_clk_src
|
||||
- const: gcc_gpu_gpll0_div_clk_src
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
|||
title: Qualcomm Global Clock & Reset Controller on IPQ9574
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Anusha Rao <quic_anusha@quicinc.com>
|
||||
|
||||
description: |
|
||||
|
|
|
|||
|
|
@ -31,11 +31,11 @@ properties:
|
|||
- qcom,mmcc-sdm660
|
||||
|
||||
clocks:
|
||||
minItems: 8
|
||||
minItems: 7
|
||||
maxItems: 13
|
||||
|
||||
clock-names:
|
||||
minItems: 8
|
||||
minItems: 7
|
||||
maxItems: 13
|
||||
|
||||
'#clock-cells':
|
||||
|
|
@ -99,6 +99,34 @@ allOf:
|
|||
- const: dsi2pllbyte
|
||||
- const: hdmipll
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,mmcc-msm8226
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: MMSS GPLL0 voted clock
|
||||
- description: GPLL0 voted clock
|
||||
- description: GPLL1 voted clock
|
||||
- description: GFX3D clock source
|
||||
- description: DSI phy instance 0 dsi clock
|
||||
- description: DSI phy instance 0 byte clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xo
|
||||
- const: mmss_gpll0_vote
|
||||
- const: gpll0_vote
|
||||
- const: gpll1_vote
|
||||
- const: gfx3d_clk_src
|
||||
- const: dsi0pll
|
||||
- const: dsi0pllbyte
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -27,6 +27,7 @@ properties:
|
|||
- qcom,sdm845-rpmh-clk
|
||||
- qcom,sdx55-rpmh-clk
|
||||
- qcom,sdx65-rpmh-clk
|
||||
- qcom,sdx75-rpmh-clk
|
||||
- qcom,sm6350-rpmh-clk
|
||||
- qcom,sm8150-rpmh-clk
|
||||
- qcom,sm8250-rpmh-clk
|
||||
|
|
|
|||
|
|
@ -0,0 +1,60 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sc8280xp-lpasscc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm LPASS Core & Audio Clock Controller on SC8280XP
|
||||
|
||||
maintainers:
|
||||
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
|
||||
|
||||
description: |
|
||||
Qualcomm LPASS core and audio clock control module provides the clocks,
|
||||
and reset on SC8280XP.
|
||||
|
||||
See also::
|
||||
include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sc8280xp-lpassaudiocc
|
||||
- qcom,sc8280xp-lpasscc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
|
||||
lpass_audiocc: clock-controller@32a9000 {
|
||||
compatible = "qcom,sc8280xp-lpassaudiocc";
|
||||
reg = <0x032a9000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
|
||||
lpasscc: clock-controller@33e0000 {
|
||||
compatible = "qcom,sc8280xp-lpasscc";
|
||||
reg = <0x033e0000 0x12000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
...
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sdx75-gcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller on SDX75
|
||||
|
||||
maintainers:
|
||||
- Imran Shaik <quic_imrashai@quicinc.com>
|
||||
- Taniya Das <quic_tdas@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on SDX75
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,sdx75-gcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sdx75-gcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Sleep clock source
|
||||
- description: EMAC0 sgmiiphy mac rclk source
|
||||
- description: EMAC0 sgmiiphy mac tclk source
|
||||
- description: EMAC0 sgmiiphy rclk source
|
||||
- description: EMAC0 sgmiiphy tclk source
|
||||
- description: EMAC1 sgmiiphy mac rclk source
|
||||
- description: EMAC1 sgmiiphy mac tclk source
|
||||
- description: EMAC1 sgmiiphy rclk source
|
||||
- description: EMAC1 sgmiiphy tclk source
|
||||
- description: PCIE20 phy aux clock source
|
||||
- description: PCIE_1 Pipe clock source
|
||||
- description: PCIE_2 Pipe clock source
|
||||
- description: PCIE Pipe clock source
|
||||
- description: USB3 phy wrapper pipe clock source
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@80000 {
|
||||
compatible = "qcom,sdx75-gcc";
|
||||
reg = <0x80000 0x1f7400>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, <&emac0_sgmiiphy_mac_rclk>,
|
||||
<&emac0_sgmiiphy_mac_tclk>, <&emac0_sgmiiphy_rclk>, <&emac0_sgmiiphy_tclk>,
|
||||
<&emac1_sgmiiphy_mac_rclk>, <&emac1_sgmiiphy_mac_tclk>, <&emac1_sgmiiphy_rclk>,
|
||||
<&emac1_sgmiiphy_tclk>, <&pcie20_phy_aux_clk>, <&pcie_1_pipe_clk>,
|
||||
<&pcie_2_pipe_clk>, <&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
|
|
@ -27,9 +27,21 @@ properties:
|
|||
- description: GPLL0 div branch source
|
||||
- description: SNoC DVM GFX source
|
||||
|
||||
power-domains:
|
||||
description:
|
||||
A phandle and PM domain specifier for the VDD_GX power rail
|
||||
maxItems: 1
|
||||
|
||||
required-opps:
|
||||
description:
|
||||
A phandle to an OPP node describing required VDD_GX performance point.
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- power-domains
|
||||
- required-opps
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
|
@ -40,6 +52,7 @@ examples:
|
|||
- |
|
||||
#include <dt-bindings/clock/qcom,sm6375-gcc.h>
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
|
|
@ -52,6 +65,8 @@ examples:
|
|||
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
|
||||
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>,
|
||||
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
|
||||
power-domains = <&rpmpd SM6375_VDDGX>;
|
||||
required-opps = <&rpmpd_opp_low_svs>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,68 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sm8350-videocc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SM8350 Video Clock & Reset Controller
|
||||
|
||||
maintainers:
|
||||
- Konrad Dybcio <konrad.dybcio@linaro.org>
|
||||
|
||||
description: |
|
||||
Qualcomm video clock control module provides the clocks, resets and power
|
||||
domains on Qualcomm SoCs.
|
||||
|
||||
See also::
|
||||
include/dt-bindings/clock/qcom,videocc-sm8350.h
|
||||
include/dt-bindings/reset/qcom,videocc-sm8350.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm8350-videocc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Board active XO source
|
||||
- description: Board sleep clock
|
||||
|
||||
power-domains:
|
||||
description:
|
||||
A phandle and PM domain specifier for the MMCX power domain.
|
||||
maxItems: 1
|
||||
|
||||
required-opps:
|
||||
description:
|
||||
A phandle to an OPP node describing required MMCX performance point.
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- power-domains
|
||||
- required-opps
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
clock-controller@abf0000 {
|
||||
compatible = "qcom,sm8350-videocc";
|
||||
reg = <0x0abf0000 0x10000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&sleep_clk>;
|
||||
power-domains = <&rpmhpd SM8350_MMCX>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
|
|
@ -0,0 +1,75 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sm8450-gpucc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Graphics Clock & Reset Controller on SM8450
|
||||
|
||||
maintainers:
|
||||
- Konrad Dybcio <konrad.dybcio@linaro.org>
|
||||
|
||||
description: |
|
||||
Qualcomm graphics clock control module provides the clocks, resets and power
|
||||
domains on Qualcomm SoCs.
|
||||
|
||||
See also::
|
||||
include/dt-bindings/clock/qcom,sm8450-gpucc.h
|
||||
include/dt-bindings/clock/qcom,sm8550-gpucc.h
|
||||
include/dt-bindings/reset/qcom,sm8450-gpucc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sm8450-gpucc
|
||||
- qcom,sm8550-gpucc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: GPLL0 main branch source
|
||||
- description: GPLL0 div branch source
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
clock-controller@3d90000 {
|
||||
compatible = "qcom,sm8450-gpucc";
|
||||
reg = <0 0x03d90000 0 0xa000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
|
||||
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
@ -0,0 +1,79 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sm8450-videocc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Video Clock & Reset Controller on SM8450
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <quic_tdas@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm video clock control module provides the clocks, resets and power
|
||||
domains on SM8450.
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,videocc-sm8450.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sm8450-videocc
|
||||
- qcom,sm8550-videocc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Video AHB clock from GCC
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
description:
|
||||
MMCX power domain.
|
||||
|
||||
required-opps:
|
||||
maxItems: 1
|
||||
description:
|
||||
A phandle to an OPP node describing required MMCX performance point.
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- power-domains
|
||||
- required-opps
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
videocc: clock-controller@aaf0000 {
|
||||
compatible = "qcom,sm8450-videocc";
|
||||
reg = <0x0aaf0000 0x10000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_VIDEO_AHB_CLK>;
|
||||
power-domains = <&rpmhpd SM8450_MMCX>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
|
|
@ -108,12 +108,12 @@ static void __init at91rm9200_pmc_setup(struct device_node *np)
|
|||
|
||||
bypass = of_property_read_bool(np, "atmel,osc-bypass");
|
||||
|
||||
hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
|
||||
hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL,
|
||||
bypass);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
||||
hw = at91_clk_register_rm9200_main(regmap, "mainck", "main_osc");
|
||||
hw = at91_clk_register_rm9200_main(regmap, "mainck", "main_osc", NULL);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
||||
|
|
@ -140,7 +140,7 @@ static void __init at91rm9200_pmc_setup(struct device_node *np)
|
|||
parent_names[2] = "pllack";
|
||||
parent_names[3] = "pllbck";
|
||||
hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
|
||||
parent_names,
|
||||
parent_names, NULL,
|
||||
&at91rm9200_master_layout,
|
||||
&rm9200_mck_characteristics,
|
||||
&rm9200_mck_lock);
|
||||
|
|
@ -148,7 +148,7 @@ static void __init at91rm9200_pmc_setup(struct device_node *np)
|
|||
goto err_free;
|
||||
|
||||
hw = at91_clk_register_master_div(regmap, "masterck_div",
|
||||
"masterck_pres",
|
||||
"masterck_pres", NULL,
|
||||
&at91rm9200_master_layout,
|
||||
&rm9200_mck_characteristics,
|
||||
&rm9200_mck_lock, CLK_SET_RATE_GATE, 0);
|
||||
|
|
@ -171,7 +171,7 @@ static void __init at91rm9200_pmc_setup(struct device_node *np)
|
|||
snprintf(name, sizeof(name), "prog%d", i);
|
||||
|
||||
hw = at91_clk_register_programmable(regmap, name,
|
||||
parent_names, 4, i,
|
||||
parent_names, NULL, 4, i,
|
||||
&at91rm9200_programmable_layout,
|
||||
NULL);
|
||||
if (IS_ERR(hw))
|
||||
|
|
@ -182,7 +182,7 @@ static void __init at91rm9200_pmc_setup(struct device_node *np)
|
|||
|
||||
for (i = 0; i < ARRAY_SIZE(at91rm9200_systemck); i++) {
|
||||
hw = at91_clk_register_system(regmap, at91rm9200_systemck[i].n,
|
||||
at91rm9200_systemck[i].p,
|
||||
at91rm9200_systemck[i].p, NULL,
|
||||
at91rm9200_systemck[i].id, 0);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
|
@ -193,7 +193,7 @@ static void __init at91rm9200_pmc_setup(struct device_node *np)
|
|||
for (i = 0; i < ARRAY_SIZE(at91rm9200_periphck); i++) {
|
||||
hw = at91_clk_register_peripheral(regmap,
|
||||
at91rm9200_periphck[i].n,
|
||||
"masterck_div",
|
||||
"masterck_div", NULL,
|
||||
at91rm9200_periphck[i].id);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
|
|
|||
|
|
@ -363,12 +363,12 @@ static void __init at91sam926x_pmc_setup(struct device_node *np,
|
|||
|
||||
bypass = of_property_read_bool(np, "atmel,osc-bypass");
|
||||
|
||||
hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
|
||||
hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL,
|
||||
bypass);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
||||
hw = at91_clk_register_rm9200_main(regmap, "mainck", "main_osc");
|
||||
hw = at91_clk_register_rm9200_main(regmap, "mainck", "main_osc", NULL);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
||||
|
|
@ -416,7 +416,7 @@ static void __init at91sam926x_pmc_setup(struct device_node *np,
|
|||
parent_names[2] = "pllack";
|
||||
parent_names[3] = "pllbck";
|
||||
hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
|
||||
parent_names,
|
||||
parent_names, NULL,
|
||||
&at91rm9200_master_layout,
|
||||
data->mck_characteristics,
|
||||
&at91sam9260_mck_lock);
|
||||
|
|
@ -424,7 +424,7 @@ static void __init at91sam926x_pmc_setup(struct device_node *np,
|
|||
goto err_free;
|
||||
|
||||
hw = at91_clk_register_master_div(regmap, "masterck_div",
|
||||
"masterck_pres",
|
||||
"masterck_pres", NULL,
|
||||
&at91rm9200_master_layout,
|
||||
data->mck_characteristics,
|
||||
&at91sam9260_mck_lock,
|
||||
|
|
@ -448,7 +448,7 @@ static void __init at91sam926x_pmc_setup(struct device_node *np,
|
|||
snprintf(name, sizeof(name), "prog%d", i);
|
||||
|
||||
hw = at91_clk_register_programmable(regmap, name,
|
||||
parent_names, 4, i,
|
||||
parent_names, NULL, 4, i,
|
||||
&at91rm9200_programmable_layout,
|
||||
NULL);
|
||||
if (IS_ERR(hw))
|
||||
|
|
@ -459,7 +459,7 @@ static void __init at91sam926x_pmc_setup(struct device_node *np,
|
|||
|
||||
for (i = 0; i < data->num_sck; i++) {
|
||||
hw = at91_clk_register_system(regmap, data->sck[i].n,
|
||||
data->sck[i].p,
|
||||
data->sck[i].p, NULL,
|
||||
data->sck[i].id, 0);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
|
@ -470,7 +470,7 @@ static void __init at91sam926x_pmc_setup(struct device_node *np,
|
|||
for (i = 0; i < data->num_pck; i++) {
|
||||
hw = at91_clk_register_peripheral(regmap,
|
||||
data->pck[i].n,
|
||||
"masterck_div",
|
||||
"masterck_div", NULL,
|
||||
data->pck[i].id);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
|
|
|||
|
|
@ -123,12 +123,12 @@ static void __init at91sam9g45_pmc_setup(struct device_node *np)
|
|||
|
||||
bypass = of_property_read_bool(np, "atmel,osc-bypass");
|
||||
|
||||
hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
|
||||
hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL,
|
||||
bypass);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
||||
hw = at91_clk_register_rm9200_main(regmap, "mainck", "main_osc");
|
||||
hw = at91_clk_register_rm9200_main(regmap, "mainck", "main_osc", NULL);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
||||
|
|
@ -145,7 +145,7 @@ static void __init at91sam9g45_pmc_setup(struct device_node *np)
|
|||
|
||||
at91sam9g45_pmc->chws[PMC_PLLACK] = hw;
|
||||
|
||||
hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck");
|
||||
hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck", NULL);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
||||
|
|
@ -156,7 +156,7 @@ static void __init at91sam9g45_pmc_setup(struct device_node *np)
|
|||
parent_names[2] = "plladivck";
|
||||
parent_names[3] = "utmick";
|
||||
hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
|
||||
parent_names,
|
||||
parent_names, NULL,
|
||||
&at91rm9200_master_layout,
|
||||
&mck_characteristics,
|
||||
&at91sam9g45_mck_lock);
|
||||
|
|
@ -164,7 +164,7 @@ static void __init at91sam9g45_pmc_setup(struct device_node *np)
|
|||
goto err_free;
|
||||
|
||||
hw = at91_clk_register_master_div(regmap, "masterck_div",
|
||||
"masterck_pres",
|
||||
"masterck_pres", NULL,
|
||||
&at91rm9200_master_layout,
|
||||
&mck_characteristics,
|
||||
&at91sam9g45_mck_lock,
|
||||
|
|
@ -191,7 +191,7 @@ static void __init at91sam9g45_pmc_setup(struct device_node *np)
|
|||
snprintf(name, sizeof(name), "prog%d", i);
|
||||
|
||||
hw = at91_clk_register_programmable(regmap, name,
|
||||
parent_names, 5, i,
|
||||
parent_names, NULL, 5, i,
|
||||
&at91sam9g45_programmable_layout,
|
||||
NULL);
|
||||
if (IS_ERR(hw))
|
||||
|
|
@ -202,7 +202,7 @@ static void __init at91sam9g45_pmc_setup(struct device_node *np)
|
|||
|
||||
for (i = 0; i < ARRAY_SIZE(at91sam9g45_systemck); i++) {
|
||||
hw = at91_clk_register_system(regmap, at91sam9g45_systemck[i].n,
|
||||
at91sam9g45_systemck[i].p,
|
||||
at91sam9g45_systemck[i].p, NULL,
|
||||
at91sam9g45_systemck[i].id,
|
||||
at91sam9g45_systemck[i].flags);
|
||||
if (IS_ERR(hw))
|
||||
|
|
@ -214,7 +214,7 @@ static void __init at91sam9g45_pmc_setup(struct device_node *np)
|
|||
for (i = 0; i < ARRAY_SIZE(at91sam9g45_periphck); i++) {
|
||||
hw = at91_clk_register_peripheral(regmap,
|
||||
at91sam9g45_periphck[i].n,
|
||||
"masterck_div",
|
||||
"masterck_div", NULL,
|
||||
at91sam9g45_periphck[i].id);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
|
|
|||
|
|
@ -147,14 +147,14 @@ static void __init at91sam9n12_pmc_setup(struct device_node *np)
|
|||
|
||||
bypass = of_property_read_bool(np, "atmel,osc-bypass");
|
||||
|
||||
hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
|
||||
hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL,
|
||||
bypass);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
||||
parent_names[0] = "main_rc_osc";
|
||||
parent_names[1] = "main_osc";
|
||||
hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
|
||||
hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL, 2);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
||||
|
|
@ -183,7 +183,7 @@ static void __init at91sam9n12_pmc_setup(struct device_node *np)
|
|||
parent_names[2] = "plladivck";
|
||||
parent_names[3] = "pllbck";
|
||||
hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
|
||||
parent_names,
|
||||
parent_names, NULL,
|
||||
&at91sam9x5_master_layout,
|
||||
&mck_characteristics,
|
||||
&at91sam9n12_mck_lock);
|
||||
|
|
@ -191,7 +191,7 @@ static void __init at91sam9n12_pmc_setup(struct device_node *np)
|
|||
goto err_free;
|
||||
|
||||
hw = at91_clk_register_master_div(regmap, "masterck_div",
|
||||
"masterck_pres",
|
||||
"masterck_pres", NULL,
|
||||
&at91sam9x5_master_layout,
|
||||
&mck_characteristics,
|
||||
&at91sam9n12_mck_lock,
|
||||
|
|
@ -216,7 +216,7 @@ static void __init at91sam9n12_pmc_setup(struct device_node *np)
|
|||
snprintf(name, sizeof(name), "prog%d", i);
|
||||
|
||||
hw = at91_clk_register_programmable(regmap, name,
|
||||
parent_names, 5, i,
|
||||
parent_names, NULL, 5, i,
|
||||
&at91sam9x5_programmable_layout,
|
||||
NULL);
|
||||
if (IS_ERR(hw))
|
||||
|
|
@ -227,7 +227,7 @@ static void __init at91sam9n12_pmc_setup(struct device_node *np)
|
|||
|
||||
for (i = 0; i < ARRAY_SIZE(at91sam9n12_systemck); i++) {
|
||||
hw = at91_clk_register_system(regmap, at91sam9n12_systemck[i].n,
|
||||
at91sam9n12_systemck[i].p,
|
||||
at91sam9n12_systemck[i].p, NULL,
|
||||
at91sam9n12_systemck[i].id,
|
||||
at91sam9n12_systemck[i].flags);
|
||||
if (IS_ERR(hw))
|
||||
|
|
@ -240,7 +240,7 @@ static void __init at91sam9n12_pmc_setup(struct device_node *np)
|
|||
hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
|
||||
&at91sam9n12_pcr_layout,
|
||||
at91sam9n12_periphck[i].n,
|
||||
"masterck_div",
|
||||
"masterck_div", NULL,
|
||||
at91sam9n12_periphck[i].id,
|
||||
&range, INT_MIN, 0);
|
||||
if (IS_ERR(hw))
|
||||
|
|
|
|||
|
|
@ -95,7 +95,7 @@ static void __init at91sam9rl_pmc_setup(struct device_node *np)
|
|||
if (!at91sam9rl_pmc)
|
||||
return;
|
||||
|
||||
hw = at91_clk_register_rm9200_main(regmap, "mainck", mainxtal_name);
|
||||
hw = at91_clk_register_rm9200_main(regmap, "mainck", mainxtal_name, NULL);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
||||
|
|
@ -109,7 +109,7 @@ static void __init at91sam9rl_pmc_setup(struct device_node *np)
|
|||
|
||||
at91sam9rl_pmc->chws[PMC_PLLACK] = hw;
|
||||
|
||||
hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck");
|
||||
hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck", NULL);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
||||
|
|
@ -120,7 +120,7 @@ static void __init at91sam9rl_pmc_setup(struct device_node *np)
|
|||
parent_names[2] = "pllack";
|
||||
parent_names[3] = "utmick";
|
||||
hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
|
||||
parent_names,
|
||||
parent_names, NULL,
|
||||
&at91rm9200_master_layout,
|
||||
&sam9rl_mck_characteristics,
|
||||
&sam9rl_mck_lock);
|
||||
|
|
@ -128,7 +128,7 @@ static void __init at91sam9rl_pmc_setup(struct device_node *np)
|
|||
goto err_free;
|
||||
|
||||
hw = at91_clk_register_master_div(regmap, "masterck_div",
|
||||
"masterck_pres",
|
||||
"masterck_pres", NULL,
|
||||
&at91rm9200_master_layout,
|
||||
&sam9rl_mck_characteristics,
|
||||
&sam9rl_mck_lock, CLK_SET_RATE_GATE, 0);
|
||||
|
|
@ -148,7 +148,7 @@ static void __init at91sam9rl_pmc_setup(struct device_node *np)
|
|||
snprintf(name, sizeof(name), "prog%d", i);
|
||||
|
||||
hw = at91_clk_register_programmable(regmap, name,
|
||||
parent_names, 5, i,
|
||||
parent_names, NULL, 5, i,
|
||||
&at91rm9200_programmable_layout,
|
||||
NULL);
|
||||
if (IS_ERR(hw))
|
||||
|
|
@ -159,7 +159,7 @@ static void __init at91sam9rl_pmc_setup(struct device_node *np)
|
|||
|
||||
for (i = 0; i < ARRAY_SIZE(at91sam9rl_systemck); i++) {
|
||||
hw = at91_clk_register_system(regmap, at91sam9rl_systemck[i].n,
|
||||
at91sam9rl_systemck[i].p,
|
||||
at91sam9rl_systemck[i].p, NULL,
|
||||
at91sam9rl_systemck[i].id, 0);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
|
@ -170,7 +170,7 @@ static void __init at91sam9rl_pmc_setup(struct device_node *np)
|
|||
for (i = 0; i < ARRAY_SIZE(at91sam9rl_periphck); i++) {
|
||||
hw = at91_clk_register_peripheral(regmap,
|
||||
at91sam9rl_periphck[i].n,
|
||||
"masterck_div",
|
||||
"masterck_div", NULL,
|
||||
at91sam9rl_periphck[i].id);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
|
|
|||
|
|
@ -169,14 +169,14 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np,
|
|||
|
||||
bypass = of_property_read_bool(np, "atmel,osc-bypass");
|
||||
|
||||
hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
|
||||
hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL,
|
||||
bypass);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
||||
parent_names[0] = "main_rc_osc";
|
||||
parent_names[1] = "main_osc";
|
||||
hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
|
||||
hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL, 2);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
||||
|
|
@ -193,7 +193,7 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np,
|
|||
|
||||
at91sam9x5_pmc->chws[PMC_PLLACK] = hw;
|
||||
|
||||
hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck");
|
||||
hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck", NULL);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
||||
|
|
@ -204,14 +204,14 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np,
|
|||
parent_names[2] = "plladivck";
|
||||
parent_names[3] = "utmick";
|
||||
hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
|
||||
parent_names,
|
||||
parent_names, NULL,
|
||||
&at91sam9x5_master_layout,
|
||||
&mck_characteristics, &mck_lock);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
||||
hw = at91_clk_register_master_div(regmap, "masterck_div",
|
||||
"masterck_pres",
|
||||
"masterck_pres", NULL,
|
||||
&at91sam9x5_master_layout,
|
||||
&mck_characteristics, &mck_lock,
|
||||
CLK_SET_RATE_GATE, 0);
|
||||
|
|
@ -241,7 +241,7 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np,
|
|||
snprintf(name, sizeof(name), "prog%d", i);
|
||||
|
||||
hw = at91_clk_register_programmable(regmap, name,
|
||||
parent_names, 5, i,
|
||||
parent_names, NULL, 5, i,
|
||||
&at91sam9x5_programmable_layout,
|
||||
NULL);
|
||||
if (IS_ERR(hw))
|
||||
|
|
@ -252,7 +252,7 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np,
|
|||
|
||||
for (i = 0; i < ARRAY_SIZE(at91sam9x5_systemck); i++) {
|
||||
hw = at91_clk_register_system(regmap, at91sam9x5_systemck[i].n,
|
||||
at91sam9x5_systemck[i].p,
|
||||
at91sam9x5_systemck[i].p, NULL,
|
||||
at91sam9x5_systemck[i].id,
|
||||
at91sam9x5_systemck[i].flags);
|
||||
if (IS_ERR(hw))
|
||||
|
|
@ -263,7 +263,7 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np,
|
|||
|
||||
if (has_lcdck) {
|
||||
hw = at91_clk_register_system(regmap, "lcdck", "masterck_div",
|
||||
3, 0);
|
||||
NULL, 3, 0);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
||||
|
|
@ -274,7 +274,7 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np,
|
|||
hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
|
||||
&at91sam9x5_pcr_layout,
|
||||
at91sam9x5_periphck[i].n,
|
||||
"masterck_div",
|
||||
"masterck_div", NULL,
|
||||
at91sam9x5_periphck[i].id,
|
||||
&range, INT_MIN, 0);
|
||||
if (IS_ERR(hw))
|
||||
|
|
@ -287,7 +287,7 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np,
|
|||
hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
|
||||
&at91sam9x5_pcr_layout,
|
||||
extra_pcks[i].n,
|
||||
"masterck_div",
|
||||
"masterck_div", NULL,
|
||||
extra_pcks[i].id,
|
||||
&range, INT_MIN, 0);
|
||||
if (IS_ERR(hw))
|
||||
|
|
|
|||
|
|
@ -319,22 +319,29 @@ struct clk_hw * __init
|
|||
at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,
|
||||
const struct clk_pcr_layout *layout,
|
||||
const char *name, const char **parent_names,
|
||||
struct clk_hw **parent_hws,
|
||||
u32 *mux_table, u8 num_parents, u8 id,
|
||||
const struct clk_range *range,
|
||||
int chg_pid)
|
||||
{
|
||||
struct clk_generated *gck;
|
||||
struct clk_init_data init;
|
||||
struct clk_init_data init = {};
|
||||
struct clk_hw *hw;
|
||||
int ret;
|
||||
|
||||
if (!(parent_names || parent_hws))
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
gck = kzalloc(sizeof(*gck), GFP_KERNEL);
|
||||
if (!gck)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
init.name = name;
|
||||
init.ops = &generated_ops;
|
||||
init.parent_names = parent_names;
|
||||
if (parent_hws)
|
||||
init.parent_hws = (const struct clk_hw **)parent_hws;
|
||||
else
|
||||
init.parent_names = parent_names;
|
||||
init.num_parents = num_parents;
|
||||
init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
|
||||
if (chg_pid >= 0)
|
||||
|
|
|
|||
|
|
@ -152,14 +152,15 @@ struct clk_hw * __init
|
|||
at91_clk_register_main_osc(struct regmap *regmap,
|
||||
const char *name,
|
||||
const char *parent_name,
|
||||
struct clk_parent_data *parent_data,
|
||||
bool bypass)
|
||||
{
|
||||
struct clk_main_osc *osc;
|
||||
struct clk_init_data init;
|
||||
struct clk_init_data init = {};
|
||||
struct clk_hw *hw;
|
||||
int ret;
|
||||
|
||||
if (!name || !parent_name)
|
||||
if (!name || !(parent_name || parent_data))
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
osc = kzalloc(sizeof(*osc), GFP_KERNEL);
|
||||
|
|
@ -168,7 +169,10 @@ at91_clk_register_main_osc(struct regmap *regmap,
|
|||
|
||||
init.name = name;
|
||||
init.ops = &main_osc_ops;
|
||||
init.parent_names = &parent_name;
|
||||
if (parent_data)
|
||||
init.parent_data = (const struct clk_parent_data *)parent_data;
|
||||
else
|
||||
init.parent_names = &parent_name;
|
||||
init.num_parents = 1;
|
||||
init.flags = CLK_IGNORE_UNUSED;
|
||||
|
||||
|
|
@ -397,17 +401,18 @@ static const struct clk_ops rm9200_main_ops = {
|
|||
struct clk_hw * __init
|
||||
at91_clk_register_rm9200_main(struct regmap *regmap,
|
||||
const char *name,
|
||||
const char *parent_name)
|
||||
const char *parent_name,
|
||||
struct clk_hw *parent_hw)
|
||||
{
|
||||
struct clk_rm9200_main *clkmain;
|
||||
struct clk_init_data init;
|
||||
struct clk_init_data init = {};
|
||||
struct clk_hw *hw;
|
||||
int ret;
|
||||
|
||||
if (!name)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
if (!parent_name)
|
||||
if (!(parent_name || parent_hw))
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL);
|
||||
|
|
@ -416,7 +421,10 @@ at91_clk_register_rm9200_main(struct regmap *regmap,
|
|||
|
||||
init.name = name;
|
||||
init.ops = &rm9200_main_ops;
|
||||
init.parent_names = &parent_name;
|
||||
if (parent_hw)
|
||||
init.parent_hws = (const struct clk_hw **)&parent_hw;
|
||||
else
|
||||
init.parent_names = &parent_name;
|
||||
init.num_parents = 1;
|
||||
init.flags = 0;
|
||||
|
||||
|
|
@ -544,10 +552,11 @@ struct clk_hw * __init
|
|||
at91_clk_register_sam9x5_main(struct regmap *regmap,
|
||||
const char *name,
|
||||
const char **parent_names,
|
||||
struct clk_hw **parent_hws,
|
||||
int num_parents)
|
||||
{
|
||||
struct clk_sam9x5_main *clkmain;
|
||||
struct clk_init_data init;
|
||||
struct clk_init_data init = {};
|
||||
unsigned int status;
|
||||
struct clk_hw *hw;
|
||||
int ret;
|
||||
|
|
@ -555,7 +564,7 @@ at91_clk_register_sam9x5_main(struct regmap *regmap,
|
|||
if (!name)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
if (!parent_names || !num_parents)
|
||||
if (!(parent_hws || parent_names) || !num_parents)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL);
|
||||
|
|
@ -564,7 +573,10 @@ at91_clk_register_sam9x5_main(struct regmap *regmap,
|
|||
|
||||
init.name = name;
|
||||
init.ops = &sam9x5_main_ops;
|
||||
init.parent_names = parent_names;
|
||||
if (parent_hws)
|
||||
init.parent_hws = (const struct clk_hw **)parent_hws;
|
||||
else
|
||||
init.parent_names = parent_names;
|
||||
init.num_parents = num_parents;
|
||||
init.flags = CLK_SET_PARENT_GATE;
|
||||
|
||||
|
|
|
|||
|
|
@ -473,18 +473,19 @@ static struct clk_hw * __init
|
|||
at91_clk_register_master_internal(struct regmap *regmap,
|
||||
const char *name, int num_parents,
|
||||
const char **parent_names,
|
||||
struct clk_hw **parent_hws,
|
||||
const struct clk_master_layout *layout,
|
||||
const struct clk_master_characteristics *characteristics,
|
||||
const struct clk_ops *ops, spinlock_t *lock, u32 flags)
|
||||
{
|
||||
struct clk_master *master;
|
||||
struct clk_init_data init;
|
||||
struct clk_init_data init = {};
|
||||
struct clk_hw *hw;
|
||||
unsigned int mckr;
|
||||
unsigned long irqflags;
|
||||
int ret;
|
||||
|
||||
if (!name || !num_parents || !parent_names || !lock)
|
||||
if (!name || !num_parents || !(parent_names || parent_hws) || !lock)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
master = kzalloc(sizeof(*master), GFP_KERNEL);
|
||||
|
|
@ -493,7 +494,10 @@ at91_clk_register_master_internal(struct regmap *regmap,
|
|||
|
||||
init.name = name;
|
||||
init.ops = ops;
|
||||
init.parent_names = parent_names;
|
||||
if (parent_hws)
|
||||
init.parent_hws = (const struct clk_hw **)parent_hws;
|
||||
else
|
||||
init.parent_names = parent_names;
|
||||
init.num_parents = num_parents;
|
||||
init.flags = flags;
|
||||
|
||||
|
|
@ -527,12 +531,13 @@ struct clk_hw * __init
|
|||
at91_clk_register_master_pres(struct regmap *regmap,
|
||||
const char *name, int num_parents,
|
||||
const char **parent_names,
|
||||
struct clk_hw **parent_hws,
|
||||
const struct clk_master_layout *layout,
|
||||
const struct clk_master_characteristics *characteristics,
|
||||
spinlock_t *lock)
|
||||
{
|
||||
return at91_clk_register_master_internal(regmap, name, num_parents,
|
||||
parent_names, layout,
|
||||
parent_names, parent_hws, layout,
|
||||
characteristics,
|
||||
&master_pres_ops,
|
||||
lock, CLK_SET_RATE_GATE);
|
||||
|
|
@ -541,7 +546,7 @@ at91_clk_register_master_pres(struct regmap *regmap,
|
|||
struct clk_hw * __init
|
||||
at91_clk_register_master_div(struct regmap *regmap,
|
||||
const char *name, const char *parent_name,
|
||||
const struct clk_master_layout *layout,
|
||||
struct clk_hw *parent_hw, const struct clk_master_layout *layout,
|
||||
const struct clk_master_characteristics *characteristics,
|
||||
spinlock_t *lock, u32 flags, u32 safe_div)
|
||||
{
|
||||
|
|
@ -554,7 +559,8 @@ at91_clk_register_master_div(struct regmap *regmap,
|
|||
ops = &master_div_ops_chg;
|
||||
|
||||
hw = at91_clk_register_master_internal(regmap, name, 1,
|
||||
&parent_name, layout,
|
||||
parent_name ? &parent_name : NULL,
|
||||
parent_hw ? &parent_hw : NULL, layout,
|
||||
characteristics, ops,
|
||||
lock, flags);
|
||||
|
||||
|
|
@ -806,18 +812,19 @@ struct clk_hw * __init
|
|||
at91_clk_sama7g5_register_master(struct regmap *regmap,
|
||||
const char *name, int num_parents,
|
||||
const char **parent_names,
|
||||
struct clk_hw **parent_hws,
|
||||
u32 *mux_table,
|
||||
spinlock_t *lock, u8 id,
|
||||
bool critical, int chg_pid)
|
||||
{
|
||||
struct clk_master *master;
|
||||
struct clk_hw *hw;
|
||||
struct clk_init_data init;
|
||||
struct clk_init_data init = {};
|
||||
unsigned long flags;
|
||||
unsigned int val;
|
||||
int ret;
|
||||
|
||||
if (!name || !num_parents || !parent_names || !mux_table ||
|
||||
if (!name || !num_parents || !(parent_names || parent_hws) || !mux_table ||
|
||||
!lock || id > MASTER_MAX_ID)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
|
|
@ -827,7 +834,10 @@ at91_clk_sama7g5_register_master(struct regmap *regmap,
|
|||
|
||||
init.name = name;
|
||||
init.ops = &sama7g5_master_ops;
|
||||
init.parent_names = parent_names;
|
||||
if (parent_hws)
|
||||
init.parent_hws = (const struct clk_hw **)parent_hws;
|
||||
else
|
||||
init.parent_names = parent_names;
|
||||
init.num_parents = num_parents;
|
||||
init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
|
||||
if (chg_pid >= 0)
|
||||
|
|
|
|||
|
|
@ -97,14 +97,15 @@ static const struct clk_ops peripheral_ops = {
|
|||
|
||||
struct clk_hw * __init
|
||||
at91_clk_register_peripheral(struct regmap *regmap, const char *name,
|
||||
const char *parent_name, u32 id)
|
||||
const char *parent_name, struct clk_hw *parent_hw,
|
||||
u32 id)
|
||||
{
|
||||
struct clk_peripheral *periph;
|
||||
struct clk_init_data init;
|
||||
struct clk_init_data init = {};
|
||||
struct clk_hw *hw;
|
||||
int ret;
|
||||
|
||||
if (!name || !parent_name || id > PERIPHERAL_ID_MAX)
|
||||
if (!name || !(parent_name || parent_hw) || id > PERIPHERAL_ID_MAX)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
periph = kzalloc(sizeof(*periph), GFP_KERNEL);
|
||||
|
|
@ -113,7 +114,10 @@ at91_clk_register_peripheral(struct regmap *regmap, const char *name,
|
|||
|
||||
init.name = name;
|
||||
init.ops = &peripheral_ops;
|
||||
init.parent_names = &parent_name;
|
||||
if (parent_hw)
|
||||
init.parent_hws = (const struct clk_hw **)&parent_hw;
|
||||
else
|
||||
init.parent_names = &parent_name;
|
||||
init.num_parents = 1;
|
||||
init.flags = 0;
|
||||
|
||||
|
|
@ -444,15 +448,16 @@ struct clk_hw * __init
|
|||
at91_clk_register_sam9x5_peripheral(struct regmap *regmap, spinlock_t *lock,
|
||||
const struct clk_pcr_layout *layout,
|
||||
const char *name, const char *parent_name,
|
||||
struct clk_hw *parent_hw,
|
||||
u32 id, const struct clk_range *range,
|
||||
int chg_pid, unsigned long flags)
|
||||
{
|
||||
struct clk_sam9x5_peripheral *periph;
|
||||
struct clk_init_data init;
|
||||
struct clk_init_data init = {};
|
||||
struct clk_hw *hw;
|
||||
int ret;
|
||||
|
||||
if (!name || !parent_name)
|
||||
if (!name || !(parent_name || parent_hw))
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
periph = kzalloc(sizeof(*periph), GFP_KERNEL);
|
||||
|
|
@ -460,7 +465,10 @@ at91_clk_register_sam9x5_peripheral(struct regmap *regmap, spinlock_t *lock,
|
|||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
init.name = name;
|
||||
init.parent_names = &parent_name;
|
||||
if (parent_hw)
|
||||
init.parent_hws = (const struct clk_hw **)&parent_hw;
|
||||
else
|
||||
init.parent_names = &parent_name;
|
||||
init.num_parents = 1;
|
||||
init.flags = flags;
|
||||
if (chg_pid < 0) {
|
||||
|
|
|
|||
|
|
@ -215,16 +215,16 @@ static const struct clk_ops programmable_ops = {
|
|||
struct clk_hw * __init
|
||||
at91_clk_register_programmable(struct regmap *regmap,
|
||||
const char *name, const char **parent_names,
|
||||
u8 num_parents, u8 id,
|
||||
struct clk_hw **parent_hws, u8 num_parents, u8 id,
|
||||
const struct clk_programmable_layout *layout,
|
||||
u32 *mux_table)
|
||||
{
|
||||
struct clk_programmable *prog;
|
||||
struct clk_hw *hw;
|
||||
struct clk_init_data init;
|
||||
struct clk_init_data init = {};
|
||||
int ret;
|
||||
|
||||
if (id > PROG_ID_MAX)
|
||||
if (id > PROG_ID_MAX || !(parent_names || parent_hws))
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
prog = kzalloc(sizeof(*prog), GFP_KERNEL);
|
||||
|
|
@ -233,7 +233,10 @@ at91_clk_register_programmable(struct regmap *regmap,
|
|||
|
||||
init.name = name;
|
||||
init.ops = &programmable_ops;
|
||||
init.parent_names = parent_names;
|
||||
if (parent_hws)
|
||||
init.parent_hws = (const struct clk_hw **)parent_hws;
|
||||
else
|
||||
init.parent_names = parent_names;
|
||||
init.num_parents = num_parents;
|
||||
init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
|
||||
|
||||
|
|
|
|||
|
|
@ -616,7 +616,7 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
|
|||
{
|
||||
struct sam9x60_frac *frac;
|
||||
struct clk_hw *hw;
|
||||
struct clk_init_data init;
|
||||
struct clk_init_data init = {};
|
||||
unsigned long parent_rate, irqflags;
|
||||
unsigned int val;
|
||||
int ret;
|
||||
|
|
@ -629,7 +629,10 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
|
|||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
init.name = name;
|
||||
init.parent_names = &parent_name;
|
||||
if (parent_name)
|
||||
init.parent_names = &parent_name;
|
||||
else
|
||||
init.parent_hws = (const struct clk_hw **)&parent_hw;
|
||||
init.num_parents = 1;
|
||||
if (flags & CLK_SET_RATE_GATE)
|
||||
init.ops = &sam9x60_frac_pll_ops;
|
||||
|
|
@ -692,14 +695,15 @@ free:
|
|||
|
||||
struct clk_hw * __init
|
||||
sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
|
||||
const char *name, const char *parent_name, u8 id,
|
||||
const char *name, const char *parent_name,
|
||||
struct clk_hw *parent_hw, u8 id,
|
||||
const struct clk_pll_characteristics *characteristics,
|
||||
const struct clk_pll_layout *layout, u32 flags,
|
||||
u32 safe_div)
|
||||
{
|
||||
struct sam9x60_div *div;
|
||||
struct clk_hw *hw;
|
||||
struct clk_init_data init;
|
||||
struct clk_init_data init = {};
|
||||
unsigned long irqflags;
|
||||
unsigned int val;
|
||||
int ret;
|
||||
|
|
@ -716,7 +720,10 @@ sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
|
|||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
init.name = name;
|
||||
init.parent_names = &parent_name;
|
||||
if (parent_hw)
|
||||
init.parent_hws = (const struct clk_hw **)&parent_hw;
|
||||
else
|
||||
init.parent_names = &parent_name;
|
||||
init.num_parents = 1;
|
||||
if (flags & CLK_SET_RATE_GATE)
|
||||
init.ops = &sam9x60_div_pll_ops;
|
||||
|
|
|
|||
|
|
@ -105,14 +105,15 @@ static const struct clk_ops system_ops = {
|
|||
|
||||
struct clk_hw * __init
|
||||
at91_clk_register_system(struct regmap *regmap, const char *name,
|
||||
const char *parent_name, u8 id, unsigned long flags)
|
||||
const char *parent_name, struct clk_hw *parent_hw, u8 id,
|
||||
unsigned long flags)
|
||||
{
|
||||
struct clk_system *sys;
|
||||
struct clk_hw *hw;
|
||||
struct clk_init_data init;
|
||||
struct clk_init_data init = {};
|
||||
int ret;
|
||||
|
||||
if (!parent_name || id > SYSTEM_MAX_ID)
|
||||
if (!(parent_name || parent_hw) || id > SYSTEM_MAX_ID)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
sys = kzalloc(sizeof(*sys), GFP_KERNEL);
|
||||
|
|
@ -121,7 +122,10 @@ at91_clk_register_system(struct regmap *regmap, const char *name,
|
|||
|
||||
init.name = name;
|
||||
init.ops = &system_ops;
|
||||
init.parent_names = &parent_name;
|
||||
if (parent_hw)
|
||||
init.parent_hws = (const struct clk_hw **)&parent_hw;
|
||||
else
|
||||
init.parent_names = &parent_name;
|
||||
init.num_parents = 1;
|
||||
init.flags = CLK_SET_RATE_PARENT | flags;
|
||||
|
||||
|
|
|
|||
|
|
@ -144,21 +144,30 @@ static struct clk_hw * __init
|
|||
at91_clk_register_utmi_internal(struct regmap *regmap_pmc,
|
||||
struct regmap *regmap_sfr,
|
||||
const char *name, const char *parent_name,
|
||||
struct clk_hw *parent_hw,
|
||||
const struct clk_ops *ops, unsigned long flags)
|
||||
{
|
||||
struct clk_utmi *utmi;
|
||||
struct clk_hw *hw;
|
||||
struct clk_init_data init;
|
||||
struct clk_init_data init = {};
|
||||
int ret;
|
||||
|
||||
if (!(parent_name || parent_hw))
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
utmi = kzalloc(sizeof(*utmi), GFP_KERNEL);
|
||||
if (!utmi)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
init.name = name;
|
||||
init.ops = ops;
|
||||
init.parent_names = parent_name ? &parent_name : NULL;
|
||||
init.num_parents = parent_name ? 1 : 0;
|
||||
if (parent_hw) {
|
||||
init.parent_hws = parent_hw ? (const struct clk_hw **)&parent_hw : NULL;
|
||||
init.num_parents = parent_hw ? 1 : 0;
|
||||
} else {
|
||||
init.parent_names = parent_name ? &parent_name : NULL;
|
||||
init.num_parents = parent_name ? 1 : 0;
|
||||
}
|
||||
init.flags = flags;
|
||||
|
||||
utmi->hw.init = &init;
|
||||
|
|
@ -177,10 +186,11 @@ at91_clk_register_utmi_internal(struct regmap *regmap_pmc,
|
|||
|
||||
struct clk_hw * __init
|
||||
at91_clk_register_utmi(struct regmap *regmap_pmc, struct regmap *regmap_sfr,
|
||||
const char *name, const char *parent_name)
|
||||
const char *name, const char *parent_name,
|
||||
struct clk_hw *parent_hw)
|
||||
{
|
||||
return at91_clk_register_utmi_internal(regmap_pmc, regmap_sfr, name,
|
||||
parent_name, &utmi_ops, CLK_SET_RATE_GATE);
|
||||
parent_name, parent_hw, &utmi_ops, CLK_SET_RATE_GATE);
|
||||
}
|
||||
|
||||
static int clk_utmi_sama7g5_prepare(struct clk_hw *hw)
|
||||
|
|
@ -279,8 +289,8 @@ static const struct clk_ops sama7g5_utmi_ops = {
|
|||
|
||||
struct clk_hw * __init
|
||||
at91_clk_sama7g5_register_utmi(struct regmap *regmap_pmc, const char *name,
|
||||
const char *parent_name)
|
||||
const char *parent_name, struct clk_hw *parent_hw)
|
||||
{
|
||||
return at91_clk_register_utmi_internal(regmap_pmc, NULL, name,
|
||||
parent_name, &sama7g5_utmi_ops, 0);
|
||||
parent_name, parent_hw, &sama7g5_utmi_ops, 0);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -171,7 +171,7 @@ static void __init of_sama5d2_clk_generated_setup(struct device_node *np)
|
|||
|
||||
hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
|
||||
&dt_pcr_layout, name,
|
||||
parent_names, NULL,
|
||||
parent_names, NULL, NULL,
|
||||
num_parents, id, &range,
|
||||
chg_pid);
|
||||
if (IS_ERR(hw))
|
||||
|
|
@ -269,7 +269,7 @@ static void __init of_at91rm9200_clk_main_osc_setup(struct device_node *np)
|
|||
if (IS_ERR(regmap))
|
||||
return;
|
||||
|
||||
hw = at91_clk_register_main_osc(regmap, name, parent_name, bypass);
|
||||
hw = at91_clk_register_main_osc(regmap, name, parent_name, NULL, bypass);
|
||||
if (IS_ERR(hw))
|
||||
return;
|
||||
|
||||
|
|
@ -323,7 +323,7 @@ static void __init of_at91rm9200_clk_main_setup(struct device_node *np)
|
|||
if (IS_ERR(regmap))
|
||||
return;
|
||||
|
||||
hw = at91_clk_register_rm9200_main(regmap, name, parent_name);
|
||||
hw = at91_clk_register_rm9200_main(regmap, name, parent_name, NULL);
|
||||
if (IS_ERR(hw))
|
||||
return;
|
||||
|
||||
|
|
@ -354,7 +354,7 @@ static void __init of_at91sam9x5_clk_main_setup(struct device_node *np)
|
|||
|
||||
of_property_read_string(np, "clock-output-names", &name);
|
||||
|
||||
hw = at91_clk_register_sam9x5_main(regmap, name, parent_names,
|
||||
hw = at91_clk_register_sam9x5_main(regmap, name, parent_names, NULL,
|
||||
num_parents);
|
||||
if (IS_ERR(hw))
|
||||
return;
|
||||
|
|
@ -420,12 +420,12 @@ of_at91_clk_master_setup(struct device_node *np,
|
|||
return;
|
||||
|
||||
hw = at91_clk_register_master_pres(regmap, "masterck_pres", num_parents,
|
||||
parent_names, layout,
|
||||
parent_names, NULL, layout,
|
||||
characteristics, &mck_lock);
|
||||
if (IS_ERR(hw))
|
||||
goto out_free_characteristics;
|
||||
|
||||
hw = at91_clk_register_master_div(regmap, name, "masterck_pres",
|
||||
hw = at91_clk_register_master_div(regmap, name, "masterck_pres", NULL,
|
||||
layout, characteristics,
|
||||
&mck_lock, CLK_SET_RATE_GATE, 0);
|
||||
if (IS_ERR(hw))
|
||||
|
|
@ -490,7 +490,7 @@ of_at91_clk_periph_setup(struct device_node *np, u8 type)
|
|||
|
||||
if (type == PERIPHERAL_AT91RM9200) {
|
||||
hw = at91_clk_register_peripheral(regmap, name,
|
||||
parent_name, id);
|
||||
parent_name, NULL, id);
|
||||
} else {
|
||||
struct clk_range range = CLK_RANGE(0, 0);
|
||||
unsigned long flags = 0;
|
||||
|
|
@ -512,6 +512,7 @@ of_at91_clk_periph_setup(struct device_node *np, u8 type)
|
|||
&dt_pcr_layout,
|
||||
name,
|
||||
parent_name,
|
||||
NULL,
|
||||
id, &range,
|
||||
INT_MIN,
|
||||
flags);
|
||||
|
|
@ -769,7 +770,7 @@ of_at91_clk_prog_setup(struct device_node *np,
|
|||
name = progclknp->name;
|
||||
|
||||
hw = at91_clk_register_programmable(regmap, name,
|
||||
parent_names, num_parents,
|
||||
parent_names, NULL, num_parents,
|
||||
id, layout, mux_table);
|
||||
if (IS_ERR(hw))
|
||||
continue;
|
||||
|
|
@ -907,8 +908,8 @@ static void __init of_at91rm9200_clk_sys_setup(struct device_node *np)
|
|||
if (!strcmp(sysclknp->name, "ddrck"))
|
||||
flags = CLK_IS_CRITICAL;
|
||||
|
||||
hw = at91_clk_register_system(regmap, name, parent_name, id,
|
||||
flags);
|
||||
hw = at91_clk_register_system(regmap, name, parent_name, NULL,
|
||||
id, flags);
|
||||
if (IS_ERR(hw))
|
||||
continue;
|
||||
|
||||
|
|
@ -1054,7 +1055,7 @@ static void __init of_at91sam9x5_clk_utmi_setup(struct device_node *np)
|
|||
regmap_sfr = NULL;
|
||||
}
|
||||
|
||||
hw = at91_clk_register_utmi(regmap_pmc, regmap_sfr, name, parent_name);
|
||||
hw = at91_clk_register_utmi(regmap_pmc, regmap_sfr, name, parent_name, NULL);
|
||||
if (IS_ERR(hw))
|
||||
return;
|
||||
|
||||
|
|
|
|||
|
|
@ -144,7 +144,8 @@ struct clk_hw * __init
|
|||
at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,
|
||||
const struct clk_pcr_layout *layout,
|
||||
const char *name, const char **parent_names,
|
||||
u32 *mux_table, u8 num_parents, u8 id,
|
||||
struct clk_hw **parent_hws, u32 *mux_table,
|
||||
u8 num_parents, u8 id,
|
||||
const struct clk_range *range, int chg_pid);
|
||||
|
||||
struct clk_hw * __init
|
||||
|
|
@ -161,25 +162,29 @@ at91_clk_register_main_rc_osc(struct regmap *regmap, const char *name,
|
|||
u32 frequency, u32 accuracy);
|
||||
struct clk_hw * __init
|
||||
at91_clk_register_main_osc(struct regmap *regmap, const char *name,
|
||||
const char *parent_name, bool bypass);
|
||||
const char *parent_name,
|
||||
struct clk_parent_data *parent_data, bool bypass);
|
||||
struct clk_hw * __init
|
||||
at91_clk_register_rm9200_main(struct regmap *regmap,
|
||||
const char *name,
|
||||
const char *parent_name);
|
||||
const char *parent_name,
|
||||
struct clk_hw *parent_hw);
|
||||
struct clk_hw * __init
|
||||
at91_clk_register_sam9x5_main(struct regmap *regmap, const char *name,
|
||||
const char **parent_names, int num_parents);
|
||||
const char **parent_names,
|
||||
struct clk_hw **parent_hws, int num_parents);
|
||||
|
||||
struct clk_hw * __init
|
||||
at91_clk_register_master_pres(struct regmap *regmap, const char *name,
|
||||
int num_parents, const char **parent_names,
|
||||
struct clk_hw **parent_hws,
|
||||
const struct clk_master_layout *layout,
|
||||
const struct clk_master_characteristics *characteristics,
|
||||
spinlock_t *lock);
|
||||
|
||||
struct clk_hw * __init
|
||||
at91_clk_register_master_div(struct regmap *regmap, const char *name,
|
||||
const char *parent_names,
|
||||
const char *parent_names, struct clk_hw *parent_hw,
|
||||
const struct clk_master_layout *layout,
|
||||
const struct clk_master_characteristics *characteristics,
|
||||
spinlock_t *lock, u32 flags, u32 safe_div);
|
||||
|
|
@ -187,17 +192,20 @@ at91_clk_register_master_div(struct regmap *regmap, const char *name,
|
|||
struct clk_hw * __init
|
||||
at91_clk_sama7g5_register_master(struct regmap *regmap,
|
||||
const char *name, int num_parents,
|
||||
const char **parent_names, u32 *mux_table,
|
||||
const char **parent_names,
|
||||
struct clk_hw **parent_hws, u32 *mux_table,
|
||||
spinlock_t *lock, u8 id, bool critical,
|
||||
int chg_pid);
|
||||
|
||||
struct clk_hw * __init
|
||||
at91_clk_register_peripheral(struct regmap *regmap, const char *name,
|
||||
const char *parent_name, u32 id);
|
||||
const char *parent_name, struct clk_hw *parent_hw,
|
||||
u32 id);
|
||||
struct clk_hw * __init
|
||||
at91_clk_register_sam9x5_peripheral(struct regmap *regmap, spinlock_t *lock,
|
||||
const struct clk_pcr_layout *layout,
|
||||
const char *name, const char *parent_name,
|
||||
struct clk_hw *parent_hw,
|
||||
u32 id, const struct clk_range *range,
|
||||
int chg_pid, unsigned long flags);
|
||||
|
||||
|
|
@ -212,7 +220,8 @@ at91_clk_register_plldiv(struct regmap *regmap, const char *name,
|
|||
|
||||
struct clk_hw * __init
|
||||
sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
|
||||
const char *name, const char *parent_name, u8 id,
|
||||
const char *name, const char *parent_name,
|
||||
struct clk_hw *parent_hw, u8 id,
|
||||
const struct clk_pll_characteristics *characteristics,
|
||||
const struct clk_pll_layout *layout, u32 flags,
|
||||
u32 safe_div);
|
||||
|
|
@ -226,7 +235,8 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
|
|||
|
||||
struct clk_hw * __init
|
||||
at91_clk_register_programmable(struct regmap *regmap, const char *name,
|
||||
const char **parent_names, u8 num_parents, u8 id,
|
||||
const char **parent_names, struct clk_hw **parent_hws,
|
||||
u8 num_parents, u8 id,
|
||||
const struct clk_programmable_layout *layout,
|
||||
u32 *mux_table);
|
||||
|
||||
|
|
@ -242,7 +252,8 @@ at91sam9x5_clk_register_smd(struct regmap *regmap, const char *name,
|
|||
|
||||
struct clk_hw * __init
|
||||
at91_clk_register_system(struct regmap *regmap, const char *name,
|
||||
const char *parent_name, u8 id, unsigned long flags);
|
||||
const char *parent_name, struct clk_hw *parent_hw,
|
||||
u8 id, unsigned long flags);
|
||||
|
||||
struct clk_hw * __init
|
||||
at91sam9x5_clk_register_usb(struct regmap *regmap, const char *name,
|
||||
|
|
@ -259,10 +270,11 @@ at91rm9200_clk_register_usb(struct regmap *regmap, const char *name,
|
|||
|
||||
struct clk_hw * __init
|
||||
at91_clk_register_utmi(struct regmap *regmap_pmc, struct regmap *regmap_sfr,
|
||||
const char *name, const char *parent_name);
|
||||
const char *name, const char *parent_name,
|
||||
struct clk_hw *parent_hw);
|
||||
|
||||
struct clk_hw * __init
|
||||
at91_clk_sama7g5_register_utmi(struct regmap *regmap, const char *name,
|
||||
const char *parent_name);
|
||||
const char *parent_name, struct clk_hw *parent_hw);
|
||||
|
||||
#endif /* __PMC_H_ */
|
||||
|
|
|
|||
|
|
@ -219,14 +219,14 @@ static void __init sam9x60_pmc_setup(struct device_node *np)
|
|||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
||||
hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, 0);
|
||||
hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL, 0);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
main_osc_hw = hw;
|
||||
|
||||
parent_names[0] = "main_rc_osc";
|
||||
parent_names[1] = "main_osc";
|
||||
hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
|
||||
hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL, 2);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
||||
|
|
@ -246,7 +246,7 @@ static void __init sam9x60_pmc_setup(struct device_node *np)
|
|||
goto err_free;
|
||||
|
||||
hw = sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, "pllack_divck",
|
||||
"pllack_fracck", 0, &plla_characteristics,
|
||||
"pllack_fracck", NULL, 0, &plla_characteristics,
|
||||
&pll_div_layout,
|
||||
/*
|
||||
* This feeds CPU. It should not
|
||||
|
|
@ -266,7 +266,7 @@ static void __init sam9x60_pmc_setup(struct device_node *np)
|
|||
goto err_free;
|
||||
|
||||
hw = sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, "upllck_divck",
|
||||
"upllck_fracck", 1, &upll_characteristics,
|
||||
"upllck_fracck", NULL, 1, &upll_characteristics,
|
||||
&pll_div_layout,
|
||||
CLK_SET_RATE_GATE |
|
||||
CLK_SET_PARENT_GATE |
|
||||
|
|
@ -280,13 +280,13 @@ static void __init sam9x60_pmc_setup(struct device_node *np)
|
|||
parent_names[1] = "mainck";
|
||||
parent_names[2] = "pllack_divck";
|
||||
hw = at91_clk_register_master_pres(regmap, "masterck_pres", 3,
|
||||
parent_names, &sam9x60_master_layout,
|
||||
parent_names, NULL, &sam9x60_master_layout,
|
||||
&mck_characteristics, &mck_lock);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
||||
hw = at91_clk_register_master_div(regmap, "masterck_div",
|
||||
"masterck_pres", &sam9x60_master_layout,
|
||||
"masterck_pres", NULL, &sam9x60_master_layout,
|
||||
&mck_characteristics, &mck_lock,
|
||||
CLK_SET_RATE_GATE, 0);
|
||||
if (IS_ERR(hw))
|
||||
|
|
@ -313,7 +313,7 @@ static void __init sam9x60_pmc_setup(struct device_node *np)
|
|||
snprintf(name, sizeof(name), "prog%d", i);
|
||||
|
||||
hw = at91_clk_register_programmable(regmap, name,
|
||||
parent_names, 6, i,
|
||||
parent_names, NULL, 6, i,
|
||||
&sam9x60_programmable_layout,
|
||||
NULL);
|
||||
if (IS_ERR(hw))
|
||||
|
|
@ -324,7 +324,7 @@ static void __init sam9x60_pmc_setup(struct device_node *np)
|
|||
|
||||
for (i = 0; i < ARRAY_SIZE(sam9x60_systemck); i++) {
|
||||
hw = at91_clk_register_system(regmap, sam9x60_systemck[i].n,
|
||||
sam9x60_systemck[i].p,
|
||||
sam9x60_systemck[i].p, NULL,
|
||||
sam9x60_systemck[i].id,
|
||||
sam9x60_systemck[i].flags);
|
||||
if (IS_ERR(hw))
|
||||
|
|
@ -337,7 +337,7 @@ static void __init sam9x60_pmc_setup(struct device_node *np)
|
|||
hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
|
||||
&sam9x60_pcr_layout,
|
||||
sam9x60_periphck[i].n,
|
||||
"masterck_div",
|
||||
"masterck_div", NULL,
|
||||
sam9x60_periphck[i].id,
|
||||
&range, INT_MIN,
|
||||
sam9x60_periphck[i].flags);
|
||||
|
|
@ -351,7 +351,7 @@ static void __init sam9x60_pmc_setup(struct device_node *np)
|
|||
hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
|
||||
&sam9x60_pcr_layout,
|
||||
sam9x60_gck[i].n,
|
||||
parent_names, NULL, 6,
|
||||
parent_names, NULL, NULL, 6,
|
||||
sam9x60_gck[i].id,
|
||||
&sam9x60_gck[i].r, INT_MIN);
|
||||
if (IS_ERR(hw))
|
||||
|
|
|
|||
|
|
@ -202,14 +202,14 @@ static void __init sama5d2_pmc_setup(struct device_node *np)
|
|||
|
||||
bypass = of_property_read_bool(np, "atmel,osc-bypass");
|
||||
|
||||
hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
|
||||
hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL,
|
||||
bypass);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
||||
parent_names[0] = "main_rc_osc";
|
||||
parent_names[1] = "main_osc";
|
||||
hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
|
||||
hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL, 2);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
||||
|
|
@ -249,7 +249,7 @@ static void __init sama5d2_pmc_setup(struct device_node *np)
|
|||
if (IS_ERR(regmap_sfr))
|
||||
regmap_sfr = NULL;
|
||||
|
||||
hw = at91_clk_register_utmi(regmap, regmap_sfr, "utmick", "mainck");
|
||||
hw = at91_clk_register_utmi(regmap, regmap_sfr, "utmick", "mainck", NULL);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
||||
|
|
@ -260,14 +260,14 @@ static void __init sama5d2_pmc_setup(struct device_node *np)
|
|||
parent_names[2] = "plladivck";
|
||||
parent_names[3] = "utmick";
|
||||
hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
|
||||
parent_names,
|
||||
parent_names, NULL,
|
||||
&at91sam9x5_master_layout,
|
||||
&mck_characteristics, &mck_lock);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
||||
hw = at91_clk_register_master_div(regmap, "masterck_div",
|
||||
"masterck_pres",
|
||||
"masterck_pres", NULL,
|
||||
&at91sam9x5_master_layout,
|
||||
&mck_characteristics, &mck_lock,
|
||||
CLK_SET_RATE_GATE, 0);
|
||||
|
|
@ -300,7 +300,7 @@ static void __init sama5d2_pmc_setup(struct device_node *np)
|
|||
snprintf(name, sizeof(name), "prog%d", i);
|
||||
|
||||
hw = at91_clk_register_programmable(regmap, name,
|
||||
parent_names, 6, i,
|
||||
parent_names, NULL, 6, i,
|
||||
&sama5d2_programmable_layout,
|
||||
NULL);
|
||||
if (IS_ERR(hw))
|
||||
|
|
@ -311,7 +311,7 @@ static void __init sama5d2_pmc_setup(struct device_node *np)
|
|||
|
||||
for (i = 0; i < ARRAY_SIZE(sama5d2_systemck); i++) {
|
||||
hw = at91_clk_register_system(regmap, sama5d2_systemck[i].n,
|
||||
sama5d2_systemck[i].p,
|
||||
sama5d2_systemck[i].p, NULL,
|
||||
sama5d2_systemck[i].id,
|
||||
sama5d2_systemck[i].flags);
|
||||
if (IS_ERR(hw))
|
||||
|
|
@ -324,7 +324,7 @@ static void __init sama5d2_pmc_setup(struct device_node *np)
|
|||
hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
|
||||
&sama5d2_pcr_layout,
|
||||
sama5d2_periphck[i].n,
|
||||
"masterck_div",
|
||||
"masterck_div", NULL,
|
||||
sama5d2_periphck[i].id,
|
||||
&range, INT_MIN,
|
||||
sama5d2_periphck[i].flags);
|
||||
|
|
@ -338,7 +338,7 @@ static void __init sama5d2_pmc_setup(struct device_node *np)
|
|||
hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
|
||||
&sama5d2_pcr_layout,
|
||||
sama5d2_periph32ck[i].n,
|
||||
"h32mxck",
|
||||
"h32mxck", NULL,
|
||||
sama5d2_periph32ck[i].id,
|
||||
&sama5d2_periph32ck[i].r,
|
||||
INT_MIN, 0);
|
||||
|
|
@ -358,7 +358,7 @@ static void __init sama5d2_pmc_setup(struct device_node *np)
|
|||
hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
|
||||
&sama5d2_pcr_layout,
|
||||
sama5d2_gck[i].n,
|
||||
parent_names, NULL, 6,
|
||||
parent_names, NULL, NULL, 6,
|
||||
sama5d2_gck[i].id,
|
||||
&sama5d2_gck[i].r,
|
||||
sama5d2_gck[i].chg_pid);
|
||||
|
|
|
|||
|
|
@ -150,14 +150,14 @@ static void __init sama5d3_pmc_setup(struct device_node *np)
|
|||
|
||||
bypass = of_property_read_bool(np, "atmel,osc-bypass");
|
||||
|
||||
hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
|
||||
hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL,
|
||||
bypass);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
||||
parent_names[0] = "main_rc_osc";
|
||||
parent_names[1] = "main_osc";
|
||||
hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
|
||||
hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL, 2);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
||||
|
|
@ -172,7 +172,7 @@ static void __init sama5d3_pmc_setup(struct device_node *np)
|
|||
|
||||
sama5d3_pmc->chws[PMC_PLLACK] = hw;
|
||||
|
||||
hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck");
|
||||
hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck", NULL);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
||||
|
|
@ -183,14 +183,14 @@ static void __init sama5d3_pmc_setup(struct device_node *np)
|
|||
parent_names[2] = "plladivck";
|
||||
parent_names[3] = "utmick";
|
||||
hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
|
||||
parent_names,
|
||||
parent_names, NULL,
|
||||
&at91sam9x5_master_layout,
|
||||
&mck_characteristics, &mck_lock);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
||||
hw = at91_clk_register_master_div(regmap, "masterck_div",
|
||||
"masterck_pres",
|
||||
"masterck_pres", NULL,
|
||||
&at91sam9x5_master_layout,
|
||||
&mck_characteristics, &mck_lock,
|
||||
CLK_SET_RATE_GATE, 0);
|
||||
|
|
@ -220,7 +220,7 @@ static void __init sama5d3_pmc_setup(struct device_node *np)
|
|||
snprintf(name, sizeof(name), "prog%d", i);
|
||||
|
||||
hw = at91_clk_register_programmable(regmap, name,
|
||||
parent_names, 5, i,
|
||||
parent_names, NULL, 5, i,
|
||||
&at91sam9x5_programmable_layout,
|
||||
NULL);
|
||||
if (IS_ERR(hw))
|
||||
|
|
@ -231,7 +231,7 @@ static void __init sama5d3_pmc_setup(struct device_node *np)
|
|||
|
||||
for (i = 0; i < ARRAY_SIZE(sama5d3_systemck); i++) {
|
||||
hw = at91_clk_register_system(regmap, sama5d3_systemck[i].n,
|
||||
sama5d3_systemck[i].p,
|
||||
sama5d3_systemck[i].p, NULL,
|
||||
sama5d3_systemck[i].id,
|
||||
sama5d3_systemck[i].flags);
|
||||
if (IS_ERR(hw))
|
||||
|
|
@ -244,7 +244,7 @@ static void __init sama5d3_pmc_setup(struct device_node *np)
|
|||
hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
|
||||
&sama5d3_pcr_layout,
|
||||
sama5d3_periphck[i].n,
|
||||
"masterck_div",
|
||||
"masterck_div", NULL,
|
||||
sama5d3_periphck[i].id,
|
||||
&sama5d3_periphck[i].r,
|
||||
INT_MIN,
|
||||
|
|
|
|||
|
|
@ -165,14 +165,14 @@ static void __init sama5d4_pmc_setup(struct device_node *np)
|
|||
|
||||
bypass = of_property_read_bool(np, "atmel,osc-bypass");
|
||||
|
||||
hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
|
||||
hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL,
|
||||
bypass);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
||||
parent_names[0] = "main_rc_osc";
|
||||
parent_names[1] = "main_osc";
|
||||
hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
|
||||
hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL, 2);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
||||
|
|
@ -187,7 +187,7 @@ static void __init sama5d4_pmc_setup(struct device_node *np)
|
|||
|
||||
sama5d4_pmc->chws[PMC_PLLACK] = hw;
|
||||
|
||||
hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck");
|
||||
hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck", NULL);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
||||
|
|
@ -198,14 +198,14 @@ static void __init sama5d4_pmc_setup(struct device_node *np)
|
|||
parent_names[2] = "plladivck";
|
||||
parent_names[3] = "utmick";
|
||||
hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
|
||||
parent_names,
|
||||
parent_names, NULL,
|
||||
&at91sam9x5_master_layout,
|
||||
&mck_characteristics, &mck_lock);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
||||
hw = at91_clk_register_master_div(regmap, "masterck_div",
|
||||
"masterck_pres",
|
||||
"masterck_pres", NULL,
|
||||
&at91sam9x5_master_layout,
|
||||
&mck_characteristics, &mck_lock,
|
||||
CLK_SET_RATE_GATE, 0);
|
||||
|
|
@ -243,7 +243,7 @@ static void __init sama5d4_pmc_setup(struct device_node *np)
|
|||
snprintf(name, sizeof(name), "prog%d", i);
|
||||
|
||||
hw = at91_clk_register_programmable(regmap, name,
|
||||
parent_names, 5, i,
|
||||
parent_names, NULL, 5, i,
|
||||
&at91sam9x5_programmable_layout,
|
||||
NULL);
|
||||
if (IS_ERR(hw))
|
||||
|
|
@ -254,7 +254,7 @@ static void __init sama5d4_pmc_setup(struct device_node *np)
|
|||
|
||||
for (i = 0; i < ARRAY_SIZE(sama5d4_systemck); i++) {
|
||||
hw = at91_clk_register_system(regmap, sama5d4_systemck[i].n,
|
||||
sama5d4_systemck[i].p,
|
||||
sama5d4_systemck[i].p, NULL,
|
||||
sama5d4_systemck[i].id,
|
||||
sama5d4_systemck[i].flags);
|
||||
if (IS_ERR(hw))
|
||||
|
|
@ -267,7 +267,7 @@ static void __init sama5d4_pmc_setup(struct device_node *np)
|
|||
hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
|
||||
&sama5d4_pcr_layout,
|
||||
sama5d4_periphck[i].n,
|
||||
"masterck_div",
|
||||
"masterck_div", NULL,
|
||||
sama5d4_periphck[i].id,
|
||||
&range, INT_MIN,
|
||||
sama5d4_periphck[i].flags);
|
||||
|
|
@ -281,7 +281,7 @@ static void __init sama5d4_pmc_setup(struct device_node *np)
|
|||
hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
|
||||
&sama5d4_pcr_layout,
|
||||
sama5d4_periph32ck[i].n,
|
||||
"h32mxck",
|
||||
"h32mxck", NULL,
|
||||
sama5d4_periph32ck[i].id,
|
||||
&range, INT_MIN, 0);
|
||||
if (IS_ERR(hw))
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -117,17 +117,17 @@ static const struct clk_ops slow_osc_ops = {
|
|||
static struct clk_hw * __init
|
||||
at91_clk_register_slow_osc(void __iomem *sckcr,
|
||||
const char *name,
|
||||
const char *parent_name,
|
||||
const struct clk_parent_data *parent_data,
|
||||
unsigned long startup,
|
||||
bool bypass,
|
||||
const struct clk_slow_bits *bits)
|
||||
{
|
||||
struct clk_slow_osc *osc;
|
||||
struct clk_hw *hw;
|
||||
struct clk_init_data init;
|
||||
struct clk_init_data init = {};
|
||||
int ret;
|
||||
|
||||
if (!sckcr || !name || !parent_name)
|
||||
if (!sckcr || !name || !parent_data)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
osc = kzalloc(sizeof(*osc), GFP_KERNEL);
|
||||
|
|
@ -136,7 +136,7 @@ at91_clk_register_slow_osc(void __iomem *sckcr,
|
|||
|
||||
init.name = name;
|
||||
init.ops = &slow_osc_ops;
|
||||
init.parent_names = &parent_name;
|
||||
init.parent_data = parent_data;
|
||||
init.num_parents = 1;
|
||||
init.flags = CLK_IGNORE_UNUSED;
|
||||
|
||||
|
|
@ -318,16 +318,16 @@ static const struct clk_ops sam9x5_slow_ops = {
|
|||
static struct clk_hw * __init
|
||||
at91_clk_register_sam9x5_slow(void __iomem *sckcr,
|
||||
const char *name,
|
||||
const char **parent_names,
|
||||
const struct clk_hw **parent_hws,
|
||||
int num_parents,
|
||||
const struct clk_slow_bits *bits)
|
||||
{
|
||||
struct clk_sam9x5_slow *slowck;
|
||||
struct clk_hw *hw;
|
||||
struct clk_init_data init;
|
||||
struct clk_init_data init = {};
|
||||
int ret;
|
||||
|
||||
if (!sckcr || !name || !parent_names || !num_parents)
|
||||
if (!sckcr || !name || !parent_hws || !num_parents)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
slowck = kzalloc(sizeof(*slowck), GFP_KERNEL);
|
||||
|
|
@ -336,7 +336,7 @@ at91_clk_register_sam9x5_slow(void __iomem *sckcr,
|
|||
|
||||
init.name = name;
|
||||
init.ops = &sam9x5_slow_ops;
|
||||
init.parent_names = parent_names;
|
||||
init.parent_hws = parent_hws;
|
||||
init.num_parents = num_parents;
|
||||
init.flags = 0;
|
||||
|
||||
|
|
@ -367,18 +367,21 @@ static void __init at91sam9x5_sckc_register(struct device_node *np,
|
|||
unsigned int rc_osc_startup_us,
|
||||
const struct clk_slow_bits *bits)
|
||||
{
|
||||
const char *parent_names[2] = { "slow_rc_osc", "slow_osc" };
|
||||
void __iomem *regbase = of_iomap(np, 0);
|
||||
struct device_node *child = NULL;
|
||||
const char *xtal_name;
|
||||
struct clk_hw *slow_rc, *slow_osc, *slowck;
|
||||
static struct clk_parent_data parent_data = {
|
||||
.name = "slow_xtal",
|
||||
};
|
||||
const struct clk_hw *parent_hws[2];
|
||||
bool bypass;
|
||||
int ret;
|
||||
|
||||
if (!regbase)
|
||||
return;
|
||||
|
||||
slow_rc = at91_clk_register_slow_rc_osc(regbase, parent_names[0],
|
||||
slow_rc = at91_clk_register_slow_rc_osc(regbase, "slow_rc_osc",
|
||||
32768, 50000000,
|
||||
rc_osc_startup_us, bits);
|
||||
if (IS_ERR(slow_rc))
|
||||
|
|
@ -402,12 +405,16 @@ static void __init at91sam9x5_sckc_register(struct device_node *np,
|
|||
if (!xtal_name)
|
||||
goto unregister_slow_rc;
|
||||
|
||||
slow_osc = at91_clk_register_slow_osc(regbase, parent_names[1],
|
||||
xtal_name, 1200000, bypass, bits);
|
||||
parent_data.fw_name = xtal_name;
|
||||
|
||||
slow_osc = at91_clk_register_slow_osc(regbase, "slow_osc",
|
||||
&parent_data, 1200000, bypass, bits);
|
||||
if (IS_ERR(slow_osc))
|
||||
goto unregister_slow_rc;
|
||||
|
||||
slowck = at91_clk_register_sam9x5_slow(regbase, "slowck", parent_names,
|
||||
parent_hws[0] = slow_rc;
|
||||
parent_hws[1] = slow_osc;
|
||||
slowck = at91_clk_register_sam9x5_slow(regbase, "slowck", parent_hws,
|
||||
2, bits);
|
||||
if (IS_ERR(slowck))
|
||||
goto unregister_slow_osc;
|
||||
|
|
@ -465,14 +472,17 @@ static void __init of_sam9x60_sckc_setup(struct device_node *np)
|
|||
struct clk_hw_onecell_data *clk_data;
|
||||
struct clk_hw *slow_rc, *slow_osc;
|
||||
const char *xtal_name;
|
||||
const char *parent_names[2] = { "slow_rc_osc", "slow_osc" };
|
||||
const struct clk_hw *parent_hws[2];
|
||||
static struct clk_parent_data parent_data = {
|
||||
.name = "slow_xtal",
|
||||
};
|
||||
bool bypass;
|
||||
int ret;
|
||||
|
||||
if (!regbase)
|
||||
return;
|
||||
|
||||
slow_rc = clk_hw_register_fixed_rate_with_accuracy(NULL, parent_names[0],
|
||||
slow_rc = clk_hw_register_fixed_rate_with_accuracy(NULL, "slow_rc_osc",
|
||||
NULL, 0, 32768,
|
||||
93750000);
|
||||
if (IS_ERR(slow_rc))
|
||||
|
|
@ -482,9 +492,10 @@ static void __init of_sam9x60_sckc_setup(struct device_node *np)
|
|||
if (!xtal_name)
|
||||
goto unregister_slow_rc;
|
||||
|
||||
parent_data.fw_name = xtal_name;
|
||||
bypass = of_property_read_bool(np, "atmel,osc-bypass");
|
||||
slow_osc = at91_clk_register_slow_osc(regbase, parent_names[1],
|
||||
xtal_name, 5000000, bypass,
|
||||
slow_osc = at91_clk_register_slow_osc(regbase, "slow_osc",
|
||||
&parent_data, 5000000, bypass,
|
||||
&at91sam9x60_bits);
|
||||
if (IS_ERR(slow_osc))
|
||||
goto unregister_slow_rc;
|
||||
|
|
@ -495,14 +506,16 @@ static void __init of_sam9x60_sckc_setup(struct device_node *np)
|
|||
|
||||
/* MD_SLCK and TD_SLCK. */
|
||||
clk_data->num = 2;
|
||||
clk_data->hws[0] = clk_hw_register_fixed_rate(NULL, "md_slck",
|
||||
parent_names[0],
|
||||
0, 32768);
|
||||
clk_data->hws[0] = clk_hw_register_fixed_rate_parent_hw(NULL, "md_slck",
|
||||
slow_rc,
|
||||
0, 32768);
|
||||
if (IS_ERR(clk_data->hws[0]))
|
||||
goto clk_data_free;
|
||||
|
||||
parent_hws[0] = slow_rc;
|
||||
parent_hws[1] = slow_osc;
|
||||
clk_data->hws[1] = at91_clk_register_sam9x5_slow(regbase, "td_slck",
|
||||
parent_names, 2,
|
||||
parent_hws, 2,
|
||||
&at91sam9x60_bits);
|
||||
if (IS_ERR(clk_data->hws[1]))
|
||||
goto unregister_md_slck;
|
||||
|
|
@ -573,30 +586,36 @@ static void __init of_sama5d4_sckc_setup(struct device_node *np)
|
|||
void __iomem *regbase = of_iomap(np, 0);
|
||||
struct clk_hw *slow_rc, *slowck;
|
||||
struct clk_sama5d4_slow_osc *osc;
|
||||
struct clk_init_data init;
|
||||
struct clk_init_data init = {};
|
||||
const char *xtal_name;
|
||||
const char *parent_names[2] = { "slow_rc_osc", "slow_osc" };
|
||||
const struct clk_hw *parent_hws[2];
|
||||
static struct clk_parent_data parent_data = {
|
||||
.name = "slow_xtal",
|
||||
};
|
||||
int ret;
|
||||
|
||||
if (!regbase)
|
||||
return;
|
||||
|
||||
slow_rc = clk_hw_register_fixed_rate_with_accuracy(NULL,
|
||||
parent_names[0],
|
||||
"slow_rc_osc",
|
||||
NULL, 0, 32768,
|
||||
250000000);
|
||||
if (IS_ERR(slow_rc))
|
||||
return;
|
||||
|
||||
xtal_name = of_clk_get_parent_name(np, 0);
|
||||
if (!xtal_name)
|
||||
goto unregister_slow_rc;
|
||||
parent_data.fw_name = xtal_name;
|
||||
|
||||
osc = kzalloc(sizeof(*osc), GFP_KERNEL);
|
||||
if (!osc)
|
||||
goto unregister_slow_rc;
|
||||
|
||||
init.name = parent_names[1];
|
||||
init.name = "slow_osc";
|
||||
init.ops = &sama5d4_slow_osc_ops;
|
||||
init.parent_names = &xtal_name;
|
||||
init.parent_data = &parent_data;
|
||||
init.num_parents = 1;
|
||||
init.flags = CLK_IGNORE_UNUSED;
|
||||
|
||||
|
|
@ -609,8 +628,10 @@ static void __init of_sama5d4_sckc_setup(struct device_node *np)
|
|||
if (ret)
|
||||
goto free_slow_osc_data;
|
||||
|
||||
parent_hws[0] = slow_rc;
|
||||
parent_hws[1] = &osc->hw;
|
||||
slowck = at91_clk_register_sam9x5_slow(regbase, "slowck",
|
||||
parent_names, 2,
|
||||
parent_hws, 2,
|
||||
&at91sama5d4_bits);
|
||||
if (IS_ERR(slowck))
|
||||
goto unregister_slow_osc;
|
||||
|
|
|
|||
|
|
@ -57,6 +57,7 @@ config QCOM_CLK_APCC_MSM8996
|
|||
config QCOM_CLK_APCS_SDX55
|
||||
tristate "SDX55 and SDX65 APCS Clock Controller"
|
||||
depends on QCOM_APCS_IPC || COMPILE_TEST
|
||||
depends on ARM || COMPILE_TEST
|
||||
help
|
||||
Support for the APCS Clock Controller on SDX55, SDX65 platforms. The
|
||||
APCS is managing the mux and divider which feeds the CPUs.
|
||||
|
|
@ -100,6 +101,7 @@ config QCOM_CLK_RPMH
|
|||
|
||||
config APQ_GCC_8084
|
||||
tristate "APQ8084 Global Clock Controller"
|
||||
depends on ARM || COMPILE_TEST
|
||||
select QCOM_GDSC
|
||||
help
|
||||
Support for the global clock controller on apq8084 devices.
|
||||
|
|
@ -108,6 +110,7 @@ config APQ_GCC_8084
|
|||
|
||||
config APQ_MMCC_8084
|
||||
tristate "APQ8084 Multimedia Clock Controller"
|
||||
depends on ARM || COMPILE_TEST
|
||||
select APQ_GCC_8084
|
||||
select QCOM_GDSC
|
||||
help
|
||||
|
|
@ -159,6 +162,7 @@ config IPQ_GCC_6018
|
|||
|
||||
config IPQ_GCC_806X
|
||||
tristate "IPQ806x Global Clock Controller"
|
||||
depends on ARM || COMPILE_TEST
|
||||
help
|
||||
Support for the global clock controller on ipq806x devices.
|
||||
Say Y if you want to use peripheral devices such as UART, SPI,
|
||||
|
|
@ -166,6 +170,7 @@ config IPQ_GCC_806X
|
|||
|
||||
config IPQ_LCC_806X
|
||||
tristate "IPQ806x LPASS Clock Controller"
|
||||
depends on ARM || COMPILE_TEST
|
||||
select IPQ_GCC_806X
|
||||
help
|
||||
Support for the LPASS clock controller on ipq806x devices.
|
||||
|
|
@ -191,6 +196,7 @@ config IPQ_GCC_9574
|
|||
|
||||
config MSM_GCC_8660
|
||||
tristate "MSM8660 Global Clock Controller"
|
||||
depends on ARM || COMPILE_TEST
|
||||
help
|
||||
Support for the global clock controller on msm8660 devices.
|
||||
Say Y if you want to use peripheral devices such as UART, SPI,
|
||||
|
|
@ -198,6 +204,7 @@ config MSM_GCC_8660
|
|||
|
||||
config MSM_GCC_8909
|
||||
tristate "MSM8909 Global Clock Controller"
|
||||
depends on ARM || COMPILE_TEST
|
||||
select QCOM_GDSC
|
||||
help
|
||||
Support for the global clock controller on msm8909 devices.
|
||||
|
|
@ -232,6 +239,7 @@ config MSM_GCC_8939
|
|||
|
||||
config MSM_GCC_8960
|
||||
tristate "APQ8064/MSM8960 Global Clock Controller"
|
||||
depends on ARM || COMPILE_TEST
|
||||
help
|
||||
Support for the global clock controller on apq8064/msm8960 devices.
|
||||
Say Y if you want to use peripheral devices such as UART, SPI,
|
||||
|
|
@ -239,6 +247,7 @@ config MSM_GCC_8960
|
|||
|
||||
config MSM_LCC_8960
|
||||
tristate "APQ8064/MSM8960 LPASS Clock Controller"
|
||||
depends on ARM || COMPILE_TEST
|
||||
select MSM_GCC_8960
|
||||
help
|
||||
Support for the LPASS clock controller on apq8064/msm8960 devices.
|
||||
|
|
@ -247,6 +256,7 @@ config MSM_LCC_8960
|
|||
|
||||
config MDM_GCC_9607
|
||||
tristate "MDM9607 Global Clock Controller"
|
||||
depends on ARM || COMPILE_TEST
|
||||
help
|
||||
Support for the global clock controller on mdm9607 devices.
|
||||
Say Y if you want to use peripheral devices such as UART, SPI,
|
||||
|
|
@ -254,6 +264,7 @@ config MDM_GCC_9607
|
|||
|
||||
config MDM_GCC_9615
|
||||
tristate "MDM9615 Global Clock Controller"
|
||||
depends on ARM || COMPILE_TEST
|
||||
help
|
||||
Support for the global clock controller on mdm9615 devices.
|
||||
Say Y if you want to use peripheral devices such as UART, SPI,
|
||||
|
|
@ -261,6 +272,7 @@ config MDM_GCC_9615
|
|||
|
||||
config MDM_LCC_9615
|
||||
tristate "MDM9615 LPASS Clock Controller"
|
||||
depends on ARM || COMPILE_TEST
|
||||
select MDM_GCC_9615
|
||||
help
|
||||
Support for the LPASS clock controller on mdm9615 devices.
|
||||
|
|
@ -269,6 +281,7 @@ config MDM_LCC_9615
|
|||
|
||||
config MSM_MMCC_8960
|
||||
tristate "MSM8960 Multimedia Clock Controller"
|
||||
depends on ARM || COMPILE_TEST
|
||||
select MSM_GCC_8960
|
||||
help
|
||||
Support for the multimedia clock controller on msm8960 devices.
|
||||
|
|
@ -285,6 +298,7 @@ config MSM_GCC_8953
|
|||
|
||||
config MSM_GCC_8974
|
||||
tristate "MSM8974 Global Clock Controller"
|
||||
depends on ARM || COMPILE_TEST
|
||||
select QCOM_GDSC
|
||||
help
|
||||
Support for the global clock controller on msm8974 devices.
|
||||
|
|
@ -293,6 +307,7 @@ config MSM_GCC_8974
|
|||
|
||||
config MSM_MMCC_8974
|
||||
tristate "MSM8974 Multimedia Clock Controller"
|
||||
depends on ARM || COMPILE_TEST
|
||||
select MSM_GCC_8974
|
||||
select QCOM_GDSC
|
||||
help
|
||||
|
|
@ -393,6 +408,7 @@ config QCS_GCC_404
|
|||
|
||||
config SC_CAMCC_7180
|
||||
tristate "SC7180 Camera Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select SC_GCC_7180
|
||||
help
|
||||
Support for the camera clock controller on Qualcomm Technologies, Inc
|
||||
|
|
@ -402,6 +418,7 @@ config SC_CAMCC_7180
|
|||
|
||||
config SC_CAMCC_7280
|
||||
tristate "SC7280 Camera Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select SC_GCC_7280
|
||||
help
|
||||
Support for the camera clock controller on Qualcomm Technologies, Inc
|
||||
|
|
@ -411,6 +428,7 @@ config SC_CAMCC_7280
|
|||
|
||||
config SC_DISPCC_7180
|
||||
tristate "SC7180 Display Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select SC_GCC_7180
|
||||
help
|
||||
Support for the display clock controller on Qualcomm Technologies, Inc
|
||||
|
|
@ -420,6 +438,7 @@ config SC_DISPCC_7180
|
|||
|
||||
config SC_DISPCC_7280
|
||||
tristate "SC7280 Display Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select SC_GCC_7280
|
||||
help
|
||||
Support for the display clock controller on Qualcomm Technologies, Inc.
|
||||
|
|
@ -429,6 +448,7 @@ config SC_DISPCC_7280
|
|||
|
||||
config SC_DISPCC_8280XP
|
||||
tristate "SC8280XP Display Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select SC_GCC_8280XP
|
||||
help
|
||||
Support for the two display clock controllers on Qualcomm
|
||||
|
|
@ -458,6 +478,7 @@ config SC_GCC_7180
|
|||
tristate "SC7180 Global Clock Controller"
|
||||
select QCOM_GDSC
|
||||
depends on COMMON_CLK_QCOM
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
help
|
||||
Support for the global clock controller on SC7180 devices.
|
||||
Say Y if you want to use peripheral devices such as UART, SPI,
|
||||
|
|
@ -467,6 +488,7 @@ config SC_GCC_7280
|
|||
tristate "SC7280 Global Clock Controller"
|
||||
select QCOM_GDSC
|
||||
depends on COMMON_CLK_QCOM
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
help
|
||||
Support for the global clock controller on SC7280 devices.
|
||||
Say Y if you want to use peripheral devices such as UART, SPI,
|
||||
|
|
@ -476,6 +498,7 @@ config SC_GCC_8180X
|
|||
tristate "SC8180X Global Clock Controller"
|
||||
select QCOM_GDSC
|
||||
depends on COMMON_CLK_QCOM
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
help
|
||||
Support for the global clock controller on SC8180X devices.
|
||||
Say Y if you want to use peripheral devices such as UART, SPI,
|
||||
|
|
@ -485,6 +508,7 @@ config SC_GCC_8280XP
|
|||
tristate "SC8280XP Global Clock Controller"
|
||||
select QCOM_GDSC
|
||||
depends on COMMON_CLK_QCOM
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
help
|
||||
Support for the global clock controller on SC8280XP devices.
|
||||
Say Y if you want to use peripheral devices such as UART, SPI,
|
||||
|
|
@ -492,6 +516,7 @@ config SC_GCC_8280XP
|
|||
|
||||
config SC_GPUCC_7180
|
||||
tristate "SC7180 Graphics Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select SC_GCC_7180
|
||||
help
|
||||
Support for the graphics clock controller on SC7180 devices.
|
||||
|
|
@ -500,6 +525,7 @@ config SC_GPUCC_7180
|
|||
|
||||
config SC_GPUCC_7280
|
||||
tristate "SC7280 Graphics Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select SC_GCC_7280
|
||||
help
|
||||
Support for the graphics clock controller on SC7280 devices.
|
||||
|
|
@ -508,6 +534,7 @@ config SC_GPUCC_7280
|
|||
|
||||
config SC_GPUCC_8280XP
|
||||
tristate "SC8280XP Graphics Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select SC_GCC_8280XP
|
||||
help
|
||||
Support for the graphics clock controller on SC8280XP devices.
|
||||
|
|
@ -516,14 +543,25 @@ config SC_GPUCC_8280XP
|
|||
|
||||
config SC_LPASSCC_7280
|
||||
tristate "SC7280 Low Power Audio Subsystem (LPASS) Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select SC_GCC_7280
|
||||
help
|
||||
Support for the LPASS clock controller on SC7280 devices.
|
||||
Say Y if you want to use the LPASS branch clocks of the LPASS clock
|
||||
controller to reset the LPASS subsystem.
|
||||
|
||||
config SC_LPASSCC_8280XP
|
||||
tristate "SC8280 Low Power Audio Subsystem (LPASS) Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select SC_GCC_8280XP
|
||||
help
|
||||
Support for the LPASS clock controller on SC8280XP devices.
|
||||
Say Y if you want to use the LPASS branch clocks of the LPASS clock
|
||||
controller to reset the LPASS subsystem.
|
||||
|
||||
config SC_LPASS_CORECC_7180
|
||||
tristate "SC7180 LPASS Core Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select SC_GCC_7180
|
||||
help
|
||||
Support for the LPASS(Low Power Audio Subsystem) core clock controller
|
||||
|
|
@ -533,6 +571,7 @@ config SC_LPASS_CORECC_7180
|
|||
|
||||
config SC_LPASS_CORECC_7280
|
||||
tristate "SC7280 LPASS Core & Audio Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select SC_GCC_7280
|
||||
select QCOM_GDSC
|
||||
help
|
||||
|
|
@ -543,6 +582,7 @@ config SC_LPASS_CORECC_7280
|
|||
|
||||
config SC_MSS_7180
|
||||
tristate "SC7180 Modem Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select SC_GCC_7180
|
||||
help
|
||||
Support for the Modem Subsystem clock controller on Qualcomm
|
||||
|
|
@ -552,6 +592,7 @@ config SC_MSS_7180
|
|||
|
||||
config SC_VIDEOCC_7180
|
||||
tristate "SC7180 Video Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select SC_GCC_7180
|
||||
help
|
||||
Support for the video clock controller on SC7180 devices.
|
||||
|
|
@ -560,6 +601,7 @@ config SC_VIDEOCC_7180
|
|||
|
||||
config SC_VIDEOCC_7280
|
||||
tristate "SC7280 Video Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select SC_GCC_7280
|
||||
help
|
||||
Support for the video clock controller on SC7280 devices.
|
||||
|
|
@ -568,6 +610,7 @@ config SC_VIDEOCC_7280
|
|||
|
||||
config SDM_CAMCC_845
|
||||
tristate "SDM845 Camera Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select SDM_GCC_845
|
||||
help
|
||||
Support for the camera clock controller on SDM845 devices.
|
||||
|
|
@ -575,6 +618,7 @@ config SDM_CAMCC_845
|
|||
|
||||
config SDM_GCC_660
|
||||
tristate "SDM660 Global Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select QCOM_GDSC
|
||||
help
|
||||
Support for the global clock controller on SDM660 devices.
|
||||
|
|
@ -583,6 +627,7 @@ config SDM_GCC_660
|
|||
|
||||
config SDM_MMCC_660
|
||||
tristate "SDM660 Multimedia Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select SDM_GCC_660
|
||||
select QCOM_GDSC
|
||||
help
|
||||
|
|
@ -592,6 +637,7 @@ config SDM_MMCC_660
|
|||
|
||||
config SDM_GPUCC_660
|
||||
tristate "SDM660 Graphics Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select SDM_GCC_660
|
||||
select QCOM_GDSC
|
||||
help
|
||||
|
|
@ -623,6 +669,7 @@ config QDU_GCC_1000
|
|||
|
||||
config SDM_GCC_845
|
||||
tristate "SDM845/SDM670 Global Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select QCOM_GDSC
|
||||
help
|
||||
Support for the global clock controller on SDM845 and SDM670 devices.
|
||||
|
|
@ -631,6 +678,7 @@ config SDM_GCC_845
|
|||
|
||||
config SDM_GPUCC_845
|
||||
tristate "SDM845 Graphics Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select SDM_GCC_845
|
||||
help
|
||||
Support for the graphics clock controller on SDM845 devices.
|
||||
|
|
@ -639,6 +687,7 @@ config SDM_GPUCC_845
|
|||
|
||||
config SDM_VIDEOCC_845
|
||||
tristate "SDM845 Video Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select SDM_GCC_845
|
||||
select QCOM_GDSC
|
||||
help
|
||||
|
|
@ -648,6 +697,7 @@ config SDM_VIDEOCC_845
|
|||
|
||||
config SDM_DISPCC_845
|
||||
tristate "SDM845 Display Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select SDM_GCC_845
|
||||
help
|
||||
Support for the display clock controller on Qualcomm Technologies, Inc
|
||||
|
|
@ -657,6 +707,7 @@ config SDM_DISPCC_845
|
|||
|
||||
config SDM_LPASSCC_845
|
||||
tristate "SDM845 Low Power Audio Subsystem (LPAAS) Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select SDM_GCC_845
|
||||
help
|
||||
Support for the LPASS clock controller on SDM845 devices.
|
||||
|
|
@ -665,6 +716,7 @@ config SDM_LPASSCC_845
|
|||
|
||||
config SDX_GCC_55
|
||||
tristate "SDX55 Global Clock Controller"
|
||||
depends on ARM || COMPILE_TEST
|
||||
select QCOM_GDSC
|
||||
help
|
||||
Support for the global clock controller on SDX55 devices.
|
||||
|
|
@ -673,14 +725,24 @@ config SDX_GCC_55
|
|||
|
||||
config SDX_GCC_65
|
||||
tristate "SDX65 Global Clock Controller"
|
||||
depends on ARM || COMPILE_TEST
|
||||
select QCOM_GDSC
|
||||
help
|
||||
Support for the global clock controller on SDX65 devices.
|
||||
Say Y if you want to use peripheral devices such as UART,
|
||||
SPI, I2C, USB, SD/UFS, PCIe etc.
|
||||
|
||||
config SDX_GCC_75
|
||||
tristate "SDX75 Global Clock Controller"
|
||||
select QCOM_GDSC
|
||||
help
|
||||
Support for the global clock controller on SDX75 devices.
|
||||
Say Y if you want to use peripheral devices such as UART,
|
||||
SPI, I2C, USB, SD/eMMC, PCIe etc.
|
||||
|
||||
config SM_CAMCC_6350
|
||||
tristate "SM6350 Camera Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select SM_GCC_6350
|
||||
help
|
||||
Support for the camera clock controller on SM6350 devices.
|
||||
|
|
@ -688,6 +750,7 @@ config SM_CAMCC_6350
|
|||
|
||||
config SM_CAMCC_8250
|
||||
tristate "SM8250 Camera Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select SM_GCC_8250
|
||||
help
|
||||
Support for the camera clock controller on SM8250 devices.
|
||||
|
|
@ -695,6 +758,7 @@ config SM_CAMCC_8250
|
|||
|
||||
config SM_CAMCC_8450
|
||||
tristate "SM8450 Camera Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select SM_GCC_8450
|
||||
help
|
||||
Support for the camera clock controller on SM8450 devices.
|
||||
|
|
@ -702,6 +766,7 @@ config SM_CAMCC_8450
|
|||
|
||||
config SM_DISPCC_6115
|
||||
tristate "SM6115 Display Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
depends on SM_GCC_6115
|
||||
help
|
||||
Support for the display clock controller on Qualcomm Technologies, Inc
|
||||
|
|
@ -711,6 +776,7 @@ config SM_DISPCC_6115
|
|||
|
||||
config SM_DISPCC_6125
|
||||
tristate "SM6125 Display Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
depends on SM_GCC_6125
|
||||
help
|
||||
Support for the display clock controller on Qualcomm Technologies, Inc
|
||||
|
|
@ -720,6 +786,7 @@ config SM_DISPCC_6125
|
|||
|
||||
config SM_DISPCC_8250
|
||||
tristate "SM8150/SM8250/SM8350 Display Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
depends on SM_GCC_8150 || SM_GCC_8250 || SM_GCC_8350
|
||||
help
|
||||
Support for the display clock controller on Qualcomm Technologies, Inc
|
||||
|
|
@ -729,6 +796,7 @@ config SM_DISPCC_8250
|
|||
|
||||
config SM_DISPCC_6350
|
||||
tristate "SM6350 Display Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
depends on SM_GCC_6350
|
||||
help
|
||||
Support for the display clock controller on Qualcomm Technologies, Inc
|
||||
|
|
@ -738,6 +806,7 @@ config SM_DISPCC_6350
|
|||
|
||||
config SM_DISPCC_6375
|
||||
tristate "SM6375 Display Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
depends on SM_GCC_6375
|
||||
help
|
||||
Support for the display clock controller on Qualcomm Technologies, Inc
|
||||
|
|
@ -747,6 +816,7 @@ config SM_DISPCC_6375
|
|||
|
||||
config SM_DISPCC_8450
|
||||
tristate "SM8450 Display Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
depends on SM_GCC_8450
|
||||
help
|
||||
Support for the display clock controller on Qualcomm Technologies, Inc
|
||||
|
|
@ -756,6 +826,7 @@ config SM_DISPCC_8450
|
|||
|
||||
config SM_DISPCC_8550
|
||||
tristate "SM8550 Display Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
depends on SM_GCC_8550
|
||||
help
|
||||
Support for the display clock controller on Qualcomm Technologies, Inc
|
||||
|
|
@ -765,6 +836,7 @@ config SM_DISPCC_8550
|
|||
|
||||
config SM_GCC_6115
|
||||
tristate "SM6115 and SM4250 Global Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select QCOM_GDSC
|
||||
help
|
||||
Support for the global clock controller on SM6115 and SM4250 devices.
|
||||
|
|
@ -773,6 +845,7 @@ config SM_GCC_6115
|
|||
|
||||
config SM_GCC_6125
|
||||
tristate "SM6125 Global Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
help
|
||||
Support for the global clock controller on SM6125 devices.
|
||||
Say Y if you want to use peripheral devices such as UART,
|
||||
|
|
@ -780,6 +853,7 @@ config SM_GCC_6125
|
|||
|
||||
config SM_GCC_6350
|
||||
tristate "SM6350 Global Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select QCOM_GDSC
|
||||
help
|
||||
Support for the global clock controller on SM6350 devices.
|
||||
|
|
@ -788,6 +862,7 @@ config SM_GCC_6350
|
|||
|
||||
config SM_GCC_6375
|
||||
tristate "SM6375 Global Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select QCOM_GDSC
|
||||
help
|
||||
Support for the global clock controller on SM6375 devices.
|
||||
|
|
@ -804,6 +879,7 @@ config SM_GCC_7150
|
|||
|
||||
config SM_GCC_8150
|
||||
tristate "SM8150 Global Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
help
|
||||
Support for the global clock controller on SM8150 devices.
|
||||
Say Y if you want to use peripheral devices such as UART,
|
||||
|
|
@ -811,6 +887,7 @@ config SM_GCC_8150
|
|||
|
||||
config SM_GCC_8250
|
||||
tristate "SM8250 Global Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select QCOM_GDSC
|
||||
help
|
||||
Support for the global clock controller on SM8250 devices.
|
||||
|
|
@ -819,6 +896,7 @@ config SM_GCC_8250
|
|||
|
||||
config SM_GCC_8350
|
||||
tristate "SM8350 Global Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select QCOM_GDSC
|
||||
help
|
||||
Support for the global clock controller on SM8350 devices.
|
||||
|
|
@ -827,6 +905,7 @@ config SM_GCC_8350
|
|||
|
||||
config SM_GCC_8450
|
||||
tristate "SM8450 Global Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select QCOM_GDSC
|
||||
help
|
||||
Support for the global clock controller on SM8450 devices.
|
||||
|
|
@ -835,6 +914,7 @@ config SM_GCC_8450
|
|||
|
||||
config SM_GCC_8550
|
||||
tristate "SM8550 Global Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select QCOM_GDSC
|
||||
help
|
||||
Support for the global clock controller on SM8550 devices.
|
||||
|
|
@ -870,6 +950,7 @@ config SM_GPUCC_6375
|
|||
|
||||
config SM_GPUCC_6350
|
||||
tristate "SM6350 Graphics Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select SM_GCC_6350
|
||||
help
|
||||
Support for the graphics clock controller on SM6350 devices.
|
||||
|
|
@ -878,6 +959,7 @@ config SM_GPUCC_6350
|
|||
|
||||
config SM_GPUCC_8150
|
||||
tristate "SM8150 Graphics Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select SM_GCC_8150
|
||||
help
|
||||
Support for the graphics clock controller on SM8150 devices.
|
||||
|
|
@ -886,6 +968,7 @@ config SM_GPUCC_8150
|
|||
|
||||
config SM_GPUCC_8250
|
||||
tristate "SM8250 Graphics Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select SM_GCC_8250
|
||||
help
|
||||
Support for the graphics clock controller on SM8250 devices.
|
||||
|
|
@ -894,14 +977,32 @@ config SM_GPUCC_8250
|
|||
|
||||
config SM_GPUCC_8350
|
||||
tristate "SM8350 Graphics Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select SM_GCC_8350
|
||||
help
|
||||
Support for the graphics clock controller on SM8350 devices.
|
||||
Say Y if you want to support graphics controller devices and
|
||||
functionality such as 3D graphics.
|
||||
|
||||
config SM_GPUCC_8450
|
||||
tristate "SM8450 Graphics Clock Controller"
|
||||
select SM_GCC_8450
|
||||
help
|
||||
Support for the graphics clock controller on SM8450 devices.
|
||||
Say Y if you want to support graphics controller devices and
|
||||
functionality such as 3D graphics.
|
||||
|
||||
config SM_GPUCC_8550
|
||||
tristate "SM8550 Graphics Clock Controller"
|
||||
select SM_GCC_8550
|
||||
help
|
||||
Support for the graphics clock controller on SM8550 devices.
|
||||
Say Y if you want to support graphics controller devices and
|
||||
functionality such as 3D graphics.
|
||||
|
||||
config SM_TCSRCC_8550
|
||||
tristate "SM8550 TCSR Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select QCOM_GDSC
|
||||
help
|
||||
Support for the TCSR clock controller on SM8550 devices.
|
||||
|
|
@ -909,6 +1010,7 @@ config SM_TCSRCC_8550
|
|||
|
||||
config SM_VIDEOCC_8150
|
||||
tristate "SM8150 Video Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select SM_GCC_8150
|
||||
select QCOM_GDSC
|
||||
help
|
||||
|
|
@ -918,6 +1020,7 @@ config SM_VIDEOCC_8150
|
|||
|
||||
config SM_VIDEOCC_8250
|
||||
tristate "SM8250 Video Clock Controller"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select SM_GCC_8250
|
||||
select QCOM_GDSC
|
||||
help
|
||||
|
|
@ -925,6 +1028,25 @@ config SM_VIDEOCC_8250
|
|||
Say Y if you want to support video devices and functionality such as
|
||||
video encode and decode.
|
||||
|
||||
config SM_VIDEOCC_8350
|
||||
tristate "SM8350 Video Clock Controller"
|
||||
select SM_GCC_8350
|
||||
select QCOM_GDSC
|
||||
help
|
||||
Support for the video clock controller on SM8350 devices.
|
||||
Say Y if you want to support video devices and functionality such as
|
||||
video encode and decode.
|
||||
|
||||
config SM_VIDEOCC_8550
|
||||
tristate "SM8550 Video Clock Controller"
|
||||
select SM_GCC_8550
|
||||
select QCOM_GDSC
|
||||
help
|
||||
Support for the video clock controller on Qualcomm Technologies, Inc.
|
||||
SM8550 devices.
|
||||
Say Y if you want to support video devices and functionality such as
|
||||
video encode/decode.
|
||||
|
||||
config SPMI_PMIC_CLKDIV
|
||||
tristate "SPMI PMIC clkdiv Support"
|
||||
depends on SPMI || COMPILE_TEST
|
||||
|
|
@ -958,8 +1080,18 @@ config KRAITCC
|
|||
|
||||
config CLK_GFM_LPASS_SM8250
|
||||
tristate "SM8250 GFM LPASS Clocks"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
help
|
||||
Support for the Glitch Free Mux (GFM) Low power audio
|
||||
subsystem (LPASS) clocks found on SM8250 SoCs.
|
||||
|
||||
config SM_VIDEOCC_8450
|
||||
tristate "SM8450 Video Clock Controller"
|
||||
select SM_GCC_8450
|
||||
select QCOM_GDSC
|
||||
help
|
||||
Support for the video clock controller on Qualcomm Technologies, Inc.
|
||||
SM8450 devices.
|
||||
Say Y if you want to support video devices and functionality such as
|
||||
video encode/decode.
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -81,6 +81,7 @@ obj-$(CONFIG_SC_GPUCC_7180) += gpucc-sc7180.o
|
|||
obj-$(CONFIG_SC_GPUCC_7280) += gpucc-sc7280.o
|
||||
obj-$(CONFIG_SC_GPUCC_8280XP) += gpucc-sc8280xp.o
|
||||
obj-$(CONFIG_SC_LPASSCC_7280) += lpasscc-sc7280.o
|
||||
obj-$(CONFIG_SC_LPASSCC_8280XP) += lpasscc-sc8280xp.o
|
||||
obj-$(CONFIG_SC_LPASS_CORECC_7180) += lpasscorecc-sc7180.o
|
||||
obj-$(CONFIG_SC_LPASS_CORECC_7280) += lpasscorecc-sc7280.o lpassaudiocc-sc7280.o
|
||||
obj-$(CONFIG_SC_MSS_7180) += mss-sc7180.o
|
||||
|
|
@ -97,6 +98,7 @@ obj-$(CONFIG_SDM_LPASSCC_845) += lpasscc-sdm845.o
|
|||
obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
|
||||
obj-$(CONFIG_SDX_GCC_55) += gcc-sdx55.o
|
||||
obj-$(CONFIG_SDX_GCC_65) += gcc-sdx65.o
|
||||
obj-$(CONFIG_SDX_GCC_75) += gcc-sdx75.o
|
||||
obj-$(CONFIG_SM_CAMCC_6350) += camcc-sm6350.o
|
||||
obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o
|
||||
obj-$(CONFIG_SM_CAMCC_8450) += camcc-sm8450.o
|
||||
|
|
@ -124,9 +126,14 @@ obj-$(CONFIG_SM_GPUCC_6375) += gpucc-sm6375.o
|
|||
obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o
|
||||
obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o
|
||||
obj-$(CONFIG_SM_GPUCC_8350) += gpucc-sm8350.o
|
||||
obj-$(CONFIG_SM_GPUCC_8450) += gpucc-sm8450.o
|
||||
obj-$(CONFIG_SM_GPUCC_8550) += gpucc-sm8550.o
|
||||
obj-$(CONFIG_SM_TCSRCC_8550) += tcsrcc-sm8550.o
|
||||
obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o
|
||||
obj-$(CONFIG_SM_VIDEOCC_8250) += videocc-sm8250.o
|
||||
obj-$(CONFIG_SM_VIDEOCC_8350) += videocc-sm8350.o
|
||||
obj-$(CONFIG_SM_VIDEOCC_8450) += videocc-sm8450.o
|
||||
obj-$(CONFIG_SM_VIDEOCC_8550) += videocc-sm8550.o
|
||||
obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
|
||||
obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
|
||||
obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
|
||||
|
|
|
|||
|
|
@ -111,6 +111,18 @@ static const struct alpha_pll_config ipq8074_pll_config = {
|
|||
.test_ctl_hi_val = 0x4000,
|
||||
};
|
||||
|
||||
static const struct alpha_pll_config ipq9574_pll_config = {
|
||||
.l = 0x3b,
|
||||
.config_ctl_val = 0x200d4828,
|
||||
.config_ctl_hi_val = 0x6,
|
||||
.early_output_mask = BIT(3),
|
||||
.aux2_output_mask = BIT(2),
|
||||
.aux_output_mask = BIT(1),
|
||||
.main_output_mask = BIT(0),
|
||||
.test_ctl_val = 0x0,
|
||||
.test_ctl_hi_val = 0x4000,
|
||||
};
|
||||
|
||||
struct apss_pll_data {
|
||||
int pll_type;
|
||||
struct clk_alpha_pll *pll;
|
||||
|
|
@ -135,6 +147,12 @@ static struct apss_pll_data ipq6018_pll_data = {
|
|||
.pll_config = &ipq6018_pll_config,
|
||||
};
|
||||
|
||||
static struct apss_pll_data ipq9574_pll_data = {
|
||||
.pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA,
|
||||
.pll = &ipq_pll_huayra,
|
||||
.pll_config = &ipq9574_pll_config,
|
||||
};
|
||||
|
||||
static const struct regmap_config ipq_pll_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
|
|
@ -180,6 +198,7 @@ static const struct of_device_id apss_ipq_pll_match_table[] = {
|
|||
{ .compatible = "qcom,ipq5332-a53pll", .data = &ipq5332_pll_data },
|
||||
{ .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_data },
|
||||
{ .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_data },
|
||||
{ .compatible = "qcom,ipq9574-a73pll", .data = &ipq9574_pll_data },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, apss_ipq_pll_match_table);
|
||||
|
|
|
|||
|
|
@ -1480,12 +1480,21 @@ static struct clk_branch cam_cc_sys_tmr_clk = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct gdsc titan_top_gdsc = {
|
||||
.gdscr = 0xb134,
|
||||
.pd = {
|
||||
.name = "titan_top_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
};
|
||||
|
||||
static struct gdsc bps_gdsc = {
|
||||
.gdscr = 0x6004,
|
||||
.pd = {
|
||||
.name = "bps_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.parent = &titan_top_gdsc.pd,
|
||||
.flags = HW_CTRL,
|
||||
};
|
||||
|
||||
|
|
@ -1495,6 +1504,7 @@ static struct gdsc ife_0_gdsc = {
|
|||
.name = "ife_0_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.parent = &titan_top_gdsc.pd,
|
||||
};
|
||||
|
||||
static struct gdsc ife_1_gdsc = {
|
||||
|
|
@ -1503,6 +1513,7 @@ static struct gdsc ife_1_gdsc = {
|
|||
.name = "ife_1_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.parent = &titan_top_gdsc.pd,
|
||||
};
|
||||
|
||||
static struct gdsc ipe_0_gdsc = {
|
||||
|
|
@ -1512,15 +1523,9 @@ static struct gdsc ipe_0_gdsc = {
|
|||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = HW_CTRL,
|
||||
.parent = &titan_top_gdsc.pd,
|
||||
};
|
||||
|
||||
static struct gdsc titan_top_gdsc = {
|
||||
.gdscr = 0xb134,
|
||||
.pd = {
|
||||
.name = "titan_top_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
};
|
||||
|
||||
static struct clk_hw *cam_cc_sc7180_hws[] = {
|
||||
[CAM_CC_PLL2_OUT_EARLY] = &cam_cc_pll2_out_early.hw,
|
||||
|
|
|
|||
|
|
@ -55,6 +55,7 @@
|
|||
#define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
|
||||
#define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
|
||||
#define PLL_TEST_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1])
|
||||
#define PLL_TEST_CTL_U2(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U2])
|
||||
#define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS])
|
||||
#define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE])
|
||||
#define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC])
|
||||
|
|
@ -383,10 +384,21 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
|
|||
|
||||
regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
|
||||
|
||||
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
|
||||
config->test_ctl_val);
|
||||
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
|
||||
config->test_ctl_hi_val);
|
||||
if (config->test_ctl_mask)
|
||||
regmap_update_bits(regmap, PLL_TEST_CTL(pll),
|
||||
config->test_ctl_mask,
|
||||
config->test_ctl_val);
|
||||
else
|
||||
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
|
||||
config->test_ctl_val);
|
||||
|
||||
if (config->test_ctl_hi_mask)
|
||||
regmap_update_bits(regmap, PLL_TEST_CTL_U(pll),
|
||||
config->test_ctl_hi_mask,
|
||||
config->test_ctl_hi_val);
|
||||
else
|
||||
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
|
||||
config->test_ctl_hi_val);
|
||||
|
||||
if (pll->flags & SUPPORTS_FSM_MODE)
|
||||
qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
|
||||
|
|
@ -2096,6 +2108,7 @@ void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regma
|
|||
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
|
||||
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
|
||||
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
|
||||
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val);
|
||||
|
||||
/* Disable PLL output */
|
||||
regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
|
||||
|
|
|
|||
|
|
@ -123,8 +123,11 @@ struct alpha_pll_config {
|
|||
u32 user_ctl_hi_val;
|
||||
u32 user_ctl_hi1_val;
|
||||
u32 test_ctl_val;
|
||||
u32 test_ctl_mask;
|
||||
u32 test_ctl_hi_val;
|
||||
u32 test_ctl_hi_mask;
|
||||
u32 test_ctl_hi1_val;
|
||||
u32 test_ctl_hi2_val;
|
||||
u32 main_output_mask;
|
||||
u32 aux_output_mask;
|
||||
u32 aux2_output_mask;
|
||||
|
|
|
|||
|
|
@ -43,6 +43,7 @@ static bool clk_branch2_check_halt(const struct clk_branch *br, bool enabling)
|
|||
{
|
||||
u32 val;
|
||||
u32 mask;
|
||||
bool invert = (br->halt_check == BRANCH_HALT_ENABLE);
|
||||
|
||||
mask = CBCR_NOC_FSM_STATUS;
|
||||
mask |= CBCR_CLK_OFF;
|
||||
|
|
@ -51,11 +52,10 @@ static bool clk_branch2_check_halt(const struct clk_branch *br, bool enabling)
|
|||
|
||||
if (enabling) {
|
||||
val &= mask;
|
||||
return (val & CBCR_CLK_OFF) == 0 ||
|
||||
return (val & CBCR_CLK_OFF) == (invert ? CBCR_CLK_OFF : 0) ||
|
||||
FIELD_GET(CBCR_NOC_FSM_STATUS, val) == FSM_STATUS_ON;
|
||||
} else {
|
||||
return val & CBCR_CLK_OFF;
|
||||
}
|
||||
return (val & CBCR_CLK_OFF) == (invert ? 0 : CBCR_CLK_OFF);
|
||||
}
|
||||
|
||||
static int clk_branch_wait(const struct clk_branch *br, bool enabling,
|
||||
|
|
|
|||
|
|
@ -141,6 +141,7 @@ extern const struct clk_ops clk_dyn_rcg_ops;
|
|||
* @clkr: regmap clock handle
|
||||
* @cfg_off: defines the cfg register offset from the CMD_RCGR + CFG_REG
|
||||
* @parked_cfg: cached value of the CFG register for parked RCGs
|
||||
* @hw_clk_ctrl: whether to enable hardware clock control
|
||||
*/
|
||||
struct clk_rcg2 {
|
||||
u32 cmd_rcgr;
|
||||
|
|
@ -152,6 +153,7 @@ struct clk_rcg2 {
|
|||
struct clk_regmap clkr;
|
||||
u8 cfg_off;
|
||||
u32 parked_cfg;
|
||||
bool hw_clk_ctrl;
|
||||
};
|
||||
|
||||
#define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr)
|
||||
|
|
|
|||
|
|
@ -325,6 +325,8 @@ static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f,
|
|||
cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
|
||||
if (rcg->mnd_width && f->n && (f->m != f->n))
|
||||
cfg |= CFG_MODE_DUAL_EDGE;
|
||||
if (rcg->hw_clk_ctrl)
|
||||
cfg |= CFG_HW_CLK_CTRL_MASK;
|
||||
|
||||
*_cfg &= ~mask;
|
||||
*_cfg |= cfg;
|
||||
|
|
|
|||
|
|
@ -700,6 +700,24 @@ static const struct clk_rpmh_desc clk_rpmh_qdu1000 = {
|
|||
.num_clks = ARRAY_SIZE(qdu1000_rpmh_clocks),
|
||||
};
|
||||
|
||||
static struct clk_hw *sdx75_rpmh_clocks[] = {
|
||||
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw,
|
||||
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw,
|
||||
[RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw,
|
||||
[RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw,
|
||||
[RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw,
|
||||
[RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw,
|
||||
[RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw,
|
||||
[RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw,
|
||||
[RPMH_QPIC_CLK] = &clk_rpmh_qpic_clk.hw,
|
||||
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
|
||||
};
|
||||
|
||||
static const struct clk_rpmh_desc clk_rpmh_sdx75 = {
|
||||
.clks = sdx75_rpmh_clocks,
|
||||
.num_clks = ARRAY_SIZE(sdx75_rpmh_clocks),
|
||||
};
|
||||
|
||||
static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
|
||||
void *data)
|
||||
{
|
||||
|
|
@ -792,6 +810,7 @@ static const struct of_device_id clk_rpmh_match_table[] = {
|
|||
{ .compatible = "qcom,sdm670-rpmh-clk", .data = &clk_rpmh_sdm670},
|
||||
{ .compatible = "qcom,sdx55-rpmh-clk", .data = &clk_rpmh_sdx55},
|
||||
{ .compatible = "qcom,sdx65-rpmh-clk", .data = &clk_rpmh_sdx65},
|
||||
{ .compatible = "qcom,sdx75-rpmh-clk", .data = &clk_rpmh_sdx75},
|
||||
{ .compatible = "qcom,sm6350-rpmh-clk", .data = &clk_rpmh_sm6350},
|
||||
{ .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150},
|
||||
{ .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250},
|
||||
|
|
|
|||
|
|
@ -67,7 +67,7 @@
|
|||
type, r_id, key)
|
||||
|
||||
#define __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(_prefix, _name, _active,\
|
||||
type, r_id, r, key) \
|
||||
type, r_id, r, key, ao_flags) \
|
||||
static struct clk_smd_rpm clk_smd_rpm_##_prefix##_active; \
|
||||
static struct clk_smd_rpm clk_smd_rpm_##_prefix##_name = { \
|
||||
.rpm_res_type = (type), \
|
||||
|
|
@ -102,12 +102,13 @@
|
|||
.name = "xo_board", \
|
||||
}, \
|
||||
.num_parents = 1, \
|
||||
.flags = (ao_flags), \
|
||||
}, \
|
||||
}
|
||||
|
||||
#define __DEFINE_CLK_SMD_RPM_BRANCH(_name, _active, type, r_id, r, key) \
|
||||
__DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(/* empty */, \
|
||||
_name, _active, type, r_id, r, key)
|
||||
_name, _active, type, r_id, r, key, 0)
|
||||
|
||||
#define DEFINE_CLK_SMD_RPM(_name, type, r_id) \
|
||||
__DEFINE_CLK_SMD_RPM(_name##_clk, _name##_a_clk, \
|
||||
|
|
@ -126,12 +127,12 @@
|
|||
#define DEFINE_CLK_SMD_RPM_BRANCH(_name, type, r_id, r) \
|
||||
__DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(branch_, \
|
||||
_name##_clk, _name##_a_clk, \
|
||||
type, r_id, r, QCOM_RPM_SMD_KEY_ENABLE)
|
||||
type, r_id, r, QCOM_RPM_SMD_KEY_ENABLE, 0)
|
||||
|
||||
#define DEFINE_CLK_SMD_RPM_BRANCH_A(_name, type, r_id, r) \
|
||||
#define DEFINE_CLK_SMD_RPM_BRANCH_A(_name, type, r_id, r, ao_flags) \
|
||||
__DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(branch_, \
|
||||
_name, _name##_a, type, \
|
||||
r_id, r, QCOM_RPM_SMD_KEY_ENABLE)
|
||||
r_id, r, QCOM_RPM_SMD_KEY_ENABLE, ao_flags)
|
||||
|
||||
#define DEFINE_CLK_SMD_RPM_QDSS(_name, type, r_id) \
|
||||
__DEFINE_CLK_SMD_RPM(_name##_clk, _name##_a_clk, \
|
||||
|
|
@ -146,7 +147,7 @@
|
|||
__DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(_prefix, \
|
||||
_name, _name##_a, \
|
||||
QCOM_SMD_RPM_CLK_BUF_A, r_id, r, \
|
||||
QCOM_RPM_KEY_SOFTWARE_ENABLE)
|
||||
QCOM_RPM_KEY_SOFTWARE_ENABLE, 0)
|
||||
|
||||
#define DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(_name, r_id, r) \
|
||||
DEFINE_CLK_SMD_RPM_XO_BUFFER(_name, r_id, r); \
|
||||
|
|
@ -156,6 +157,8 @@
|
|||
|
||||
#define to_clk_smd_rpm(_hw) container_of(_hw, struct clk_smd_rpm, hw)
|
||||
|
||||
static struct qcom_smd_rpm *rpmcc_smd_rpm;
|
||||
|
||||
struct clk_smd_rpm {
|
||||
const int rpm_res_type;
|
||||
const int rpm_key;
|
||||
|
|
@ -166,7 +169,6 @@ struct clk_smd_rpm {
|
|||
struct clk_smd_rpm *peer;
|
||||
struct clk_hw hw;
|
||||
unsigned long rate;
|
||||
struct qcom_smd_rpm *rpm;
|
||||
};
|
||||
|
||||
struct clk_smd_rpm_req {
|
||||
|
|
@ -178,6 +180,7 @@ struct clk_smd_rpm_req {
|
|||
struct rpm_smd_clk_desc {
|
||||
struct clk_smd_rpm **clks;
|
||||
size_t num_clks;
|
||||
bool scaling_before_handover;
|
||||
};
|
||||
|
||||
static DEFINE_MUTEX(rpm_smd_clk_lock);
|
||||
|
|
@ -191,12 +194,12 @@ static int clk_smd_rpm_handoff(struct clk_smd_rpm *r)
|
|||
.value = cpu_to_le32(r->branch ? 1 : INT_MAX),
|
||||
};
|
||||
|
||||
ret = qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_ACTIVE_STATE,
|
||||
ret = qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_ACTIVE_STATE,
|
||||
r->rpm_res_type, r->rpm_clk_id, &req,
|
||||
sizeof(req));
|
||||
if (ret)
|
||||
return ret;
|
||||
ret = qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_SLEEP_STATE,
|
||||
ret = qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_SLEEP_STATE,
|
||||
r->rpm_res_type, r->rpm_clk_id, &req,
|
||||
sizeof(req));
|
||||
if (ret)
|
||||
|
|
@ -214,7 +217,7 @@ static int clk_smd_rpm_set_rate_active(struct clk_smd_rpm *r,
|
|||
.value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */
|
||||
};
|
||||
|
||||
return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_ACTIVE_STATE,
|
||||
return qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_ACTIVE_STATE,
|
||||
r->rpm_res_type, r->rpm_clk_id, &req,
|
||||
sizeof(req));
|
||||
}
|
||||
|
|
@ -228,7 +231,7 @@ static int clk_smd_rpm_set_rate_sleep(struct clk_smd_rpm *r,
|
|||
.value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */
|
||||
};
|
||||
|
||||
return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_SLEEP_STATE,
|
||||
return qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_SLEEP_STATE,
|
||||
r->rpm_res_type, r->rpm_clk_id, &req,
|
||||
sizeof(req));
|
||||
}
|
||||
|
|
@ -395,7 +398,7 @@ static unsigned long clk_smd_rpm_recalc_rate(struct clk_hw *hw,
|
|||
return r->rate;
|
||||
}
|
||||
|
||||
static int clk_smd_rpm_enable_scaling(struct qcom_smd_rpm *rpm)
|
||||
static int clk_smd_rpm_enable_scaling(void)
|
||||
{
|
||||
int ret;
|
||||
struct clk_smd_rpm_req req = {
|
||||
|
|
@ -404,7 +407,7 @@ static int clk_smd_rpm_enable_scaling(struct qcom_smd_rpm *rpm)
|
|||
.value = cpu_to_le32(1),
|
||||
};
|
||||
|
||||
ret = qcom_rpm_smd_write(rpm, QCOM_SMD_RPM_SLEEP_STATE,
|
||||
ret = qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_SLEEP_STATE,
|
||||
QCOM_SMD_RPM_MISC_CLK,
|
||||
QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req));
|
||||
if (ret) {
|
||||
|
|
@ -412,7 +415,7 @@ static int clk_smd_rpm_enable_scaling(struct qcom_smd_rpm *rpm)
|
|||
return ret;
|
||||
}
|
||||
|
||||
ret = qcom_rpm_smd_write(rpm, QCOM_SMD_RPM_ACTIVE_STATE,
|
||||
ret = qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_ACTIVE_STATE,
|
||||
QCOM_SMD_RPM_MISC_CLK,
|
||||
QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req));
|
||||
if (ret) {
|
||||
|
|
@ -438,10 +441,11 @@ static const struct clk_ops clk_smd_rpm_branch_ops = {
|
|||
.recalc_rate = clk_smd_rpm_recalc_rate,
|
||||
};
|
||||
|
||||
DEFINE_CLK_SMD_RPM_BRANCH_A(bi_tcxo, QCOM_SMD_RPM_MISC_CLK, 0, 19200000);
|
||||
/* Disabling BI_TCXO_AO could gate the root clock source of the entire system. */
|
||||
DEFINE_CLK_SMD_RPM_BRANCH_A(bi_tcxo, QCOM_SMD_RPM_MISC_CLK, 0, 19200000, CLK_IS_CRITICAL);
|
||||
DEFINE_CLK_SMD_RPM_BRANCH(qdss, QCOM_SMD_RPM_MISC_CLK, 1, 19200000);
|
||||
DEFINE_CLK_SMD_RPM_QDSS(qdss, QCOM_SMD_RPM_MISC_CLK, 1);
|
||||
DEFINE_CLK_SMD_RPM_BRANCH_A(bimc_freq_log, QCOM_SMD_RPM_MISC_CLK, 4, 1);
|
||||
DEFINE_CLK_SMD_RPM_BRANCH_A(bimc_freq_log, QCOM_SMD_RPM_MISC_CLK, 4, 1, 0);
|
||||
|
||||
DEFINE_CLK_SMD_RPM_BRANCH(mss_cfg_ahb, QCOM_SMD_RPM_MCFG_CLK, 0, 19200000);
|
||||
|
||||
|
|
@ -693,6 +697,7 @@ static struct clk_smd_rpm *msm8974_clks[] = {
|
|||
static const struct rpm_smd_clk_desc rpm_clk_msm8974 = {
|
||||
.clks = msm8974_clks,
|
||||
.num_clks = ARRAY_SIZE(msm8974_clks),
|
||||
.scaling_before_handover = true,
|
||||
};
|
||||
|
||||
static struct clk_smd_rpm *msm8976_clks[] = {
|
||||
|
|
@ -1301,12 +1306,11 @@ static int rpm_smd_clk_probe(struct platform_device *pdev)
|
|||
{
|
||||
int ret;
|
||||
size_t num_clks, i;
|
||||
struct qcom_smd_rpm *rpm;
|
||||
struct clk_smd_rpm **rpm_smd_clks;
|
||||
const struct rpm_smd_clk_desc *desc;
|
||||
|
||||
rpm = dev_get_drvdata(pdev->dev.parent);
|
||||
if (!rpm) {
|
||||
rpmcc_smd_rpm = dev_get_drvdata(pdev->dev.parent);
|
||||
if (!rpmcc_smd_rpm) {
|
||||
dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
|
@ -1318,20 +1322,26 @@ static int rpm_smd_clk_probe(struct platform_device *pdev)
|
|||
rpm_smd_clks = desc->clks;
|
||||
num_clks = desc->num_clks;
|
||||
|
||||
if (desc->scaling_before_handover) {
|
||||
ret = clk_smd_rpm_enable_scaling();
|
||||
if (ret)
|
||||
goto err;
|
||||
}
|
||||
|
||||
for (i = 0; i < num_clks; i++) {
|
||||
if (!rpm_smd_clks[i])
|
||||
continue;
|
||||
|
||||
rpm_smd_clks[i]->rpm = rpm;
|
||||
|
||||
ret = clk_smd_rpm_handoff(rpm_smd_clks[i]);
|
||||
if (ret)
|
||||
goto err;
|
||||
}
|
||||
|
||||
ret = clk_smd_rpm_enable_scaling(rpm);
|
||||
if (ret)
|
||||
goto err;
|
||||
if (!desc->scaling_before_handover) {
|
||||
ret = clk_smd_rpm_enable_scaling();
|
||||
if (ret)
|
||||
goto err;
|
||||
}
|
||||
|
||||
for (i = 0; i < num_clks; i++) {
|
||||
if (!rpm_smd_clks[i])
|
||||
|
|
|
|||
|
|
@ -24,9 +24,11 @@
|
|||
|
||||
enum {
|
||||
P_BI_TCXO,
|
||||
P_BI_TCXO_AO,
|
||||
P_DISP_CC_PLL0_OUT_MAIN,
|
||||
P_DSI0_PHY_PLL_OUT_BYTECLK,
|
||||
P_DSI0_PHY_PLL_OUT_DSICLK,
|
||||
P_GPLL0_OUT_DIV,
|
||||
P_GPLL0_OUT_MAIN,
|
||||
P_SLEEP_CLK,
|
||||
};
|
||||
|
|
@ -82,8 +84,8 @@ static const struct clk_parent_data disp_cc_parent_data_1[] = {
|
|||
};
|
||||
|
||||
static const struct parent_map disp_cc_parent_map_2[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_GPLL0_OUT_MAIN, 4 },
|
||||
{ P_BI_TCXO_AO, 0 },
|
||||
{ P_GPLL0_OUT_DIV, 4 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data disp_cc_parent_data_2[] = {
|
||||
|
|
@ -151,9 +153,9 @@ static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
|
|||
};
|
||||
|
||||
static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
|
||||
F(19200000, P_BI_TCXO, 1, 0, 0),
|
||||
F(37500000, P_GPLL0_OUT_MAIN, 8, 0, 0),
|
||||
F(75000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
|
||||
F(19200000, P_BI_TCXO_AO, 1, 0, 0),
|
||||
F(37500000, P_GPLL0_OUT_DIV, 8, 0, 0),
|
||||
F(75000000, P_GPLL0_OUT_DIV, 4, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -20,8 +20,8 @@
|
|||
#include "reset.h"
|
||||
|
||||
enum {
|
||||
DT_SLEEP_CLK,
|
||||
DT_XO,
|
||||
DT_SLEEP_CLK,
|
||||
DT_PCIE_2LANE_PHY_PIPE_CLK,
|
||||
DT_PCIE_2LANE_PHY_PIPE_CLK_X1,
|
||||
DT_USB_PCIE_WRAPPER_PIPE_CLK,
|
||||
|
|
@ -366,7 +366,7 @@ static struct clk_rcg2 gcc_adss_pwm_clk_src = {
|
|||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gcc_apss_axi_clk_src[] = {
|
||||
F(480000000, P_GPLL4_OUT_MAIN, 2.5, 0, 0),
|
||||
F(480000000, P_GPLL4_OUT_AUX, 2.5, 0, 0),
|
||||
F(533333333, P_GPLL0_OUT_MAIN, 1.5, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
|
@ -963,7 +963,7 @@ static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
|
|||
.name = "gcc_sdcc1_apps_clk_src",
|
||||
.parent_data = gcc_parent_data_9,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_9),
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_floor_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -26,8 +26,6 @@
|
|||
#include "clk-regmap-mux.h"
|
||||
#include "reset.h"
|
||||
|
||||
#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
|
||||
|
||||
enum {
|
||||
P_XO,
|
||||
P_BIAS_PLL,
|
||||
|
|
@ -1654,7 +1652,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
|
|||
.name = "sdcc1_apps_clk_src",
|
||||
.parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
|
||||
.num_parents = 4,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_floor_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -4151,15 +4149,18 @@ static struct clk_branch gcc_dcc_clk = {
|
|||
|
||||
static const struct alpha_pll_config ubi32_pll_config = {
|
||||
.l = 0x3e,
|
||||
.alpha = 0x57,
|
||||
.config_ctl_val = 0x240d6aa8,
|
||||
.config_ctl_hi_val = 0x3c2,
|
||||
.alpha = 0x6667,
|
||||
.config_ctl_val = 0x240d4828,
|
||||
.config_ctl_hi_val = 0x6,
|
||||
.main_output_mask = BIT(0),
|
||||
.aux_output_mask = BIT(1),
|
||||
.pre_div_val = 0x0,
|
||||
.pre_div_mask = BIT(12),
|
||||
.post_div_val = 0x0,
|
||||
.post_div_mask = GENMASK(9, 8),
|
||||
.alpha_en_mask = BIT(24),
|
||||
.test_ctl_val = 0x1C0000C0,
|
||||
.test_ctl_hi_val = 0x4000,
|
||||
};
|
||||
|
||||
static const struct alpha_pll_config nss_crypto_pll_config = {
|
||||
|
|
@ -4517,24 +4518,24 @@ static const struct qcom_reset_map gcc_ipq6018_resets[] = {
|
|||
[GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
|
||||
[GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
|
||||
[GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 },
|
||||
[GCC_PPE_FULL_RESET] = { 0x68014, 0 },
|
||||
[GCC_UNIPHY0_SOFT_RESET] = { 0x56004, 0 },
|
||||
[GCC_PPE_FULL_RESET] = { .reg = 0x68014, .bitmask = 0xf0000 },
|
||||
[GCC_UNIPHY0_SOFT_RESET] = { .reg = 0x56004, .bitmask = 0x3ff2 },
|
||||
[GCC_UNIPHY0_XPCS_RESET] = { 0x56004, 2 },
|
||||
[GCC_UNIPHY1_SOFT_RESET] = { 0x56104, 0 },
|
||||
[GCC_UNIPHY1_SOFT_RESET] = { .reg = 0x56104, .bitmask = 0x32 },
|
||||
[GCC_UNIPHY1_XPCS_RESET] = { 0x56104, 2 },
|
||||
[GCC_EDMA_HW_RESET] = { 0x68014, 0 },
|
||||
[GCC_NSSPORT1_RESET] = { 0x68014, 0 },
|
||||
[GCC_NSSPORT2_RESET] = { 0x68014, 0 },
|
||||
[GCC_NSSPORT3_RESET] = { 0x68014, 0 },
|
||||
[GCC_NSSPORT4_RESET] = { 0x68014, 0 },
|
||||
[GCC_NSSPORT5_RESET] = { 0x68014, 0 },
|
||||
[GCC_UNIPHY0_PORT1_ARES] = { 0x56004, 0 },
|
||||
[GCC_UNIPHY0_PORT2_ARES] = { 0x56004, 0 },
|
||||
[GCC_UNIPHY0_PORT3_ARES] = { 0x56004, 0 },
|
||||
[GCC_UNIPHY0_PORT4_ARES] = { 0x56004, 0 },
|
||||
[GCC_UNIPHY0_PORT5_ARES] = { 0x56004, 0 },
|
||||
[GCC_UNIPHY0_PORT_4_5_RESET] = { 0x56004, 0 },
|
||||
[GCC_UNIPHY0_PORT_4_RESET] = { 0x56004, 0 },
|
||||
[GCC_EDMA_HW_RESET] = { .reg = 0x68014, .bitmask = 0x300000 },
|
||||
[GCC_NSSPORT1_RESET] = { .reg = 0x68014, .bitmask = 0x1000003 },
|
||||
[GCC_NSSPORT2_RESET] = { .reg = 0x68014, .bitmask = 0x200000c },
|
||||
[GCC_NSSPORT3_RESET] = { .reg = 0x68014, .bitmask = 0x4000030 },
|
||||
[GCC_NSSPORT4_RESET] = { .reg = 0x68014, .bitmask = 0x8000300 },
|
||||
[GCC_NSSPORT5_RESET] = { .reg = 0x68014, .bitmask = 0x10000c00 },
|
||||
[GCC_UNIPHY0_PORT1_ARES] = { .reg = 0x56004, .bitmask = 0x30 },
|
||||
[GCC_UNIPHY0_PORT2_ARES] = { .reg = 0x56004, .bitmask = 0xc0 },
|
||||
[GCC_UNIPHY0_PORT3_ARES] = { .reg = 0x56004, .bitmask = 0x300 },
|
||||
[GCC_UNIPHY0_PORT4_ARES] = { .reg = 0x56004, .bitmask = 0xc00 },
|
||||
[GCC_UNIPHY0_PORT5_ARES] = { .reg = 0x56004, .bitmask = 0x3000 },
|
||||
[GCC_UNIPHY0_PORT_4_5_RESET] = { .reg = 0x56004, .bitmask = 0x3c02 },
|
||||
[GCC_UNIPHY0_PORT_4_RESET] = { .reg = 0x56004, .bitmask = 0xc02 },
|
||||
[GCC_LPASS_BCR] = {0x1F000, 0},
|
||||
[GCC_UBI32_TBU_BCR] = {0x65000, 0},
|
||||
[GCC_LPASS_TBU_BCR] = {0x6C000, 0},
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -650,7 +650,7 @@ static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
|
|||
.name = "gcc_usb30_prim_mock_utmi_clk_src",
|
||||
.parent_data = gcc_parents_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_0),
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -686,7 +686,7 @@ static struct clk_rcg2 gcc_camss_axi_clk_src = {
|
|||
.name = "gcc_camss_axi_clk_src",
|
||||
.parent_data = gcc_parents_4,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_4),
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -706,7 +706,7 @@ static struct clk_rcg2 gcc_camss_cci_clk_src = {
|
|||
.name = "gcc_camss_cci_clk_src",
|
||||
.parent_data = gcc_parents_9,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_9),
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -728,7 +728,7 @@ static struct clk_rcg2 gcc_camss_csi0phytimer_clk_src = {
|
|||
.name = "gcc_camss_csi0phytimer_clk_src",
|
||||
.parent_data = gcc_parents_5,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_5),
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -742,7 +742,7 @@ static struct clk_rcg2 gcc_camss_csi1phytimer_clk_src = {
|
|||
.name = "gcc_camss_csi1phytimer_clk_src",
|
||||
.parent_data = gcc_parents_5,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_5),
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -764,7 +764,7 @@ static struct clk_rcg2 gcc_camss_mclk0_clk_src = {
|
|||
.parent_data = gcc_parents_3,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_3),
|
||||
.flags = CLK_OPS_PARENT_ENABLE,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -779,7 +779,7 @@ static struct clk_rcg2 gcc_camss_mclk1_clk_src = {
|
|||
.parent_data = gcc_parents_3,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_3),
|
||||
.flags = CLK_OPS_PARENT_ENABLE,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -794,7 +794,7 @@ static struct clk_rcg2 gcc_camss_mclk2_clk_src = {
|
|||
.parent_data = gcc_parents_3,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_3),
|
||||
.flags = CLK_OPS_PARENT_ENABLE,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -809,7 +809,7 @@ static struct clk_rcg2 gcc_camss_mclk3_clk_src = {
|
|||
.parent_data = gcc_parents_3,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_3),
|
||||
.flags = CLK_OPS_PARENT_ENABLE,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -830,7 +830,7 @@ static struct clk_rcg2 gcc_camss_ope_ahb_clk_src = {
|
|||
.name = "gcc_camss_ope_ahb_clk_src",
|
||||
.parent_data = gcc_parents_6,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_6),
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -854,7 +854,7 @@ static struct clk_rcg2 gcc_camss_ope_clk_src = {
|
|||
.parent_data = gcc_parents_6,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_6),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -888,7 +888,7 @@ static struct clk_rcg2 gcc_camss_tfe_0_clk_src = {
|
|||
.name = "gcc_camss_tfe_0_clk_src",
|
||||
.parent_data = gcc_parents_7,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_7),
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -912,7 +912,7 @@ static struct clk_rcg2 gcc_camss_tfe_0_csid_clk_src = {
|
|||
.name = "gcc_camss_tfe_0_csid_clk_src",
|
||||
.parent_data = gcc_parents_8,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_8),
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -926,7 +926,7 @@ static struct clk_rcg2 gcc_camss_tfe_1_clk_src = {
|
|||
.name = "gcc_camss_tfe_1_clk_src",
|
||||
.parent_data = gcc_parents_7,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_7),
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -940,7 +940,7 @@ static struct clk_rcg2 gcc_camss_tfe_1_csid_clk_src = {
|
|||
.name = "gcc_camss_tfe_1_csid_clk_src",
|
||||
.parent_data = gcc_parents_8,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_8),
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -963,7 +963,7 @@ static struct clk_rcg2 gcc_camss_tfe_cphy_rx_clk_src = {
|
|||
.parent_data = gcc_parents_10,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_10),
|
||||
.flags = CLK_OPS_PARENT_ENABLE,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -984,7 +984,7 @@ static struct clk_rcg2 gcc_camss_top_ahb_clk_src = {
|
|||
.name = "gcc_camss_top_ahb_clk_src",
|
||||
.parent_data = gcc_parents_4,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_4),
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -1006,7 +1006,7 @@ static struct clk_rcg2 gcc_gp1_clk_src = {
|
|||
.name = "gcc_gp1_clk_src",
|
||||
.parent_data = gcc_parents_2,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_2),
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -1020,7 +1020,7 @@ static struct clk_rcg2 gcc_gp2_clk_src = {
|
|||
.name = "gcc_gp2_clk_src",
|
||||
.parent_data = gcc_parents_2,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_2),
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -1034,7 +1034,7 @@ static struct clk_rcg2 gcc_gp3_clk_src = {
|
|||
.name = "gcc_gp3_clk_src",
|
||||
.parent_data = gcc_parents_2,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_2),
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -1054,7 +1054,7 @@ static struct clk_rcg2 gcc_pdm2_clk_src = {
|
|||
.name = "gcc_pdm2_clk_src",
|
||||
.parent_data = gcc_parents_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_0),
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -1082,7 +1082,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
|
|||
.name = "gcc_qupv3_wrap0_s0_clk_src",
|
||||
.parent_data = gcc_parents_1,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_1),
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
|
||||
|
|
@ -1098,7 +1098,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
|
|||
.name = "gcc_qupv3_wrap0_s1_clk_src",
|
||||
.parent_data = gcc_parents_1,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_1),
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
|
||||
|
|
@ -1114,7 +1114,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
|
|||
.name = "gcc_qupv3_wrap0_s2_clk_src",
|
||||
.parent_data = gcc_parents_1,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_1),
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
|
||||
|
|
@ -1130,7 +1130,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
|
|||
.name = "gcc_qupv3_wrap0_s3_clk_src",
|
||||
.parent_data = gcc_parents_1,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_1),
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
|
||||
|
|
@ -1146,7 +1146,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
|
|||
.name = "gcc_qupv3_wrap0_s4_clk_src",
|
||||
.parent_data = gcc_parents_1,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_1),
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
|
||||
|
|
@ -1162,7 +1162,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
|
|||
.name = "gcc_qupv3_wrap0_s5_clk_src",
|
||||
.parent_data = gcc_parents_1,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_1),
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
|
||||
|
|
@ -1219,7 +1219,7 @@ static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
|
|||
.name = "gcc_sdcc1_ice_core_clk_src",
|
||||
.parent_data = gcc_parents_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_0),
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -1266,7 +1266,7 @@ static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
|
|||
.name = "gcc_usb30_prim_master_clk_src",
|
||||
.parent_data = gcc_parents_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_0),
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -1280,7 +1280,7 @@ static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
|
|||
.name = "gcc_usb3_prim_phy_aux_clk_src",
|
||||
.parent_data = gcc_parents_13,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_13),
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -1303,7 +1303,7 @@ static struct clk_rcg2 gcc_video_venus_clk_src = {
|
|||
.parent_data = gcc_parents_14,
|
||||
.num_parents = ARRAY_SIZE(gcc_parents_14),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@
|
|||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
|
|
@ -7421,9 +7422,19 @@ static int gcc_sc8280xp_probe(struct platform_device *pdev)
|
|||
struct regmap *regmap;
|
||||
int ret;
|
||||
|
||||
ret = devm_pm_runtime_enable(&pdev->dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = pm_runtime_resume_and_get(&pdev->dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
regmap = qcom_cc_map(pdev, &gcc_sc8280xp_desc);
|
||||
if (IS_ERR(regmap))
|
||||
if (IS_ERR(regmap)) {
|
||||
pm_runtime_put(&pdev->dev);
|
||||
return PTR_ERR(regmap);
|
||||
}
|
||||
|
||||
/*
|
||||
* Keep the clocks always-ON
|
||||
|
|
@ -7445,7 +7456,10 @@ static int gcc_sc8280xp_probe(struct platform_device *pdev)
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
return qcom_cc_really_probe(pdev, &gcc_sc8280xp_desc, regmap);
|
||||
ret = qcom_cc_really_probe(pdev, &gcc_sc8280xp_desc, regmap);
|
||||
pm_runtime_put(&pdev->dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct of_device_id gcc_sc8280xp_match_table[] = {
|
||||
|
|
|
|||
|
|
@ -25,8 +25,6 @@
|
|||
#include "reset.h"
|
||||
#include "gdsc.h"
|
||||
|
||||
#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
|
||||
|
||||
enum {
|
||||
P_XO,
|
||||
P_SLEEP_CLK,
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -119,6 +119,8 @@ static const struct alpha_pll_config gpll10_config = {
|
|||
.vco_mask = GENMASK(21, 20),
|
||||
.main_output_mask = BIT(0),
|
||||
.config_ctl_val = 0x4001055b,
|
||||
.test_ctl_hi1_val = 0x1,
|
||||
.test_ctl_hi_mask = 0x1,
|
||||
};
|
||||
|
||||
static struct clk_alpha_pll gpll10 = {
|
||||
|
|
@ -170,6 +172,8 @@ static const struct alpha_pll_config gpll11_config = {
|
|||
.vco_val = 0x2 << 20,
|
||||
.vco_mask = GENMASK(21, 20),
|
||||
.config_ctl_val = 0x4001055b,
|
||||
.test_ctl_hi1_val = 0x1,
|
||||
.test_ctl_hi_mask = 0x1,
|
||||
};
|
||||
|
||||
static struct clk_alpha_pll gpll11 = {
|
||||
|
|
@ -362,6 +366,8 @@ static const struct alpha_pll_config gpll8_config = {
|
|||
.post_div_val = 0x1 << 8,
|
||||
.post_div_mask = GENMASK(11, 8),
|
||||
.config_ctl_val = 0x4001055b,
|
||||
.test_ctl_hi1_val = 0x1,
|
||||
.test_ctl_hi_mask = 0x1,
|
||||
};
|
||||
|
||||
static struct clk_alpha_pll gpll8 = {
|
||||
|
|
@ -413,6 +419,8 @@ static const struct alpha_pll_config gpll9_config = {
|
|||
.post_div_mask = GENMASK(9, 8),
|
||||
.main_output_mask = BIT(0),
|
||||
.config_ctl_val = 0x00004289,
|
||||
.test_ctl_mask = GENMASK(31, 0),
|
||||
.test_ctl_val = 0x08000000,
|
||||
};
|
||||
|
||||
static struct clk_alpha_pll gpll9 = {
|
||||
|
|
|
|||
|
|
@ -334,6 +334,7 @@ static struct clk_rcg2 gcc_gp1_clk_src = {
|
|||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_1,
|
||||
.freq_tbl = ftbl_gcc_gp1_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_gp1_clk_src",
|
||||
.parent_data = gcc_parent_data_1,
|
||||
|
|
@ -349,6 +350,7 @@ static struct clk_rcg2 gcc_gp2_clk_src = {
|
|||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_1,
|
||||
.freq_tbl = ftbl_gcc_gp1_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_gp2_clk_src",
|
||||
.parent_data = gcc_parent_data_1,
|
||||
|
|
@ -364,6 +366,7 @@ static struct clk_rcg2 gcc_gp3_clk_src = {
|
|||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_1,
|
||||
.freq_tbl = ftbl_gcc_gp1_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_gp3_clk_src",
|
||||
.parent_data = gcc_parent_data_1,
|
||||
|
|
@ -384,6 +387,7 @@ static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
|
|||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_2,
|
||||
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_pcie_0_aux_clk_src",
|
||||
.parent_data = gcc_parent_data_2,
|
||||
|
|
@ -405,6 +409,7 @@ static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
|
|||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_pcie_0_phy_rchng_clk_src",
|
||||
.parent_data = gcc_parent_data_0,
|
||||
|
|
@ -420,6 +425,7 @@ static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
|
|||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_2,
|
||||
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_pcie_1_aux_clk_src",
|
||||
.parent_data = gcc_parent_data_2,
|
||||
|
|
@ -435,6 +441,7 @@ static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
|
|||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_pcie_1_phy_rchng_clk_src",
|
||||
.parent_data = gcc_parent_data_0,
|
||||
|
|
@ -455,6 +462,7 @@ static struct clk_rcg2 gcc_pdm2_clk_src = {
|
|||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_pdm2_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_pdm2_clk_src",
|
||||
.parent_data = gcc_parent_data_0,
|
||||
|
|
@ -493,6 +501,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
|
|||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
|
||||
};
|
||||
|
||||
|
|
@ -510,6 +519,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
|
|||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
|
||||
};
|
||||
|
||||
|
|
@ -527,6 +537,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
|
|||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
|
||||
};
|
||||
|
||||
|
|
@ -544,6 +555,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
|
|||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
|
||||
};
|
||||
|
||||
|
|
@ -561,6 +573,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
|
|||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
|
||||
};
|
||||
|
||||
|
|
@ -590,6 +603,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
|
|||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_qupv3_wrap0_s5_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
|
||||
};
|
||||
|
||||
|
|
@ -607,6 +621,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
|
|||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
|
||||
};
|
||||
|
||||
|
|
@ -624,6 +639,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
|
|||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
|
||||
};
|
||||
|
||||
|
|
@ -660,6 +676,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
|
|||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
|
||||
};
|
||||
|
||||
|
|
@ -677,6 +694,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
|
|||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
|
||||
};
|
||||
|
||||
|
|
@ -694,6 +712,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
|
|||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
|
||||
};
|
||||
|
||||
|
|
@ -711,6 +730,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
|
|||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
|
||||
};
|
||||
|
||||
|
|
@ -728,6 +748,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
|
|||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
|
||||
};
|
||||
|
||||
|
|
@ -745,6 +766,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
|
|||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
|
||||
};
|
||||
|
||||
|
|
@ -762,6 +784,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
|
|||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
|
||||
};
|
||||
|
||||
|
|
@ -779,6 +802,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
|
|||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,
|
||||
};
|
||||
|
||||
|
|
@ -796,6 +820,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
|
|||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,
|
||||
};
|
||||
|
||||
|
|
@ -813,6 +838,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
|
|||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,
|
||||
};
|
||||
|
||||
|
|
@ -830,6 +856,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
|
|||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,
|
||||
};
|
||||
|
||||
|
|
@ -847,6 +874,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
|
|||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,
|
||||
};
|
||||
|
||||
|
|
@ -864,6 +892,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
|
|||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,
|
||||
};
|
||||
|
||||
|
|
@ -881,6 +910,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
|
|||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init,
|
||||
};
|
||||
|
||||
|
|
@ -899,6 +929,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
|
|||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_7,
|
||||
.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_sdcc2_apps_clk_src",
|
||||
.parent_data = gcc_parent_data_7,
|
||||
|
|
@ -921,6 +952,7 @@ static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
|
|||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_sdcc4_apps_clk_src",
|
||||
.parent_data = gcc_parent_data_0,
|
||||
|
|
@ -944,6 +976,7 @@ static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
|
|||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_ufs_phy_axi_clk_src",
|
||||
.parent_data = gcc_parent_data_0,
|
||||
|
|
@ -966,6 +999,7 @@ static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
|
|||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_ufs_phy_ice_core_clk_src",
|
||||
.parent_data = gcc_parent_data_0,
|
||||
|
|
@ -987,6 +1021,7 @@ static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
|
|||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_3,
|
||||
.freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_ufs_phy_phy_aux_clk_src",
|
||||
.parent_data = gcc_parent_data_3,
|
||||
|
|
@ -1002,6 +1037,7 @@ static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
|
|||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_ufs_phy_unipro_core_clk_src",
|
||||
.parent_data = gcc_parent_data_0,
|
||||
|
|
@ -1025,6 +1061,7 @@ static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
|
|||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_usb30_prim_master_clk_src",
|
||||
.parent_data = gcc_parent_data_0,
|
||||
|
|
@ -1040,6 +1077,7 @@ static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
|
|||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_0,
|
||||
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_usb30_prim_mock_utmi_clk_src",
|
||||
.parent_data = gcc_parent_data_0,
|
||||
|
|
@ -1055,6 +1093,7 @@ static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
|
|||
.hid_width = 5,
|
||||
.parent_map = gcc_parent_map_2,
|
||||
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_usb3_prim_phy_aux_clk_src",
|
||||
.parent_data = gcc_parent_data_2,
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@
|
|||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
#include <dt-bindings/clock/qcom,gpucc-sc8280xp.h>
|
||||
|
|
@ -424,10 +425,21 @@ static struct qcom_cc_desc gpu_cc_sc8280xp_desc = {
|
|||
static int gpu_cc_sc8280xp_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct regmap *regmap;
|
||||
int ret;
|
||||
|
||||
ret = devm_pm_runtime_enable(&pdev->dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = pm_runtime_resume_and_get(&pdev->dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
regmap = qcom_cc_map(pdev, &gpu_cc_sc8280xp_desc);
|
||||
if (IS_ERR(regmap))
|
||||
if (IS_ERR(regmap)) {
|
||||
pm_runtime_put(&pdev->dev);
|
||||
return PTR_ERR(regmap);
|
||||
}
|
||||
|
||||
clk_lucid_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
|
||||
clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
|
||||
|
|
@ -439,7 +451,10 @@ static int gpu_cc_sc8280xp_probe(struct platform_device *pdev)
|
|||
regmap_update_bits(regmap, 0x1170, BIT(0), BIT(0));
|
||||
regmap_update_bits(regmap, 0x109c, BIT(0), BIT(0));
|
||||
|
||||
return qcom_cc_really_probe(pdev, &gpu_cc_sc8280xp_desc, regmap);
|
||||
ret = qcom_cc_really_probe(pdev, &gpu_cc_sc8280xp_desc, regmap);
|
||||
pm_runtime_put(&pdev->dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct of_device_id gpu_cc_sc8280xp_match_table[] = {
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@
|
|||
#include <linux/clk-provider.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
#include <dt-bindings/clock/qcom,sm6375-gpucc.h>
|
||||
|
|
@ -434,15 +435,29 @@ MODULE_DEVICE_TABLE(of, gpucc_sm6375_match_table);
|
|||
static int gpucc_sm6375_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct regmap *regmap;
|
||||
int ret;
|
||||
|
||||
ret = devm_pm_runtime_enable(&pdev->dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = pm_runtime_resume_and_get(&pdev->dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
regmap = qcom_cc_map(pdev, &gpucc_sm6375_desc);
|
||||
if (IS_ERR(regmap))
|
||||
if (IS_ERR(regmap)) {
|
||||
pm_runtime_put(&pdev->dev);
|
||||
return PTR_ERR(regmap);
|
||||
}
|
||||
|
||||
clk_lucid_pll_configure(&gpucc_pll0, regmap, &gpucc_pll0_config);
|
||||
clk_lucid_pll_configure(&gpucc_pll1, regmap, &gpucc_pll1_config);
|
||||
|
||||
return qcom_cc_really_probe(pdev, &gpucc_sm6375_desc, regmap);
|
||||
ret = qcom_cc_really_probe(pdev, &gpucc_sm6375_desc, regmap);
|
||||
pm_runtime_put(&pdev->dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct platform_driver gpucc_sm6375_driver = {
|
||||
|
|
|
|||
|
|
@ -0,0 +1,766 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
#include <dt-bindings/clock/qcom,sm8450-gpucc.h>
|
||||
#include <dt-bindings/reset/qcom,sm8450-gpucc.h>
|
||||
|
||||
#include "clk-alpha-pll.h"
|
||||
#include "clk-branch.h"
|
||||
#include "clk-rcg.h"
|
||||
#include "clk-regmap.h"
|
||||
#include "clk-regmap-divider.h"
|
||||
#include "clk-regmap-mux.h"
|
||||
#include "clk-regmap-phy-mux.h"
|
||||
#include "gdsc.h"
|
||||
#include "reset.h"
|
||||
|
||||
enum {
|
||||
DT_BI_TCXO,
|
||||
DT_GPLL0_OUT_MAIN,
|
||||
DT_GPLL0_OUT_MAIN_DIV,
|
||||
};
|
||||
|
||||
enum {
|
||||
P_BI_TCXO,
|
||||
P_GPLL0_OUT_MAIN,
|
||||
P_GPLL0_OUT_MAIN_DIV,
|
||||
P_GPU_CC_PLL0_OUT_MAIN,
|
||||
P_GPU_CC_PLL1_OUT_MAIN,
|
||||
};
|
||||
|
||||
static struct pll_vco lucid_evo_vco[] = {
|
||||
{ 249600000, 2000000000, 0 },
|
||||
};
|
||||
|
||||
static struct alpha_pll_config gpu_cc_pll0_config = {
|
||||
.l = 0x1d,
|
||||
.alpha = 0xb000,
|
||||
.config_ctl_val = 0x20485699,
|
||||
.config_ctl_hi_val = 0x00182261,
|
||||
.config_ctl_hi1_val = 0x32aa299c,
|
||||
.user_ctl_val = 0x00000000,
|
||||
.user_ctl_hi_val = 0x00000805,
|
||||
};
|
||||
|
||||
static struct clk_alpha_pll gpu_cc_pll0 = {
|
||||
.offset = 0x0,
|
||||
.vco_table = lucid_evo_vco,
|
||||
.num_vco = ARRAY_SIZE(lucid_evo_vco),
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
|
||||
.clkr = {
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_pll0",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.index = DT_BI_TCXO,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_lucid_evo_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct alpha_pll_config gpu_cc_pll1_config = {
|
||||
.l = 0x34,
|
||||
.alpha = 0x1555,
|
||||
.config_ctl_val = 0x20485699,
|
||||
.config_ctl_hi_val = 0x00182261,
|
||||
.config_ctl_hi1_val = 0x32aa299c,
|
||||
.user_ctl_val = 0x00000000,
|
||||
.user_ctl_hi_val = 0x00000805,
|
||||
};
|
||||
|
||||
static struct clk_alpha_pll gpu_cc_pll1 = {
|
||||
.offset = 0x1000,
|
||||
.vco_table = lucid_evo_vco,
|
||||
.num_vco = ARRAY_SIZE(lucid_evo_vco),
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
|
||||
.clkr = {
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_pll1",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.index = DT_BI_TCXO,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_lucid_evo_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct parent_map gpu_cc_parent_map_0[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_GPLL0_OUT_MAIN, 5 },
|
||||
{ P_GPLL0_OUT_MAIN_DIV, 6 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data gpu_cc_parent_data_0[] = {
|
||||
{ .index = DT_BI_TCXO },
|
||||
{ .index = DT_GPLL0_OUT_MAIN },
|
||||
{ .index = DT_GPLL0_OUT_MAIN_DIV },
|
||||
};
|
||||
|
||||
static const struct parent_map gpu_cc_parent_map_1[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
|
||||
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
|
||||
{ P_GPLL0_OUT_MAIN, 5 },
|
||||
{ P_GPLL0_OUT_MAIN_DIV, 6 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data gpu_cc_parent_data_1[] = {
|
||||
{ .index = DT_BI_TCXO },
|
||||
{ .hw = &gpu_cc_pll0.clkr.hw },
|
||||
{ .hw = &gpu_cc_pll1.clkr.hw },
|
||||
{ .index = DT_GPLL0_OUT_MAIN },
|
||||
{ .index = DT_GPLL0_OUT_MAIN_DIV },
|
||||
};
|
||||
|
||||
static const struct parent_map gpu_cc_parent_map_2[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
|
||||
{ P_GPLL0_OUT_MAIN, 5 },
|
||||
{ P_GPLL0_OUT_MAIN_DIV, 6 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data gpu_cc_parent_data_2[] = {
|
||||
{ .index = DT_BI_TCXO },
|
||||
{ .hw = &gpu_cc_pll1.clkr.hw },
|
||||
{ .index = DT_GPLL0_OUT_MAIN },
|
||||
{ .index = DT_GPLL0_OUT_MAIN_DIV },
|
||||
};
|
||||
|
||||
static const struct parent_map gpu_cc_parent_map_3[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data gpu_cc_parent_data_3[] = {
|
||||
{ .index = DT_BI_TCXO },
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = {
|
||||
F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gpu_cc_ff_clk_src = {
|
||||
.cmd_rcgr = 0x9474,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = gpu_cc_parent_map_0,
|
||||
.freq_tbl = ftbl_gpu_cc_ff_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_ff_clk_src",
|
||||
.parent_data = gpu_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
|
||||
F(19200000, P_BI_TCXO, 1, 0, 0),
|
||||
F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
|
||||
F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gpu_cc_gmu_clk_src = {
|
||||
.cmd_rcgr = 0x9318,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = gpu_cc_parent_map_1,
|
||||
.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_gmu_clk_src",
|
||||
.parent_data = gpu_cc_parent_data_1,
|
||||
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = {
|
||||
F(150000000, P_GPLL0_OUT_MAIN_DIV, 2, 0, 0),
|
||||
F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
|
||||
F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gpu_cc_hub_clk_src = {
|
||||
.cmd_rcgr = 0x93ec,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = gpu_cc_parent_map_2,
|
||||
.freq_tbl = ftbl_gpu_cc_hub_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_hub_clk_src",
|
||||
.parent_data = gpu_cc_parent_data_2,
|
||||
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_2),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gpu_cc_xo_clk_src[] = {
|
||||
F(19200000, P_BI_TCXO, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gpu_cc_xo_clk_src = {
|
||||
.cmd_rcgr = 0x9010,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = gpu_cc_parent_map_3,
|
||||
.freq_tbl = ftbl_gpu_cc_xo_clk_src,
|
||||
.hw_clk_ctrl = true,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_xo_clk_src",
|
||||
.parent_data = gpu_cc_parent_data_3,
|
||||
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_3),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_div gpu_cc_demet_div_clk_src = {
|
||||
.reg = 0x9054,
|
||||
.shift = 0,
|
||||
.width = 4,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.name = "gpu_cc_demet_div_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gpu_cc_xo_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_regmap_div_ro_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_div gpu_cc_hub_ahb_div_clk_src = {
|
||||
.reg = 0x9430,
|
||||
.shift = 0,
|
||||
.width = 4,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.name = "gpu_cc_hub_ahb_div_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gpu_cc_hub_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_regmap_div_ro_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_div gpu_cc_hub_cx_int_div_clk_src = {
|
||||
.reg = 0x942c,
|
||||
.shift = 0,
|
||||
.width = 4,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.name = "gpu_cc_hub_cx_int_div_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gpu_cc_hub_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_regmap_div_ro_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_div gpu_cc_xo_div_clk_src = {
|
||||
.reg = 0x9050,
|
||||
.shift = 0,
|
||||
.width = 4,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.name = "gpu_cc_xo_div_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gpu_cc_xo_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_regmap_div_ro_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_ahb_clk = {
|
||||
.halt_reg = 0x911c,
|
||||
.halt_check = BRANCH_HALT_DELAY,
|
||||
.clkr = {
|
||||
.enable_reg = 0x911c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_ahb_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpu_cc_hub_ahb_div_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_crc_ahb_clk = {
|
||||
.halt_reg = 0x9120,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9120,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_crc_ahb_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpu_cc_hub_ahb_div_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_cx_apb_clk = {
|
||||
.halt_reg = 0x912c,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x912c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_cx_apb_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_cx_ff_clk = {
|
||||
.halt_reg = 0x914c,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x914c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_cx_ff_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpu_cc_ff_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_cx_gmu_clk = {
|
||||
.halt_reg = 0x913c,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x913c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_cx_gmu_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpu_cc_gmu_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_aon_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
|
||||
.halt_reg = 0x9130,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9130,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_cx_snoc_dvm_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_cxo_aon_clk = {
|
||||
.halt_reg = 0x9004,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9004,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_cxo_aon_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpu_cc_xo_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_cxo_clk = {
|
||||
.halt_reg = 0x9144,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9144,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_cxo_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpu_cc_xo_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_demet_clk = {
|
||||
.halt_reg = 0x900c,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x900c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_demet_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpu_cc_demet_div_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_aon_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_freq_measure_clk = {
|
||||
.halt_reg = 0x9008,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9008,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_freq_measure_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpu_cc_xo_div_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_gx_ff_clk = {
|
||||
.halt_reg = 0x90c0,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x90c0,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_gx_ff_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpu_cc_ff_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_gx_gfx3d_clk = {
|
||||
.halt_reg = 0x90a8,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x90a8,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_gx_gfx3d_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_gx_gfx3d_rdvm_clk = {
|
||||
.halt_reg = 0x90c8,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x90c8,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_gx_gfx3d_rdvm_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_gx_gmu_clk = {
|
||||
.halt_reg = 0x90bc,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x90bc,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_gx_gmu_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpu_cc_gmu_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_gx_vsense_clk = {
|
||||
.halt_reg = 0x90b0,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x90b0,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_gx_vsense_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
|
||||
.halt_reg = 0x7000,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x7000,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_hub_aon_clk = {
|
||||
.halt_reg = 0x93e8,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x93e8,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_hub_aon_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpu_cc_hub_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_aon_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_hub_cx_int_clk = {
|
||||
.halt_reg = 0x9148,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9148,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_hub_cx_int_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpu_cc_hub_cx_int_div_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_aon_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_memnoc_gfx_clk = {
|
||||
.halt_reg = 0x9150,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9150,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_memnoc_gfx_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk = {
|
||||
.halt_reg = 0x9288,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9288,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_mnd1x_0_gfx3d_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_mnd1x_1_gfx3d_clk = {
|
||||
.halt_reg = 0x928c,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x928c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_mnd1x_1_gfx3d_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_sleep_clk = {
|
||||
.halt_reg = 0x9134,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9134,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_sleep_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct gdsc gpu_cx_gdsc = {
|
||||
.gdscr = 0x9108,
|
||||
.gds_hw_ctrl = 0x953c,
|
||||
.clk_dis_wait_val = 8,
|
||||
.pd = {
|
||||
.name = "gpu_cx_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = VOTABLE | RETAIN_FF_ENABLE,
|
||||
};
|
||||
|
||||
static struct gdsc gpu_gx_gdsc = {
|
||||
.gdscr = 0x905c,
|
||||
.clamp_io_ctrl = 0x9504,
|
||||
.resets = (unsigned int []){ GPUCC_GPU_CC_GX_BCR,
|
||||
GPUCC_GPU_CC_ACD_BCR,
|
||||
GPUCC_GPU_CC_GX_ACD_IROOT_BCR },
|
||||
.reset_count = 3,
|
||||
.pd = {
|
||||
.name = "gpu_gx_gdsc",
|
||||
.power_on = gdsc_gx_do_nothing_enable,
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = CLAMP_IO | AON_RESET | SW_RESET | POLL_CFG_GDSCR,
|
||||
};
|
||||
|
||||
static struct clk_regmap *gpu_cc_sm8450_clocks[] = {
|
||||
[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
|
||||
[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
|
||||
[GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr,
|
||||
[GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr,
|
||||
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
|
||||
[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
|
||||
[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
|
||||
[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
|
||||
[GPU_CC_DEMET_CLK] = &gpu_cc_demet_clk.clkr,
|
||||
[GPU_CC_DEMET_DIV_CLK_SRC] = &gpu_cc_demet_div_clk_src.clkr,
|
||||
[GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr,
|
||||
[GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr,
|
||||
[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
|
||||
[GPU_CC_GX_FF_CLK] = &gpu_cc_gx_ff_clk.clkr,
|
||||
[GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr,
|
||||
[GPU_CC_GX_GFX3D_RDVM_CLK] = &gpu_cc_gx_gfx3d_rdvm_clk.clkr,
|
||||
[GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
|
||||
[GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr,
|
||||
[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
|
||||
[GPU_CC_HUB_AHB_DIV_CLK_SRC] = &gpu_cc_hub_ahb_div_clk_src.clkr,
|
||||
[GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
|
||||
[GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,
|
||||
[GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr,
|
||||
[GPU_CC_HUB_CX_INT_DIV_CLK_SRC] = &gpu_cc_hub_cx_int_div_clk_src.clkr,
|
||||
[GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr,
|
||||
[GPU_CC_MND1X_0_GFX3D_CLK] = &gpu_cc_mnd1x_0_gfx3d_clk.clkr,
|
||||
[GPU_CC_MND1X_1_GFX3D_CLK] = &gpu_cc_mnd1x_1_gfx3d_clk.clkr,
|
||||
[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
|
||||
[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
|
||||
[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
|
||||
[GPU_CC_XO_CLK_SRC] = &gpu_cc_xo_clk_src.clkr,
|
||||
[GPU_CC_XO_DIV_CLK_SRC] = &gpu_cc_xo_div_clk_src.clkr,
|
||||
};
|
||||
|
||||
static const struct qcom_reset_map gpu_cc_sm8450_resets[] = {
|
||||
[GPUCC_GPU_CC_XO_BCR] = { 0x9000 },
|
||||
[GPUCC_GPU_CC_GX_BCR] = { 0x9058 },
|
||||
[GPUCC_GPU_CC_CX_BCR] = { 0x9104 },
|
||||
[GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x9198 },
|
||||
[GPUCC_GPU_CC_ACD_BCR] = { 0x9358 },
|
||||
[GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x93e4 },
|
||||
[GPUCC_GPU_CC_FF_BCR] = { 0x9470 },
|
||||
[GPUCC_GPU_CC_GMU_BCR] = { 0x9314 },
|
||||
[GPUCC_GPU_CC_GX_ACD_IROOT_BCR] = { 0x958c },
|
||||
};
|
||||
|
||||
static struct gdsc *gpu_cc_sm8450_gdscs[] = {
|
||||
[GPU_CX_GDSC] = &gpu_cx_gdsc,
|
||||
[GPU_GX_GDSC] = &gpu_gx_gdsc,
|
||||
};
|
||||
|
||||
static const struct regmap_config gpu_cc_sm8450_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0xa000,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static const struct qcom_cc_desc gpu_cc_sm8450_desc = {
|
||||
.config = &gpu_cc_sm8450_regmap_config,
|
||||
.clks = gpu_cc_sm8450_clocks,
|
||||
.num_clks = ARRAY_SIZE(gpu_cc_sm8450_clocks),
|
||||
.resets = gpu_cc_sm8450_resets,
|
||||
.num_resets = ARRAY_SIZE(gpu_cc_sm8450_resets),
|
||||
.gdscs = gpu_cc_sm8450_gdscs,
|
||||
.num_gdscs = ARRAY_SIZE(gpu_cc_sm8450_gdscs),
|
||||
};
|
||||
|
||||
static const struct of_device_id gpu_cc_sm8450_match_table[] = {
|
||||
{ .compatible = "qcom,sm8450-gpucc" },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, gpu_cc_sm8450_match_table);
|
||||
|
||||
static int gpu_cc_sm8450_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct regmap *regmap;
|
||||
|
||||
regmap = qcom_cc_map(pdev, &gpu_cc_sm8450_desc);
|
||||
if (IS_ERR(regmap))
|
||||
return PTR_ERR(regmap);
|
||||
|
||||
clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
|
||||
clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
|
||||
|
||||
return qcom_cc_really_probe(pdev, &gpu_cc_sm8450_desc, regmap);
|
||||
}
|
||||
|
||||
static struct platform_driver gpu_cc_sm8450_driver = {
|
||||
.probe = gpu_cc_sm8450_probe,
|
||||
.driver = {
|
||||
.name = "sm8450-gpucc",
|
||||
.of_match_table = gpu_cc_sm8450_match_table,
|
||||
},
|
||||
};
|
||||
module_platform_driver(gpu_cc_sm8450_driver);
|
||||
|
||||
MODULE_DESCRIPTION("QTI GPU_CC SM8450 Driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -0,0 +1,611 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
#include <dt-bindings/clock/qcom,sm8550-gpucc.h>
|
||||
|
||||
#include "clk-alpha-pll.h"
|
||||
#include "clk-branch.h"
|
||||
#include "clk-rcg.h"
|
||||
#include "clk-regmap.h"
|
||||
#include "clk-regmap-divider.h"
|
||||
#include "common.h"
|
||||
#include "gdsc.h"
|
||||
#include "reset.h"
|
||||
|
||||
enum {
|
||||
DT_BI_TCXO,
|
||||
DT_GPLL0_OUT_MAIN,
|
||||
DT_GPLL0_OUT_MAIN_DIV,
|
||||
};
|
||||
|
||||
enum {
|
||||
P_BI_TCXO,
|
||||
P_GPLL0_OUT_MAIN,
|
||||
P_GPLL0_OUT_MAIN_DIV,
|
||||
P_GPU_CC_PLL0_OUT_MAIN,
|
||||
P_GPU_CC_PLL1_OUT_MAIN,
|
||||
};
|
||||
|
||||
static const struct pll_vco lucid_ole_vco[] = {
|
||||
{ 249600000, 2300000000, 0 },
|
||||
};
|
||||
|
||||
static const struct alpha_pll_config gpu_cc_pll0_config = {
|
||||
/* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */
|
||||
.l = 0x4444000d,
|
||||
.alpha = 0x0,
|
||||
.config_ctl_val = 0x20485699,
|
||||
.config_ctl_hi_val = 0x00182261,
|
||||
.config_ctl_hi1_val = 0x82aa299c,
|
||||
.test_ctl_val = 0x00000000,
|
||||
.test_ctl_hi_val = 0x00000003,
|
||||
.test_ctl_hi1_val = 0x00009000,
|
||||
.test_ctl_hi2_val = 0x00000034,
|
||||
.user_ctl_val = 0x00000000,
|
||||
.user_ctl_hi_val = 0x00000005,
|
||||
};
|
||||
|
||||
static struct clk_alpha_pll gpu_cc_pll0 = {
|
||||
.offset = 0x0,
|
||||
.vco_table = lucid_ole_vco,
|
||||
.num_vco = ARRAY_SIZE(lucid_ole_vco),
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
|
||||
.clkr = {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_pll0",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.index = DT_BI_TCXO,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_lucid_evo_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct alpha_pll_config gpu_cc_pll1_config = {
|
||||
/* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */
|
||||
.l = 0x44440016,
|
||||
.alpha = 0xeaaa,
|
||||
.config_ctl_val = 0x20485699,
|
||||
.config_ctl_hi_val = 0x00182261,
|
||||
.config_ctl_hi1_val = 0x82aa299c,
|
||||
.test_ctl_val = 0x00000000,
|
||||
.test_ctl_hi_val = 0x00000003,
|
||||
.test_ctl_hi1_val = 0x00009000,
|
||||
.test_ctl_hi2_val = 0x00000034,
|
||||
.user_ctl_val = 0x00000000,
|
||||
.user_ctl_hi_val = 0x00000005,
|
||||
};
|
||||
|
||||
static struct clk_alpha_pll gpu_cc_pll1 = {
|
||||
.offset = 0x1000,
|
||||
.vco_table = lucid_ole_vco,
|
||||
.num_vco = ARRAY_SIZE(lucid_ole_vco),
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
|
||||
.clkr = {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_pll1",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.index = DT_BI_TCXO,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_lucid_evo_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct parent_map gpu_cc_parent_map_0[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_GPLL0_OUT_MAIN, 5 },
|
||||
{ P_GPLL0_OUT_MAIN_DIV, 6 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data gpu_cc_parent_data_0[] = {
|
||||
{ .index = DT_BI_TCXO },
|
||||
{ .index = DT_GPLL0_OUT_MAIN },
|
||||
{ .index = DT_GPLL0_OUT_MAIN_DIV },
|
||||
};
|
||||
|
||||
static const struct parent_map gpu_cc_parent_map_1[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
|
||||
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
|
||||
{ P_GPLL0_OUT_MAIN, 5 },
|
||||
{ P_GPLL0_OUT_MAIN_DIV, 6 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data gpu_cc_parent_data_1[] = {
|
||||
{ .index = DT_BI_TCXO },
|
||||
{ .hw = &gpu_cc_pll0.clkr.hw },
|
||||
{ .hw = &gpu_cc_pll1.clkr.hw },
|
||||
{ .index = DT_GPLL0_OUT_MAIN },
|
||||
{ .index = DT_GPLL0_OUT_MAIN_DIV },
|
||||
};
|
||||
|
||||
static const struct parent_map gpu_cc_parent_map_2[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
|
||||
{ P_GPLL0_OUT_MAIN, 5 },
|
||||
{ P_GPLL0_OUT_MAIN_DIV, 6 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data gpu_cc_parent_data_2[] = {
|
||||
{ .index = DT_BI_TCXO },
|
||||
{ .hw = &gpu_cc_pll1.clkr.hw },
|
||||
{ .index = DT_GPLL0_OUT_MAIN },
|
||||
{ .index = DT_GPLL0_OUT_MAIN_DIV },
|
||||
};
|
||||
|
||||
static const struct parent_map gpu_cc_parent_map_3[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data gpu_cc_parent_data_3[] = {
|
||||
{ .index = DT_BI_TCXO },
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = {
|
||||
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gpu_cc_ff_clk_src = {
|
||||
.cmd_rcgr = 0x9474,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = gpu_cc_parent_map_0,
|
||||
.freq_tbl = ftbl_gpu_cc_ff_clk_src,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_ff_clk_src",
|
||||
.parent_data = gpu_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
|
||||
F(19200000, P_BI_TCXO, 1, 0, 0),
|
||||
F(220000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0),
|
||||
F(550000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gpu_cc_gmu_clk_src = {
|
||||
.cmd_rcgr = 0x9318,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = gpu_cc_parent_map_1,
|
||||
.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_gmu_clk_src",
|
||||
.parent_data = gpu_cc_parent_data_1,
|
||||
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = {
|
||||
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
|
||||
F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
|
||||
F(400000000, P_GPLL0_OUT_MAIN, 1.5, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gpu_cc_hub_clk_src = {
|
||||
.cmd_rcgr = 0x93ec,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = gpu_cc_parent_map_2,
|
||||
.freq_tbl = ftbl_gpu_cc_hub_clk_src,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_hub_clk_src",
|
||||
.parent_data = gpu_cc_parent_data_2,
|
||||
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_2),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gpu_cc_xo_clk_src[] = {
|
||||
F(19200000, P_BI_TCXO, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gpu_cc_xo_clk_src = {
|
||||
.cmd_rcgr = 0x9010,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = gpu_cc_parent_map_3,
|
||||
.freq_tbl = ftbl_gpu_cc_xo_clk_src,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_xo_clk_src",
|
||||
.parent_data = gpu_cc_parent_data_3,
|
||||
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_3),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_div gpu_cc_demet_div_clk_src = {
|
||||
.reg = 0x9054,
|
||||
.shift = 0,
|
||||
.width = 4,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_demet_div_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpu_cc_xo_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_regmap_div_ro_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_div gpu_cc_xo_div_clk_src = {
|
||||
.reg = 0x9050,
|
||||
.shift = 0,
|
||||
.width = 4,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_xo_div_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpu_cc_xo_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_regmap_div_ro_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_ahb_clk = {
|
||||
.halt_reg = 0x911c,
|
||||
.halt_check = BRANCH_HALT_DELAY,
|
||||
.clkr = {
|
||||
.enable_reg = 0x911c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_ahb_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpu_cc_hub_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_crc_ahb_clk = {
|
||||
.halt_reg = 0x9120,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9120,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_crc_ahb_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpu_cc_hub_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_cx_ff_clk = {
|
||||
.halt_reg = 0x914c,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x914c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_cx_ff_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpu_cc_ff_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_cx_gmu_clk = {
|
||||
.halt_reg = 0x913c,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x913c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_cx_gmu_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpu_cc_gmu_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_aon_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_cxo_clk = {
|
||||
.halt_reg = 0x9144,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9144,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_cxo_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpu_cc_xo_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_freq_measure_clk = {
|
||||
.halt_reg = 0x9008,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9008,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_freq_measure_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpu_cc_xo_div_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
|
||||
.halt_reg = 0x7000,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x7000,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_hub_aon_clk = {
|
||||
.halt_reg = 0x93e8,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x93e8,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_hub_aon_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpu_cc_hub_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_aon_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_hub_cx_int_clk = {
|
||||
.halt_reg = 0x9148,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9148,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_hub_cx_int_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&gpu_cc_hub_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_aon_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_memnoc_gfx_clk = {
|
||||
.halt_reg = 0x9150,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9150,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_memnoc_gfx_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk = {
|
||||
.halt_reg = 0x9288,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9288,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_mnd1x_0_gfx3d_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_mnd1x_1_gfx3d_clk = {
|
||||
.halt_reg = 0x928c,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x928c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_mnd1x_1_gfx3d_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_sleep_clk = {
|
||||
.halt_reg = 0x9134,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9134,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpu_cc_sleep_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct gdsc gpu_cc_cx_gdsc = {
|
||||
.gdscr = 0x9108,
|
||||
.gds_hw_ctrl = 0x953c,
|
||||
.en_rest_wait_val = 0x2,
|
||||
.en_few_wait_val = 0x2,
|
||||
.clk_dis_wait_val = 0xf,
|
||||
.pd = {
|
||||
.name = "gpu_cc_cx_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = RETAIN_FF_ENABLE | VOTABLE,
|
||||
};
|
||||
|
||||
static struct gdsc gpu_cc_gx_gdsc = {
|
||||
.gdscr = 0x905c,
|
||||
.clamp_io_ctrl = 0x9504,
|
||||
.en_rest_wait_val = 0x2,
|
||||
.en_few_wait_val = 0x2,
|
||||
.clk_dis_wait_val = 0xf,
|
||||
.pd = {
|
||||
.name = "gpu_cc_gx_gdsc",
|
||||
.power_on = gdsc_gx_do_nothing_enable,
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = CLAMP_IO | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
|
||||
};
|
||||
|
||||
static struct clk_regmap *gpu_cc_sm8550_clocks[] = {
|
||||
[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
|
||||
[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
|
||||
[GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr,
|
||||
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
|
||||
[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
|
||||
[GPU_CC_DEMET_DIV_CLK_SRC] = &gpu_cc_demet_div_clk_src.clkr,
|
||||
[GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr,
|
||||
[GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr,
|
||||
[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
|
||||
[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
|
||||
[GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
|
||||
[GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,
|
||||
[GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr,
|
||||
[GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr,
|
||||
[GPU_CC_MND1X_0_GFX3D_CLK] = &gpu_cc_mnd1x_0_gfx3d_clk.clkr,
|
||||
[GPU_CC_MND1X_1_GFX3D_CLK] = &gpu_cc_mnd1x_1_gfx3d_clk.clkr,
|
||||
[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
|
||||
[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
|
||||
[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
|
||||
[GPU_CC_XO_CLK_SRC] = &gpu_cc_xo_clk_src.clkr,
|
||||
[GPU_CC_XO_DIV_CLK_SRC] = &gpu_cc_xo_div_clk_src.clkr,
|
||||
};
|
||||
|
||||
static struct gdsc *gpu_cc_sm8550_gdscs[] = {
|
||||
[GPU_CC_CX_GDSC] = &gpu_cc_cx_gdsc,
|
||||
[GPU_CC_GX_GDSC] = &gpu_cc_gx_gdsc,
|
||||
};
|
||||
|
||||
static const struct qcom_reset_map gpu_cc_sm8550_resets[] = {
|
||||
[GPUCC_GPU_CC_ACD_BCR] = { 0x9358 },
|
||||
[GPUCC_GPU_CC_CX_BCR] = { 0x9104 },
|
||||
[GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x93e4 },
|
||||
[GPUCC_GPU_CC_FF_BCR] = { 0x9470 },
|
||||
[GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x9198 },
|
||||
[GPUCC_GPU_CC_GMU_BCR] = { 0x9314 },
|
||||
[GPUCC_GPU_CC_GX_BCR] = { 0x9058 },
|
||||
[GPUCC_GPU_CC_XO_BCR] = { 0x9000 },
|
||||
};
|
||||
|
||||
static const struct regmap_config gpu_cc_sm8550_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0x9988,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static const struct qcom_cc_desc gpu_cc_sm8550_desc = {
|
||||
.config = &gpu_cc_sm8550_regmap_config,
|
||||
.clks = gpu_cc_sm8550_clocks,
|
||||
.num_clks = ARRAY_SIZE(gpu_cc_sm8550_clocks),
|
||||
.resets = gpu_cc_sm8550_resets,
|
||||
.num_resets = ARRAY_SIZE(gpu_cc_sm8550_resets),
|
||||
.gdscs = gpu_cc_sm8550_gdscs,
|
||||
.num_gdscs = ARRAY_SIZE(gpu_cc_sm8550_gdscs),
|
||||
};
|
||||
|
||||
static const struct of_device_id gpu_cc_sm8550_match_table[] = {
|
||||
{ .compatible = "qcom,sm8550-gpucc" },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, gpu_cc_sm8550_match_table);
|
||||
|
||||
static int gpu_cc_sm8550_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct regmap *regmap;
|
||||
|
||||
regmap = qcom_cc_map(pdev, &gpu_cc_sm8550_desc);
|
||||
if (IS_ERR(regmap))
|
||||
return PTR_ERR(regmap);
|
||||
|
||||
clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
|
||||
clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
|
||||
|
||||
/*
|
||||
* Keep clocks always enabled:
|
||||
* gpu_cc_cxo_aon_clk
|
||||
* gpu_cc_demet_clk
|
||||
*/
|
||||
regmap_update_bits(regmap, 0x9004, BIT(0), BIT(0));
|
||||
regmap_update_bits(regmap, 0x900c, BIT(0), BIT(0));
|
||||
|
||||
return qcom_cc_really_probe(pdev, &gpu_cc_sm8550_desc, regmap);
|
||||
}
|
||||
|
||||
static struct platform_driver gpu_cc_sm8550_driver = {
|
||||
.probe = gpu_cc_sm8550_probe,
|
||||
.driver = {
|
||||
.name = "gpu_cc-sm8550",
|
||||
.of_match_table = gpu_cc_sm8550_match_table,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init gpu_cc_sm8550_init(void)
|
||||
{
|
||||
return platform_driver_register(&gpu_cc_sm8550_driver);
|
||||
}
|
||||
subsys_initcall(gpu_cc_sm8550_init);
|
||||
|
||||
static void __exit gpu_cc_sm8550_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&gpu_cc_sm8550_driver);
|
||||
}
|
||||
module_exit(gpu_cc_sm8550_exit);
|
||||
|
||||
MODULE_DESCRIPTION("QTI GPUCC SM8550 Driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -0,0 +1,87 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2022, Linaro Limited
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "reset.h"
|
||||
|
||||
static const struct qcom_reset_map lpass_audiocc_sc8280xp_resets[] = {
|
||||
[LPASS_AUDIO_SWR_RX_CGCR] = { 0xa0, 1 },
|
||||
[LPASS_AUDIO_SWR_WSA_CGCR] = { 0xb0, 1 },
|
||||
[LPASS_AUDIO_SWR_WSA2_CGCR] = { 0xd8, 1 },
|
||||
};
|
||||
|
||||
static struct regmap_config lpass_audiocc_sc8280xp_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.name = "lpass-audio-csr",
|
||||
.max_register = 0x1000,
|
||||
};
|
||||
|
||||
static const struct qcom_cc_desc lpass_audiocc_sc8280xp_reset_desc = {
|
||||
.config = &lpass_audiocc_sc8280xp_regmap_config,
|
||||
.resets = lpass_audiocc_sc8280xp_resets,
|
||||
.num_resets = ARRAY_SIZE(lpass_audiocc_sc8280xp_resets),
|
||||
};
|
||||
|
||||
static const struct qcom_reset_map lpasscc_sc8280xp_resets[] = {
|
||||
[LPASS_AUDIO_SWR_TX_CGCR] = { 0xc010, 1 },
|
||||
};
|
||||
|
||||
static struct regmap_config lpasscc_sc8280xp_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.name = "lpass-tcsr",
|
||||
.max_register = 0x12000,
|
||||
};
|
||||
|
||||
static const struct qcom_cc_desc lpasscc_sc8280xp_reset_desc = {
|
||||
.config = &lpasscc_sc8280xp_regmap_config,
|
||||
.resets = lpasscc_sc8280xp_resets,
|
||||
.num_resets = ARRAY_SIZE(lpasscc_sc8280xp_resets),
|
||||
};
|
||||
|
||||
static const struct of_device_id lpasscc_sc8280xp_match_table[] = {
|
||||
{
|
||||
.compatible = "qcom,sc8280xp-lpassaudiocc",
|
||||
.data = &lpass_audiocc_sc8280xp_reset_desc,
|
||||
}, {
|
||||
.compatible = "qcom,sc8280xp-lpasscc",
|
||||
.data = &lpasscc_sc8280xp_reset_desc,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, lpasscc_sc8280xp_match_table);
|
||||
|
||||
static int lpasscc_sc8280xp_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct qcom_cc_desc *desc = of_device_get_match_data(&pdev->dev);
|
||||
|
||||
return qcom_cc_probe_by_index(pdev, 0, desc);
|
||||
}
|
||||
|
||||
static struct platform_driver lpasscc_sc8280xp_driver = {
|
||||
.probe = lpasscc_sc8280xp_probe,
|
||||
.driver = {
|
||||
.name = "lpasscc-sc8280xp",
|
||||
.of_match_table = lpasscc_sc8280xp_match_table,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(lpasscc_sc8280xp_driver);
|
||||
|
||||
MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org>");
|
||||
MODULE_DESCRIPTION("QTI LPASSCC SC8280XP Driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -485,7 +485,7 @@ static struct clk_rcg2 mdp_clk_src = {
|
|||
.name = "mdp_clk_src",
|
||||
.parent_data = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
|
||||
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_dsi_hdmi_gpll0),
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -2204,23 +2204,6 @@ static struct clk_branch ocmemcx_ocmemnoc_clk = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct clk_branch oxili_ocmemgx_clk = {
|
||||
.halt_reg = 0x402c,
|
||||
.clkr = {
|
||||
.enable_reg = 0x402c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "oxili_ocmemgx_clk",
|
||||
.parent_data = (const struct clk_parent_data[]){
|
||||
{ .fw_name = "gfx3d_clk_src", .name = "gfx3d_clk_src" },
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch ocmemnoc_clk = {
|
||||
.halt_reg = 0x50b4,
|
||||
.clkr = {
|
||||
|
|
@ -2401,7 +2384,7 @@ static struct gdsc mdss_gdsc = {
|
|||
.pd = {
|
||||
.name = "mdss",
|
||||
},
|
||||
.pwrsts = PWRSTS_RET_ON,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
};
|
||||
|
||||
static struct gdsc camss_jpeg_gdsc = {
|
||||
|
|
@ -2512,7 +2495,6 @@ static struct clk_regmap *mmcc_msm8226_clocks[] = {
|
|||
[MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
|
||||
[MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
|
||||
[OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
|
||||
[OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr,
|
||||
[OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
|
||||
[OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
|
||||
[OXILICX_AXI_CLK] = &oxilicx_axi_clk.clkr,
|
||||
|
|
@ -2670,7 +2652,6 @@ static struct clk_regmap *mmcc_msm8974_clocks[] = {
|
|||
[MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
|
||||
[OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
|
||||
[OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
|
||||
[OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr,
|
||||
[OCMEMNOC_CLK] = &ocmemnoc_clk.clkr,
|
||||
[OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
|
||||
[OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
|
||||
|
|
|
|||
|
|
@ -0,0 +1,552 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2023, Linaro Limited
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_clock.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
#include <dt-bindings/clock/qcom,sm8350-videocc.h>
|
||||
#include <dt-bindings/reset/qcom,sm8350-videocc.h>
|
||||
|
||||
#include "clk-alpha-pll.h"
|
||||
#include "clk-branch.h"
|
||||
#include "clk-rcg.h"
|
||||
#include "clk-regmap.h"
|
||||
#include "clk-regmap-divider.h"
|
||||
#include "common.h"
|
||||
#include "reset.h"
|
||||
#include "gdsc.h"
|
||||
|
||||
enum {
|
||||
DT_BI_TCXO,
|
||||
DT_BI_TCXO_AO,
|
||||
DT_SLEEP_CLK,
|
||||
};
|
||||
|
||||
enum {
|
||||
P_BI_TCXO,
|
||||
P_BI_TCXO_AO,
|
||||
P_SLEEP_CLK,
|
||||
P_VIDEO_PLL0_OUT_MAIN,
|
||||
P_VIDEO_PLL1_OUT_MAIN,
|
||||
};
|
||||
|
||||
static const struct pll_vco lucid_5lpe_vco[] = {
|
||||
{ 249600000, 1750000000, 0 },
|
||||
};
|
||||
|
||||
static const struct alpha_pll_config video_pll0_config = {
|
||||
.l = 0x25,
|
||||
.alpha = 0x8000,
|
||||
.config_ctl_val = 0x20485699,
|
||||
.config_ctl_hi_val = 0x00002261,
|
||||
.config_ctl_hi1_val = 0x2a9a699c,
|
||||
.test_ctl_val = 0x00000000,
|
||||
.test_ctl_hi_val = 0x00000000,
|
||||
.test_ctl_hi1_val = 0x01800000,
|
||||
.user_ctl_val = 0x00000000,
|
||||
.user_ctl_hi_val = 0x00000805,
|
||||
.user_ctl_hi1_val = 0x00000000,
|
||||
};
|
||||
|
||||
static struct clk_alpha_pll video_pll0 = {
|
||||
.offset = 0x42c,
|
||||
.vco_table = lucid_5lpe_vco,
|
||||
.num_vco = ARRAY_SIZE(lucid_5lpe_vco),
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
|
||||
.clkr = {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "video_pll0",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.index = DT_BI_TCXO,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_lucid_5lpe_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct alpha_pll_config video_pll1_config = {
|
||||
.l = 0x2b,
|
||||
.alpha = 0xc000,
|
||||
.config_ctl_val = 0x20485699,
|
||||
.config_ctl_hi_val = 0x00002261,
|
||||
.config_ctl_hi1_val = 0x2a9a699c,
|
||||
.test_ctl_val = 0x00000000,
|
||||
.test_ctl_hi_val = 0x00000000,
|
||||
.test_ctl_hi1_val = 0x01800000,
|
||||
.user_ctl_val = 0x00000000,
|
||||
.user_ctl_hi_val = 0x00000805,
|
||||
.user_ctl_hi1_val = 0x00000000,
|
||||
};
|
||||
|
||||
static struct clk_alpha_pll video_pll1 = {
|
||||
.offset = 0x7d0,
|
||||
.vco_table = lucid_5lpe_vco,
|
||||
.num_vco = ARRAY_SIZE(lucid_5lpe_vco),
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
|
||||
.clkr = {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "video_pll1",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.index = DT_BI_TCXO,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_lucid_5lpe_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct parent_map video_cc_parent_map_0[] = {
|
||||
{ P_BI_TCXO_AO, 0 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data video_cc_parent_data_0[] = {
|
||||
{ .index = DT_BI_TCXO_AO },
|
||||
};
|
||||
|
||||
static const struct parent_map video_cc_parent_map_1[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_VIDEO_PLL0_OUT_MAIN, 1 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data video_cc_parent_data_1[] = {
|
||||
{ .index = DT_BI_TCXO },
|
||||
{ .hw = &video_pll0.clkr.hw },
|
||||
};
|
||||
|
||||
static const struct parent_map video_cc_parent_map_2[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_VIDEO_PLL1_OUT_MAIN, 1 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data video_cc_parent_data_2[] = {
|
||||
{ .index = DT_BI_TCXO },
|
||||
{ .hw = &video_pll1.clkr.hw },
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_video_cc_ahb_clk_src[] = {
|
||||
F(19200000, P_BI_TCXO, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 video_cc_ahb_clk_src = {
|
||||
.cmd_rcgr = 0xbd4,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = video_cc_parent_map_0,
|
||||
.freq_tbl = ftbl_video_cc_ahb_clk_src,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "video_cc_ahb_clk_src",
|
||||
.parent_data = video_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(video_cc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = {
|
||||
F(720000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
|
||||
F(1014000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
|
||||
F(1098000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
|
||||
F(1332000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 video_cc_mvs0_clk_src = {
|
||||
.cmd_rcgr = 0xb94,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = video_cc_parent_map_1,
|
||||
.freq_tbl = ftbl_video_cc_mvs0_clk_src,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "video_cc_mvs0_clk_src",
|
||||
.parent_data = video_cc_parent_data_1,
|
||||
.num_parents = ARRAY_SIZE(video_cc_parent_data_1),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = {
|
||||
F(840000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
|
||||
F(1098000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
|
||||
F(1332000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 video_cc_mvs1_clk_src = {
|
||||
.cmd_rcgr = 0xbb4,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = video_cc_parent_map_2,
|
||||
.freq_tbl = ftbl_video_cc_mvs1_clk_src,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "video_cc_mvs1_clk_src",
|
||||
.parent_data = video_cc_parent_data_2,
|
||||
.num_parents = ARRAY_SIZE(video_cc_parent_data_2),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_video_cc_sleep_clk_src[] = {
|
||||
F(32000, P_SLEEP_CLK, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 video_cc_sleep_clk_src = {
|
||||
.cmd_rcgr = 0xef0,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.freq_tbl = ftbl_video_cc_sleep_clk_src,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "video_cc_sleep_clk_src",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.index = DT_SLEEP_CLK,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_rcg2 video_cc_xo_clk_src = {
|
||||
.cmd_rcgr = 0xecc,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = video_cc_parent_map_0,
|
||||
.freq_tbl = ftbl_video_cc_ahb_clk_src,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "video_cc_xo_clk_src",
|
||||
.parent_data = video_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(video_cc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_div video_cc_mvs0_div_clk_src = {
|
||||
.reg = 0xd54,
|
||||
.shift = 0,
|
||||
.width = 4,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "video_cc_mvs0_div_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&video_cc_mvs0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_regmap_div_ro_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src = {
|
||||
.reg = 0xc54,
|
||||
.shift = 0,
|
||||
.width = 4,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "video_cc_mvs0c_div2_div_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&video_cc_mvs0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_regmap_div_ro_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_div video_cc_mvs1_div_clk_src = {
|
||||
.reg = 0xdd4,
|
||||
.shift = 0,
|
||||
.width = 4,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "video_cc_mvs1_div_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&video_cc_mvs1_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_regmap_div_ro_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_div video_cc_mvs1c_div2_div_clk_src = {
|
||||
.reg = 0xcf4,
|
||||
.shift = 0,
|
||||
.width = 4,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "video_cc_mvs1c_div2_div_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&video_cc_mvs1_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_regmap_div_ro_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch video_cc_mvs0_clk = {
|
||||
.halt_reg = 0xd34,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.hwcg_reg = 0xd34,
|
||||
.hwcg_bit = 1,
|
||||
.clkr = {
|
||||
.enable_reg = 0xd34,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "video_cc_mvs0_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&video_cc_mvs0_div_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch video_cc_mvs0c_clk = {
|
||||
.halt_reg = 0xc34,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0xc34,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "video_cc_mvs0c_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&video_cc_mvs0c_div2_div_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch video_cc_mvs1_clk = {
|
||||
.halt_reg = 0xdb4,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.hwcg_reg = 0xdb4,
|
||||
.hwcg_bit = 1,
|
||||
.clkr = {
|
||||
.enable_reg = 0xdb4,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "video_cc_mvs1_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&video_cc_mvs1_div_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch video_cc_mvs1_div2_clk = {
|
||||
.halt_reg = 0xdf4,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.hwcg_reg = 0xdf4,
|
||||
.hwcg_bit = 1,
|
||||
.clkr = {
|
||||
.enable_reg = 0xdf4,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "video_cc_mvs1_div2_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&video_cc_mvs1c_div2_div_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch video_cc_mvs1c_clk = {
|
||||
.halt_reg = 0xcd4,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0xcd4,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "video_cc_mvs1c_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&video_cc_mvs1c_div2_div_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch video_cc_sleep_clk = {
|
||||
.halt_reg = 0xf10,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0xf10,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "video_cc_sleep_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&video_cc_sleep_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct gdsc mvs0c_gdsc = {
|
||||
.gdscr = 0xbf8,
|
||||
.pd = {
|
||||
.name = "mvs0c_gdsc",
|
||||
},
|
||||
.flags = RETAIN_FF_ENABLE,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
};
|
||||
|
||||
static struct gdsc mvs1c_gdsc = {
|
||||
.gdscr = 0xc98,
|
||||
.pd = {
|
||||
.name = "mvs1c_gdsc",
|
||||
},
|
||||
.flags = RETAIN_FF_ENABLE,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
};
|
||||
|
||||
static struct gdsc mvs0_gdsc = {
|
||||
.gdscr = 0xd18,
|
||||
.pd = {
|
||||
.name = "mvs0_gdsc",
|
||||
},
|
||||
.flags = HW_CTRL | RETAIN_FF_ENABLE,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
};
|
||||
|
||||
static struct gdsc mvs1_gdsc = {
|
||||
.gdscr = 0xd98,
|
||||
.pd = {
|
||||
.name = "mvs1_gdsc",
|
||||
},
|
||||
.flags = HW_CTRL | RETAIN_FF_ENABLE,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
};
|
||||
|
||||
static struct clk_regmap *video_cc_sm8350_clocks[] = {
|
||||
[VIDEO_CC_AHB_CLK_SRC] = &video_cc_ahb_clk_src.clkr,
|
||||
[VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr,
|
||||
[VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr,
|
||||
[VIDEO_CC_MVS0_DIV_CLK_SRC] = &video_cc_mvs0_div_clk_src.clkr,
|
||||
[VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr,
|
||||
[VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] = &video_cc_mvs0c_div2_div_clk_src.clkr,
|
||||
[VIDEO_CC_MVS1_CLK] = &video_cc_mvs1_clk.clkr,
|
||||
[VIDEO_CC_MVS1_CLK_SRC] = &video_cc_mvs1_clk_src.clkr,
|
||||
[VIDEO_CC_MVS1_DIV2_CLK] = &video_cc_mvs1_div2_clk.clkr,
|
||||
[VIDEO_CC_MVS1_DIV_CLK_SRC] = &video_cc_mvs1_div_clk_src.clkr,
|
||||
[VIDEO_CC_MVS1C_CLK] = &video_cc_mvs1c_clk.clkr,
|
||||
[VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] = &video_cc_mvs1c_div2_div_clk_src.clkr,
|
||||
[VIDEO_CC_SLEEP_CLK] = &video_cc_sleep_clk.clkr,
|
||||
[VIDEO_CC_SLEEP_CLK_SRC] = &video_cc_sleep_clk_src.clkr,
|
||||
[VIDEO_CC_XO_CLK_SRC] = &video_cc_xo_clk_src.clkr,
|
||||
[VIDEO_PLL0] = &video_pll0.clkr,
|
||||
[VIDEO_PLL1] = &video_pll1.clkr,
|
||||
};
|
||||
|
||||
static const struct qcom_reset_map video_cc_sm8350_resets[] = {
|
||||
[VIDEO_CC_CVP_INTERFACE_BCR] = { 0xe54 },
|
||||
[VIDEO_CC_CVP_MVS0_BCR] = { 0xd14 },
|
||||
[VIDEO_CC_MVS0C_CLK_ARES] = { 0xc34, 2 },
|
||||
[VIDEO_CC_CVP_MVS0C_BCR] = { 0xbf4 },
|
||||
[VIDEO_CC_CVP_MVS1_BCR] = { 0xd94 },
|
||||
[VIDEO_CC_MVS1C_CLK_ARES] = { 0xcd4, 2 },
|
||||
[VIDEO_CC_CVP_MVS1C_BCR] = { 0xc94 },
|
||||
};
|
||||
|
||||
static struct gdsc *video_cc_sm8350_gdscs[] = {
|
||||
[MVS0C_GDSC] = &mvs0c_gdsc,
|
||||
[MVS1C_GDSC] = &mvs1c_gdsc,
|
||||
[MVS0_GDSC] = &mvs0_gdsc,
|
||||
[MVS1_GDSC] = &mvs1_gdsc,
|
||||
};
|
||||
|
||||
static const struct regmap_config video_cc_sm8350_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0x10000,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static struct qcom_cc_desc video_cc_sm8350_desc = {
|
||||
.config = &video_cc_sm8350_regmap_config,
|
||||
.clks = video_cc_sm8350_clocks,
|
||||
.num_clks = ARRAY_SIZE(video_cc_sm8350_clocks),
|
||||
.resets = video_cc_sm8350_resets,
|
||||
.num_resets = ARRAY_SIZE(video_cc_sm8350_resets),
|
||||
.gdscs = video_cc_sm8350_gdscs,
|
||||
.num_gdscs = ARRAY_SIZE(video_cc_sm8350_gdscs),
|
||||
};
|
||||
|
||||
static int video_cc_sm8350_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct regmap *regmap;
|
||||
int ret;
|
||||
|
||||
ret = devm_pm_runtime_enable(&pdev->dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = pm_runtime_resume_and_get(&pdev->dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
regmap = qcom_cc_map(pdev, &video_cc_sm8350_desc);
|
||||
if (IS_ERR(regmap)) {
|
||||
pm_runtime_put(&pdev->dev);
|
||||
return PTR_ERR(regmap);
|
||||
}
|
||||
|
||||
clk_lucid_pll_configure(&video_pll0, regmap, &video_pll0_config);
|
||||
clk_lucid_pll_configure(&video_pll1, regmap, &video_pll1_config);
|
||||
|
||||
/*
|
||||
* Keep clocks always enabled:
|
||||
* video_cc_ahb_clk
|
||||
* video_cc_xo_clk
|
||||
*/
|
||||
regmap_update_bits(regmap, 0xe58, BIT(0), BIT(0));
|
||||
regmap_update_bits(regmap, 0xeec, BIT(0), BIT(0));
|
||||
|
||||
ret = qcom_cc_really_probe(pdev, &video_cc_sm8350_desc, regmap);
|
||||
pm_runtime_put(&pdev->dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct of_device_id video_cc_sm8350_match_table[] = {
|
||||
{ .compatible = "qcom,sm8350-videocc" },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, video_cc_sm8350_match_table);
|
||||
|
||||
static struct platform_driver video_cc_sm8350_driver = {
|
||||
.probe = video_cc_sm8350_probe,
|
||||
.driver = {
|
||||
.name = "sm8350-videocc",
|
||||
.of_match_table = video_cc_sm8350_match_table,
|
||||
},
|
||||
};
|
||||
module_platform_driver(video_cc_sm8350_driver);
|
||||
|
||||
MODULE_DESCRIPTION("QTI SM8350 VIDEOCC Driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -0,0 +1,463 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
#include <dt-bindings/clock/qcom,sm8450-videocc.h>
|
||||
|
||||
#include "clk-alpha-pll.h"
|
||||
#include "clk-branch.h"
|
||||
#include "clk-rcg.h"
|
||||
#include "clk-regmap.h"
|
||||
#include "clk-regmap-divider.h"
|
||||
#include "common.h"
|
||||
#include "gdsc.h"
|
||||
#include "reset.h"
|
||||
|
||||
enum {
|
||||
DT_BI_TCXO,
|
||||
};
|
||||
|
||||
enum {
|
||||
P_BI_TCXO,
|
||||
P_VIDEO_CC_PLL0_OUT_MAIN,
|
||||
P_VIDEO_CC_PLL1_OUT_MAIN,
|
||||
};
|
||||
|
||||
static const struct pll_vco lucid_evo_vco[] = {
|
||||
{ 249600000, 2020000000, 0 },
|
||||
};
|
||||
|
||||
static const struct alpha_pll_config video_cc_pll0_config = {
|
||||
/* .l includes CAL_L_VAL, L_VAL fields */
|
||||
.l = 0x0044001e,
|
||||
.alpha = 0x0,
|
||||
.config_ctl_val = 0x20485699,
|
||||
.config_ctl_hi_val = 0x00182261,
|
||||
.config_ctl_hi1_val = 0x32aa299c,
|
||||
.user_ctl_val = 0x00000000,
|
||||
.user_ctl_hi_val = 0x00000805,
|
||||
};
|
||||
|
||||
static struct clk_alpha_pll video_cc_pll0 = {
|
||||
.offset = 0x0,
|
||||
.vco_table = lucid_evo_vco,
|
||||
.num_vco = ARRAY_SIZE(lucid_evo_vco),
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
|
||||
.clkr = {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "video_cc_pll0",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.index = DT_BI_TCXO,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_lucid_evo_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct alpha_pll_config video_cc_pll1_config = {
|
||||
/* .l includes CAL_L_VAL, L_VAL fields */
|
||||
.l = 0x0044002b,
|
||||
.alpha = 0xc000,
|
||||
.config_ctl_val = 0x20485699,
|
||||
.config_ctl_hi_val = 0x00182261,
|
||||
.config_ctl_hi1_val = 0x32aa299c,
|
||||
.user_ctl_val = 0x00000000,
|
||||
.user_ctl_hi_val = 0x00000805,
|
||||
};
|
||||
|
||||
static struct clk_alpha_pll video_cc_pll1 = {
|
||||
.offset = 0x1000,
|
||||
.vco_table = lucid_evo_vco,
|
||||
.num_vco = ARRAY_SIZE(lucid_evo_vco),
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
|
||||
.clkr = {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "video_cc_pll1",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.index = DT_BI_TCXO,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_lucid_evo_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct parent_map video_cc_parent_map_0[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_VIDEO_CC_PLL0_OUT_MAIN, 1 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data video_cc_parent_data_0[] = {
|
||||
{ .index = DT_BI_TCXO },
|
||||
{ .hw = &video_cc_pll0.clkr.hw },
|
||||
};
|
||||
|
||||
static const struct parent_map video_cc_parent_map_1[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_VIDEO_CC_PLL1_OUT_MAIN, 1 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data video_cc_parent_data_1[] = {
|
||||
{ .index = DT_BI_TCXO },
|
||||
{ .hw = &video_cc_pll1.clkr.hw },
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = {
|
||||
F(576000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
|
||||
F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
|
||||
F(1014000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
|
||||
F(1098000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
|
||||
F(1332000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 video_cc_mvs0_clk_src = {
|
||||
.cmd_rcgr = 0x8000,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = video_cc_parent_map_0,
|
||||
.freq_tbl = ftbl_video_cc_mvs0_clk_src,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "video_cc_mvs0_clk_src",
|
||||
.parent_data = video_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(video_cc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = {
|
||||
F(840000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
|
||||
F(1050000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
|
||||
F(1350000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
|
||||
F(1500000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
|
||||
F(1650000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 video_cc_mvs1_clk_src = {
|
||||
.cmd_rcgr = 0x8018,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = video_cc_parent_map_1,
|
||||
.freq_tbl = ftbl_video_cc_mvs1_clk_src,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "video_cc_mvs1_clk_src",
|
||||
.parent_data = video_cc_parent_data_1,
|
||||
.num_parents = ARRAY_SIZE(video_cc_parent_data_1),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_div video_cc_mvs0_div_clk_src = {
|
||||
.reg = 0x80b8,
|
||||
.shift = 0,
|
||||
.width = 4,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "video_cc_mvs0_div_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&video_cc_mvs0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_regmap_div_ro_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src = {
|
||||
.reg = 0x806c,
|
||||
.shift = 0,
|
||||
.width = 4,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "video_cc_mvs0c_div2_div_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&video_cc_mvs0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_regmap_div_ro_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_div video_cc_mvs1_div_clk_src = {
|
||||
.reg = 0x80dc,
|
||||
.shift = 0,
|
||||
.width = 4,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "video_cc_mvs1_div_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&video_cc_mvs1_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_regmap_div_ro_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_div video_cc_mvs1c_div2_div_clk_src = {
|
||||
.reg = 0x8094,
|
||||
.shift = 0,
|
||||
.width = 4,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "video_cc_mvs1c_div2_div_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&video_cc_mvs1_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_regmap_div_ro_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch video_cc_mvs0_clk = {
|
||||
.halt_reg = 0x80b0,
|
||||
.halt_check = BRANCH_HALT_SKIP,
|
||||
.hwcg_reg = 0x80b0,
|
||||
.hwcg_bit = 1,
|
||||
.clkr = {
|
||||
.enable_reg = 0x80b0,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "video_cc_mvs0_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&video_cc_mvs0_div_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch video_cc_mvs0c_clk = {
|
||||
.halt_reg = 0x8064,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x8064,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "video_cc_mvs0c_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&video_cc_mvs0c_div2_div_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch video_cc_mvs1_clk = {
|
||||
.halt_reg = 0x80d4,
|
||||
.halt_check = BRANCH_HALT_SKIP,
|
||||
.hwcg_reg = 0x80d4,
|
||||
.hwcg_bit = 1,
|
||||
.clkr = {
|
||||
.enable_reg = 0x80d4,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "video_cc_mvs1_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&video_cc_mvs1_div_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch video_cc_mvs1c_clk = {
|
||||
.halt_reg = 0x808c,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x808c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "video_cc_mvs1c_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&video_cc_mvs1c_div2_div_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct gdsc video_cc_mvs0c_gdsc = {
|
||||
.gdscr = 0x804c,
|
||||
.en_rest_wait_val = 0x2,
|
||||
.en_few_wait_val = 0x2,
|
||||
.clk_dis_wait_val = 0x6,
|
||||
.pd = {
|
||||
.name = "video_cc_mvs0c_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = RETAIN_FF_ENABLE,
|
||||
};
|
||||
|
||||
static struct gdsc video_cc_mvs0_gdsc = {
|
||||
.gdscr = 0x809c,
|
||||
.en_rest_wait_val = 0x2,
|
||||
.en_few_wait_val = 0x2,
|
||||
.clk_dis_wait_val = 0x6,
|
||||
.pd = {
|
||||
.name = "video_cc_mvs0_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.parent = &video_cc_mvs0c_gdsc.pd,
|
||||
.flags = RETAIN_FF_ENABLE | HW_CTRL,
|
||||
};
|
||||
|
||||
static struct gdsc video_cc_mvs1c_gdsc = {
|
||||
.gdscr = 0x8074,
|
||||
.en_rest_wait_val = 0x2,
|
||||
.en_few_wait_val = 0x2,
|
||||
.clk_dis_wait_val = 0x6,
|
||||
.pd = {
|
||||
.name = "video_cc_mvs1c_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = RETAIN_FF_ENABLE,
|
||||
};
|
||||
|
||||
static struct gdsc video_cc_mvs1_gdsc = {
|
||||
.gdscr = 0x80c0,
|
||||
.en_rest_wait_val = 0x2,
|
||||
.en_few_wait_val = 0x2,
|
||||
.clk_dis_wait_val = 0x6,
|
||||
.pd = {
|
||||
.name = "video_cc_mvs1_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.parent = &video_cc_mvs1c_gdsc.pd,
|
||||
.flags = RETAIN_FF_ENABLE | HW_CTRL,
|
||||
};
|
||||
|
||||
static struct clk_regmap *video_cc_sm8450_clocks[] = {
|
||||
[VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr,
|
||||
[VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr,
|
||||
[VIDEO_CC_MVS0_DIV_CLK_SRC] = &video_cc_mvs0_div_clk_src.clkr,
|
||||
[VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr,
|
||||
[VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] = &video_cc_mvs0c_div2_div_clk_src.clkr,
|
||||
[VIDEO_CC_MVS1_CLK] = &video_cc_mvs1_clk.clkr,
|
||||
[VIDEO_CC_MVS1_CLK_SRC] = &video_cc_mvs1_clk_src.clkr,
|
||||
[VIDEO_CC_MVS1_DIV_CLK_SRC] = &video_cc_mvs1_div_clk_src.clkr,
|
||||
[VIDEO_CC_MVS1C_CLK] = &video_cc_mvs1c_clk.clkr,
|
||||
[VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] = &video_cc_mvs1c_div2_div_clk_src.clkr,
|
||||
[VIDEO_CC_PLL0] = &video_cc_pll0.clkr,
|
||||
[VIDEO_CC_PLL1] = &video_cc_pll1.clkr,
|
||||
};
|
||||
|
||||
static struct gdsc *video_cc_sm8450_gdscs[] = {
|
||||
[VIDEO_CC_MVS0C_GDSC] = &video_cc_mvs0c_gdsc,
|
||||
[VIDEO_CC_MVS0_GDSC] = &video_cc_mvs0_gdsc,
|
||||
[VIDEO_CC_MVS1C_GDSC] = &video_cc_mvs1c_gdsc,
|
||||
[VIDEO_CC_MVS1_GDSC] = &video_cc_mvs1_gdsc,
|
||||
};
|
||||
|
||||
static const struct qcom_reset_map video_cc_sm8450_resets[] = {
|
||||
[CVP_VIDEO_CC_INTERFACE_BCR] = { 0x80e0 },
|
||||
[CVP_VIDEO_CC_MVS0_BCR] = { 0x8098 },
|
||||
[CVP_VIDEO_CC_MVS0C_BCR] = { 0x8048 },
|
||||
[CVP_VIDEO_CC_MVS1_BCR] = { 0x80bc },
|
||||
[CVP_VIDEO_CC_MVS1C_BCR] = { 0x8070 },
|
||||
[VIDEO_CC_MVS0C_CLK_ARES] = { 0x8064, 2 },
|
||||
[VIDEO_CC_MVS1C_CLK_ARES] = { 0x808c, 2 },
|
||||
};
|
||||
|
||||
static const struct regmap_config video_cc_sm8450_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0x9f4c,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static struct qcom_cc_desc video_cc_sm8450_desc = {
|
||||
.config = &video_cc_sm8450_regmap_config,
|
||||
.clks = video_cc_sm8450_clocks,
|
||||
.num_clks = ARRAY_SIZE(video_cc_sm8450_clocks),
|
||||
.resets = video_cc_sm8450_resets,
|
||||
.num_resets = ARRAY_SIZE(video_cc_sm8450_resets),
|
||||
.gdscs = video_cc_sm8450_gdscs,
|
||||
.num_gdscs = ARRAY_SIZE(video_cc_sm8450_gdscs),
|
||||
};
|
||||
|
||||
static const struct of_device_id video_cc_sm8450_match_table[] = {
|
||||
{ .compatible = "qcom,sm8450-videocc" },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, video_cc_sm8450_match_table);
|
||||
|
||||
static int video_cc_sm8450_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct regmap *regmap;
|
||||
int ret;
|
||||
|
||||
ret = devm_pm_runtime_enable(&pdev->dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = pm_runtime_resume_and_get(&pdev->dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
regmap = qcom_cc_map(pdev, &video_cc_sm8450_desc);
|
||||
if (IS_ERR(regmap)) {
|
||||
pm_runtime_put(&pdev->dev);
|
||||
return PTR_ERR(regmap);
|
||||
}
|
||||
|
||||
clk_lucid_evo_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config);
|
||||
clk_lucid_evo_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config);
|
||||
|
||||
/*
|
||||
* Keep clocks always enabled:
|
||||
* video_cc_ahb_clk
|
||||
* video_cc_sleep_clk
|
||||
* video_cc_xo_clk
|
||||
*/
|
||||
regmap_update_bits(regmap, 0x80e4, BIT(0), BIT(0));
|
||||
regmap_update_bits(regmap, 0x8130, BIT(0), BIT(0));
|
||||
regmap_update_bits(regmap, 0x8114, BIT(0), BIT(0));
|
||||
|
||||
ret = qcom_cc_really_probe(pdev, &video_cc_sm8450_desc, regmap);
|
||||
|
||||
pm_runtime_put(&pdev->dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct platform_driver video_cc_sm8450_driver = {
|
||||
.probe = video_cc_sm8450_probe,
|
||||
.driver = {
|
||||
.name = "video_cc-sm8450",
|
||||
.of_match_table = video_cc_sm8450_match_table,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init video_cc_sm8450_init(void)
|
||||
{
|
||||
return platform_driver_register(&video_cc_sm8450_driver);
|
||||
}
|
||||
subsys_initcall(video_cc_sm8450_init);
|
||||
|
||||
static void __exit video_cc_sm8450_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&video_cc_sm8450_driver);
|
||||
}
|
||||
module_exit(video_cc_sm8450_exit);
|
||||
|
||||
MODULE_DESCRIPTION("QTI VIDEOCC SM8450 Driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -0,0 +1,470 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
#include <dt-bindings/clock/qcom,sm8450-videocc.h>
|
||||
|
||||
#include "clk-alpha-pll.h"
|
||||
#include "clk-branch.h"
|
||||
#include "clk-rcg.h"
|
||||
#include "clk-regmap.h"
|
||||
#include "clk-regmap-divider.h"
|
||||
#include "common.h"
|
||||
#include "gdsc.h"
|
||||
#include "reset.h"
|
||||
|
||||
enum {
|
||||
DT_BI_TCXO,
|
||||
};
|
||||
|
||||
enum {
|
||||
P_BI_TCXO,
|
||||
P_VIDEO_CC_PLL0_OUT_MAIN,
|
||||
P_VIDEO_CC_PLL1_OUT_MAIN,
|
||||
};
|
||||
|
||||
static const struct pll_vco lucid_ole_vco[] = {
|
||||
{ 249600000, 2300000000, 0 },
|
||||
};
|
||||
|
||||
static const struct alpha_pll_config video_cc_pll0_config = {
|
||||
/* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */
|
||||
.l = 0x44440025,
|
||||
.alpha = 0x8000,
|
||||
.config_ctl_val = 0x20485699,
|
||||
.config_ctl_hi_val = 0x00182261,
|
||||
.config_ctl_hi1_val = 0x82aa299c,
|
||||
.test_ctl_val = 0x00000000,
|
||||
.test_ctl_hi_val = 0x00000003,
|
||||
.test_ctl_hi1_val = 0x00009000,
|
||||
.test_ctl_hi2_val = 0x00000034,
|
||||
.user_ctl_val = 0x00000000,
|
||||
.user_ctl_hi_val = 0x00000005,
|
||||
};
|
||||
|
||||
static struct clk_alpha_pll video_cc_pll0 = {
|
||||
.offset = 0x0,
|
||||
.vco_table = lucid_ole_vco,
|
||||
.num_vco = ARRAY_SIZE(lucid_ole_vco),
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
|
||||
.clkr = {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "video_cc_pll0",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.index = DT_BI_TCXO,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_lucid_evo_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct alpha_pll_config video_cc_pll1_config = {
|
||||
/* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */
|
||||
.l = 0x44440036,
|
||||
.alpha = 0xb000,
|
||||
.config_ctl_val = 0x20485699,
|
||||
.config_ctl_hi_val = 0x00182261,
|
||||
.config_ctl_hi1_val = 0x82aa299c,
|
||||
.test_ctl_val = 0x00000000,
|
||||
.test_ctl_hi_val = 0x00000003,
|
||||
.test_ctl_hi1_val = 0x00009000,
|
||||
.test_ctl_hi2_val = 0x00000034,
|
||||
.user_ctl_val = 0x00000000,
|
||||
.user_ctl_hi_val = 0x00000005,
|
||||
};
|
||||
|
||||
static struct clk_alpha_pll video_cc_pll1 = {
|
||||
.offset = 0x1000,
|
||||
.vco_table = lucid_ole_vco,
|
||||
.num_vco = ARRAY_SIZE(lucid_ole_vco),
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
|
||||
.clkr = {
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "video_cc_pll1",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.index = DT_BI_TCXO,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_lucid_evo_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct parent_map video_cc_parent_map_0[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_VIDEO_CC_PLL0_OUT_MAIN, 1 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data video_cc_parent_data_0[] = {
|
||||
{ .index = DT_BI_TCXO },
|
||||
{ .hw = &video_cc_pll0.clkr.hw },
|
||||
};
|
||||
|
||||
static const struct parent_map video_cc_parent_map_1[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_VIDEO_CC_PLL1_OUT_MAIN, 1 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data video_cc_parent_data_1[] = {
|
||||
{ .index = DT_BI_TCXO },
|
||||
{ .hw = &video_cc_pll1.clkr.hw },
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = {
|
||||
F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
|
||||
F(1014000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
|
||||
F(1098000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
|
||||
F(1332000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
|
||||
F(1600000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 video_cc_mvs0_clk_src = {
|
||||
.cmd_rcgr = 0x8000,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = video_cc_parent_map_0,
|
||||
.freq_tbl = ftbl_video_cc_mvs0_clk_src,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "video_cc_mvs0_clk_src",
|
||||
.parent_data = video_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(video_cc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = {
|
||||
F(1050000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
|
||||
F(1350000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
|
||||
F(1500000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
|
||||
F(1650000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 video_cc_mvs1_clk_src = {
|
||||
.cmd_rcgr = 0x8018,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = video_cc_parent_map_1,
|
||||
.freq_tbl = ftbl_video_cc_mvs1_clk_src,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "video_cc_mvs1_clk_src",
|
||||
.parent_data = video_cc_parent_data_1,
|
||||
.num_parents = ARRAY_SIZE(video_cc_parent_data_1),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_div video_cc_mvs0_div_clk_src = {
|
||||
.reg = 0x80c4,
|
||||
.shift = 0,
|
||||
.width = 4,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "video_cc_mvs0_div_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&video_cc_mvs0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_regmap_div_ro_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src = {
|
||||
.reg = 0x8070,
|
||||
.shift = 0,
|
||||
.width = 4,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "video_cc_mvs0c_div2_div_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&video_cc_mvs0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_regmap_div_ro_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_div video_cc_mvs1_div_clk_src = {
|
||||
.reg = 0x80ec,
|
||||
.shift = 0,
|
||||
.width = 4,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "video_cc_mvs1_div_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&video_cc_mvs1_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_regmap_div_ro_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_div video_cc_mvs1c_div2_div_clk_src = {
|
||||
.reg = 0x809c,
|
||||
.shift = 0,
|
||||
.width = 4,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "video_cc_mvs1c_div2_div_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&video_cc_mvs1_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_regmap_div_ro_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch video_cc_mvs0_clk = {
|
||||
.halt_reg = 0x80b8,
|
||||
.halt_check = BRANCH_HALT_SKIP,
|
||||
.hwcg_reg = 0x80b8,
|
||||
.hwcg_bit = 1,
|
||||
.clkr = {
|
||||
.enable_reg = 0x80b8,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "video_cc_mvs0_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&video_cc_mvs0_div_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch video_cc_mvs0c_clk = {
|
||||
.halt_reg = 0x8064,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x8064,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "video_cc_mvs0c_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&video_cc_mvs0c_div2_div_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch video_cc_mvs1_clk = {
|
||||
.halt_reg = 0x80e0,
|
||||
.halt_check = BRANCH_HALT_SKIP,
|
||||
.hwcg_reg = 0x80e0,
|
||||
.hwcg_bit = 1,
|
||||
.clkr = {
|
||||
.enable_reg = 0x80e0,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "video_cc_mvs1_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&video_cc_mvs1_div_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch video_cc_mvs1c_clk = {
|
||||
.halt_reg = 0x8090,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x8090,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "video_cc_mvs1c_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&video_cc_mvs1c_div2_div_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct gdsc video_cc_mvs0c_gdsc = {
|
||||
.gdscr = 0x804c,
|
||||
.en_rest_wait_val = 0x2,
|
||||
.en_few_wait_val = 0x2,
|
||||
.clk_dis_wait_val = 0x6,
|
||||
.pd = {
|
||||
.name = "video_cc_mvs0c_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
|
||||
};
|
||||
|
||||
static struct gdsc video_cc_mvs0_gdsc = {
|
||||
.gdscr = 0x80a4,
|
||||
.en_rest_wait_val = 0x2,
|
||||
.en_few_wait_val = 0x2,
|
||||
.clk_dis_wait_val = 0x6,
|
||||
.pd = {
|
||||
.name = "video_cc_mvs0_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.parent = &video_cc_mvs0c_gdsc.pd,
|
||||
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL,
|
||||
};
|
||||
|
||||
static struct gdsc video_cc_mvs1c_gdsc = {
|
||||
.gdscr = 0x8078,
|
||||
.en_rest_wait_val = 0x2,
|
||||
.en_few_wait_val = 0x2,
|
||||
.clk_dis_wait_val = 0x6,
|
||||
.pd = {
|
||||
.name = "video_cc_mvs1c_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
|
||||
};
|
||||
|
||||
static struct gdsc video_cc_mvs1_gdsc = {
|
||||
.gdscr = 0x80cc,
|
||||
.en_rest_wait_val = 0x2,
|
||||
.en_few_wait_val = 0x2,
|
||||
.clk_dis_wait_val = 0x6,
|
||||
.pd = {
|
||||
.name = "video_cc_mvs1_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.parent = &video_cc_mvs1c_gdsc.pd,
|
||||
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL,
|
||||
};
|
||||
|
||||
static struct clk_regmap *video_cc_sm8550_clocks[] = {
|
||||
[VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr,
|
||||
[VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr,
|
||||
[VIDEO_CC_MVS0_DIV_CLK_SRC] = &video_cc_mvs0_div_clk_src.clkr,
|
||||
[VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr,
|
||||
[VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] = &video_cc_mvs0c_div2_div_clk_src.clkr,
|
||||
[VIDEO_CC_MVS1_CLK] = &video_cc_mvs1_clk.clkr,
|
||||
[VIDEO_CC_MVS1_CLK_SRC] = &video_cc_mvs1_clk_src.clkr,
|
||||
[VIDEO_CC_MVS1_DIV_CLK_SRC] = &video_cc_mvs1_div_clk_src.clkr,
|
||||
[VIDEO_CC_MVS1C_CLK] = &video_cc_mvs1c_clk.clkr,
|
||||
[VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] = &video_cc_mvs1c_div2_div_clk_src.clkr,
|
||||
[VIDEO_CC_PLL0] = &video_cc_pll0.clkr,
|
||||
[VIDEO_CC_PLL1] = &video_cc_pll1.clkr,
|
||||
};
|
||||
|
||||
static struct gdsc *video_cc_sm8550_gdscs[] = {
|
||||
[VIDEO_CC_MVS0C_GDSC] = &video_cc_mvs0c_gdsc,
|
||||
[VIDEO_CC_MVS0_GDSC] = &video_cc_mvs0_gdsc,
|
||||
[VIDEO_CC_MVS1C_GDSC] = &video_cc_mvs1c_gdsc,
|
||||
[VIDEO_CC_MVS1_GDSC] = &video_cc_mvs1_gdsc,
|
||||
};
|
||||
|
||||
static const struct qcom_reset_map video_cc_sm8550_resets[] = {
|
||||
[CVP_VIDEO_CC_INTERFACE_BCR] = { 0x80f0 },
|
||||
[CVP_VIDEO_CC_MVS0_BCR] = { 0x80a0 },
|
||||
[CVP_VIDEO_CC_MVS0C_BCR] = { 0x8048 },
|
||||
[CVP_VIDEO_CC_MVS1_BCR] = { 0x80c8 },
|
||||
[CVP_VIDEO_CC_MVS1C_BCR] = { 0x8074 },
|
||||
[VIDEO_CC_MVS0C_CLK_ARES] = { 0x8064, 2 },
|
||||
[VIDEO_CC_MVS1C_CLK_ARES] = { 0x8090, 2 },
|
||||
};
|
||||
|
||||
static const struct regmap_config video_cc_sm8550_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0x9f4c,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static struct qcom_cc_desc video_cc_sm8550_desc = {
|
||||
.config = &video_cc_sm8550_regmap_config,
|
||||
.clks = video_cc_sm8550_clocks,
|
||||
.num_clks = ARRAY_SIZE(video_cc_sm8550_clocks),
|
||||
.resets = video_cc_sm8550_resets,
|
||||
.num_resets = ARRAY_SIZE(video_cc_sm8550_resets),
|
||||
.gdscs = video_cc_sm8550_gdscs,
|
||||
.num_gdscs = ARRAY_SIZE(video_cc_sm8550_gdscs),
|
||||
};
|
||||
|
||||
static const struct of_device_id video_cc_sm8550_match_table[] = {
|
||||
{ .compatible = "qcom,sm8550-videocc" },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, video_cc_sm8550_match_table);
|
||||
|
||||
static int video_cc_sm8550_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct regmap *regmap;
|
||||
int ret;
|
||||
|
||||
ret = devm_pm_runtime_enable(&pdev->dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = pm_runtime_resume_and_get(&pdev->dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
regmap = qcom_cc_map(pdev, &video_cc_sm8550_desc);
|
||||
if (IS_ERR(regmap)) {
|
||||
pm_runtime_put(&pdev->dev);
|
||||
return PTR_ERR(regmap);
|
||||
}
|
||||
|
||||
clk_lucid_evo_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config);
|
||||
clk_lucid_evo_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config);
|
||||
|
||||
/*
|
||||
* Keep clocks always enabled:
|
||||
* video_cc_ahb_clk
|
||||
* video_cc_sleep_clk
|
||||
* video_cc_xo_clk
|
||||
*/
|
||||
regmap_update_bits(regmap, 0x80f4, BIT(0), BIT(0));
|
||||
regmap_update_bits(regmap, 0x8140, BIT(0), BIT(0));
|
||||
regmap_update_bits(regmap, 0x8124, BIT(0), BIT(0));
|
||||
|
||||
ret = qcom_cc_really_probe(pdev, &video_cc_sm8550_desc, regmap);
|
||||
|
||||
pm_runtime_put(&pdev->dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct platform_driver video_cc_sm8550_driver = {
|
||||
.probe = video_cc_sm8550_probe,
|
||||
.driver = {
|
||||
.name = "video_cc-sm8550",
|
||||
.of_match_table = video_cc_sm8550_match_table,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init video_cc_sm8550_init(void)
|
||||
{
|
||||
return platform_driver_register(&video_cc_sm8550_driver);
|
||||
}
|
||||
subsys_initcall(video_cc_sm8550_init);
|
||||
|
||||
static void __exit video_cc_sm8550_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&video_cc_sm8550_driver);
|
||||
}
|
||||
module_exit(video_cc_sm8550_exit);
|
||||
|
||||
MODULE_DESCRIPTION("QTI VIDEOCC SM8550 Driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -210,4 +210,8 @@
|
|||
#define GCC_SNOC_PCIE1_1LANE_S_CLK 201
|
||||
#define GCC_SNOC_PCIE2_2LANE_S_CLK 202
|
||||
#define GCC_SNOC_PCIE3_2LANE_S_CLK 203
|
||||
#define GCC_CRYPTO_CLK_SRC 204
|
||||
#define GCC_CRYPTO_CLK 205
|
||||
#define GCC_CRYPTO_AXI_CLK 206
|
||||
#define GCC_CRYPTO_AHB_CLK 207
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1,17 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2023, Linaro Ltd.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H
|
||||
|
||||
/* LPASS AUDIO CC CSR */
|
||||
#define LPASS_AUDIO_SWR_RX_CGCR 0
|
||||
#define LPASS_AUDIO_SWR_WSA_CGCR 1
|
||||
#define LPASS_AUDIO_SWR_WSA2_CGCR 2
|
||||
|
||||
/* LPASS TCSR */
|
||||
#define LPASS_AUDIO_SWR_TX_CGCR 0
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,193 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SDX75_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_GCC_SDX75_H
|
||||
|
||||
/* GCC clocks */
|
||||
#define GPLL0 0
|
||||
#define GPLL0_OUT_EVEN 1
|
||||
#define GPLL4 2
|
||||
#define GPLL5 3
|
||||
#define GPLL6 4
|
||||
#define GPLL8 5
|
||||
#define GCC_AHB_PCIE_LINK_CLK 6
|
||||
#define GCC_BOOT_ROM_AHB_CLK 7
|
||||
#define GCC_EEE_EMAC0_CLK 8
|
||||
#define GCC_EEE_EMAC0_CLK_SRC 9
|
||||
#define GCC_EEE_EMAC1_CLK 10
|
||||
#define GCC_EEE_EMAC1_CLK_SRC 11
|
||||
#define GCC_EMAC0_AXI_CLK 12
|
||||
#define GCC_EMAC0_CC_SGMIIPHY_RX_CLK 13
|
||||
#define GCC_EMAC0_CC_SGMIIPHY_RX_CLK_SRC 14
|
||||
#define GCC_EMAC0_CC_SGMIIPHY_TX_CLK 15
|
||||
#define GCC_EMAC0_CC_SGMIIPHY_TX_CLK_SRC 16
|
||||
#define GCC_EMAC0_PHY_AUX_CLK 17
|
||||
#define GCC_EMAC0_PHY_AUX_CLK_SRC 18
|
||||
#define GCC_EMAC0_PTP_CLK 19
|
||||
#define GCC_EMAC0_PTP_CLK_SRC 20
|
||||
#define GCC_EMAC0_RGMII_CLK 21
|
||||
#define GCC_EMAC0_RGMII_CLK_SRC 22
|
||||
#define GCC_EMAC0_RPCS_RX_CLK 23
|
||||
#define GCC_EMAC0_RPCS_TX_CLK 24
|
||||
#define GCC_EMAC0_SGMIIPHY_MAC_RCLK_SRC 25
|
||||
#define GCC_EMAC0_SGMIIPHY_MAC_TCLK_SRC 26
|
||||
#define GCC_EMAC0_SLV_AHB_CLK 27
|
||||
#define GCC_EMAC0_XGXS_RX_CLK 28
|
||||
#define GCC_EMAC0_XGXS_TX_CLK 29
|
||||
#define GCC_EMAC1_AXI_CLK 30
|
||||
#define GCC_EMAC1_CC_SGMIIPHY_RX_CLK 31
|
||||
#define GCC_EMAC1_CC_SGMIIPHY_RX_CLK_SRC 32
|
||||
#define GCC_EMAC1_CC_SGMIIPHY_TX_CLK 33
|
||||
#define GCC_EMAC1_CC_SGMIIPHY_TX_CLK_SRC 34
|
||||
#define GCC_EMAC1_PHY_AUX_CLK 35
|
||||
#define GCC_EMAC1_PHY_AUX_CLK_SRC 36
|
||||
#define GCC_EMAC1_PTP_CLK 37
|
||||
#define GCC_EMAC1_PTP_CLK_SRC 38
|
||||
#define GCC_EMAC1_RGMII_CLK 39
|
||||
#define GCC_EMAC1_RGMII_CLK_SRC 40
|
||||
#define GCC_EMAC1_RPCS_RX_CLK 41
|
||||
#define GCC_EMAC1_RPCS_TX_CLK 42
|
||||
#define GCC_EMAC1_SGMIIPHY_MAC_RCLK_SRC 43
|
||||
#define GCC_EMAC1_SGMIIPHY_MAC_TCLK_SRC 44
|
||||
#define GCC_EMAC1_SLV_AHB_CLK 45
|
||||
#define GCC_EMAC1_XGXS_RX_CLK 46
|
||||
#define GCC_EMAC1_XGXS_TX_CLK 47
|
||||
#define GCC_EMAC_0_CLKREF_EN 48
|
||||
#define GCC_EMAC_1_CLKREF_EN 49
|
||||
#define GCC_GP1_CLK 50
|
||||
#define GCC_GP1_CLK_SRC 51
|
||||
#define GCC_GP2_CLK 52
|
||||
#define GCC_GP2_CLK_SRC 53
|
||||
#define GCC_GP3_CLK 54
|
||||
#define GCC_GP3_CLK_SRC 55
|
||||
#define GCC_PCIE_0_CLKREF_EN 56
|
||||
#define GCC_PCIE_1_AUX_CLK 57
|
||||
#define GCC_PCIE_1_AUX_PHY_CLK_SRC 58
|
||||
#define GCC_PCIE_1_CFG_AHB_CLK 59
|
||||
#define GCC_PCIE_1_CLKREF_EN 60
|
||||
#define GCC_PCIE_1_MSTR_AXI_CLK 61
|
||||
#define GCC_PCIE_1_PHY_RCHNG_CLK 62
|
||||
#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 63
|
||||
#define GCC_PCIE_1_PIPE_CLK 64
|
||||
#define GCC_PCIE_1_PIPE_CLK_SRC 65
|
||||
#define GCC_PCIE_1_PIPE_DIV2_CLK 66
|
||||
#define GCC_PCIE_1_PIPE_DIV2_CLK_SRC 67
|
||||
#define GCC_PCIE_1_SLV_AXI_CLK 68
|
||||
#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 69
|
||||
#define GCC_PCIE_2_AUX_CLK 70
|
||||
#define GCC_PCIE_2_AUX_PHY_CLK_SRC 71
|
||||
#define GCC_PCIE_2_CFG_AHB_CLK 72
|
||||
#define GCC_PCIE_2_CLKREF_EN 73
|
||||
#define GCC_PCIE_2_MSTR_AXI_CLK 74
|
||||
#define GCC_PCIE_2_PHY_RCHNG_CLK 75
|
||||
#define GCC_PCIE_2_PHY_RCHNG_CLK_SRC 76
|
||||
#define GCC_PCIE_2_PIPE_CLK 77
|
||||
#define GCC_PCIE_2_PIPE_CLK_SRC 78
|
||||
#define GCC_PCIE_2_PIPE_DIV2_CLK 79
|
||||
#define GCC_PCIE_2_PIPE_DIV2_CLK_SRC 80
|
||||
#define GCC_PCIE_2_SLV_AXI_CLK 81
|
||||
#define GCC_PCIE_2_SLV_Q2A_AXI_CLK 82
|
||||
#define GCC_PCIE_AUX_CLK 83
|
||||
#define GCC_PCIE_AUX_CLK_SRC 84
|
||||
#define GCC_PCIE_AUX_PHY_CLK_SRC 85
|
||||
#define GCC_PCIE_CFG_AHB_CLK 86
|
||||
#define GCC_PCIE_MSTR_AXI_CLK 87
|
||||
#define GCC_PCIE_PIPE_CLK 88
|
||||
#define GCC_PCIE_PIPE_CLK_SRC 89
|
||||
#define GCC_PCIE_RCHNG_PHY_CLK 90
|
||||
#define GCC_PCIE_RCHNG_PHY_CLK_SRC 91
|
||||
#define GCC_PCIE_SLEEP_CLK 92
|
||||
#define GCC_PCIE_SLV_AXI_CLK 93
|
||||
#define GCC_PCIE_SLV_Q2A_AXI_CLK 94
|
||||
#define GCC_PDM2_CLK 95
|
||||
#define GCC_PDM2_CLK_SRC 96
|
||||
#define GCC_PDM_AHB_CLK 97
|
||||
#define GCC_PDM_XO4_CLK 98
|
||||
#define GCC_QUPV3_WRAP0_CORE_2X_CLK 99
|
||||
#define GCC_QUPV3_WRAP0_CORE_CLK 100
|
||||
#define GCC_QUPV3_WRAP0_S0_CLK 101
|
||||
#define GCC_QUPV3_WRAP0_S0_CLK_SRC 102
|
||||
#define GCC_QUPV3_WRAP0_S1_CLK 103
|
||||
#define GCC_QUPV3_WRAP0_S1_CLK_SRC 104
|
||||
#define GCC_QUPV3_WRAP0_S2_CLK 105
|
||||
#define GCC_QUPV3_WRAP0_S2_CLK_SRC 106
|
||||
#define GCC_QUPV3_WRAP0_S3_CLK 107
|
||||
#define GCC_QUPV3_WRAP0_S3_CLK_SRC 108
|
||||
#define GCC_QUPV3_WRAP0_S4_CLK 109
|
||||
#define GCC_QUPV3_WRAP0_S4_CLK_SRC 110
|
||||
#define GCC_QUPV3_WRAP0_S5_CLK 111
|
||||
#define GCC_QUPV3_WRAP0_S5_CLK_SRC 112
|
||||
#define GCC_QUPV3_WRAP0_S6_CLK 113
|
||||
#define GCC_QUPV3_WRAP0_S6_CLK_SRC 114
|
||||
#define GCC_QUPV3_WRAP0_S7_CLK 115
|
||||
#define GCC_QUPV3_WRAP0_S7_CLK_SRC 116
|
||||
#define GCC_QUPV3_WRAP0_S8_CLK 117
|
||||
#define GCC_QUPV3_WRAP0_S8_CLK_SRC 118
|
||||
#define GCC_QUPV3_WRAP_0_M_AHB_CLK 119
|
||||
#define GCC_QUPV3_WRAP_0_S_AHB_CLK 120
|
||||
#define GCC_SDCC1_AHB_CLK 121
|
||||
#define GCC_SDCC1_APPS_CLK 122
|
||||
#define GCC_SDCC1_APPS_CLK_SRC 123
|
||||
#define GCC_SDCC2_AHB_CLK 124
|
||||
#define GCC_SDCC2_APPS_CLK 125
|
||||
#define GCC_SDCC2_APPS_CLK_SRC 126
|
||||
#define GCC_USB2_CLKREF_EN 127
|
||||
#define GCC_USB30_MASTER_CLK 128
|
||||
#define GCC_USB30_MASTER_CLK_SRC 129
|
||||
#define GCC_USB30_MOCK_UTMI_CLK 130
|
||||
#define GCC_USB30_MOCK_UTMI_CLK_SRC 131
|
||||
#define GCC_USB30_MOCK_UTMI_POSTDIV_CLK_SRC 132
|
||||
#define GCC_USB30_MSTR_AXI_CLK 133
|
||||
#define GCC_USB30_SLEEP_CLK 134
|
||||
#define GCC_USB30_SLV_AHB_CLK 135
|
||||
#define GCC_USB3_PHY_AUX_CLK 136
|
||||
#define GCC_USB3_PHY_AUX_CLK_SRC 137
|
||||
#define GCC_USB3_PHY_PIPE_CLK 138
|
||||
#define GCC_USB3_PHY_PIPE_CLK_SRC 139
|
||||
#define GCC_USB3_PRIM_CLKREF_EN 140
|
||||
#define GCC_USB_PHY_CFG_AHB2PHY_CLK 141
|
||||
#define GCC_XO_PCIE_LINK_CLK 142
|
||||
|
||||
/* GCC power domains */
|
||||
#define GCC_EMAC0_GDSC 0
|
||||
#define GCC_EMAC1_GDSC 1
|
||||
#define GCC_PCIE_1_GDSC 2
|
||||
#define GCC_PCIE_1_PHY_GDSC 3
|
||||
#define GCC_PCIE_2_GDSC 4
|
||||
#define GCC_PCIE_2_PHY_GDSC 5
|
||||
#define GCC_PCIE_GDSC 6
|
||||
#define GCC_PCIE_PHY_GDSC 7
|
||||
#define GCC_USB30_GDSC 8
|
||||
#define GCC_USB3_PHY_GDSC 9
|
||||
|
||||
/* GCC resets */
|
||||
#define GCC_EMAC0_BCR 0
|
||||
#define GCC_EMAC1_BCR 1
|
||||
#define GCC_EMMC_BCR 2
|
||||
#define GCC_PCIE_1_BCR 3
|
||||
#define GCC_PCIE_1_LINK_DOWN_BCR 4
|
||||
#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 5
|
||||
#define GCC_PCIE_1_PHY_BCR 6
|
||||
#define GCC_PCIE_2_BCR 7
|
||||
#define GCC_PCIE_2_LINK_DOWN_BCR 8
|
||||
#define GCC_PCIE_2_NOCSR_COM_PHY_BCR 9
|
||||
#define GCC_PCIE_2_PHY_BCR 10
|
||||
#define GCC_PCIE_BCR 11
|
||||
#define GCC_PCIE_LINK_DOWN_BCR 12
|
||||
#define GCC_PCIE_NOCSR_COM_PHY_BCR 13
|
||||
#define GCC_PCIE_PHY_BCR 14
|
||||
#define GCC_PCIE_PHY_CFG_AHB_BCR 15
|
||||
#define GCC_PCIE_PHY_COM_BCR 16
|
||||
#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR 17
|
||||
#define GCC_QUSB2PHY_BCR 18
|
||||
#define GCC_TCSR_PCIE_BCR 19
|
||||
#define GCC_USB30_BCR 20
|
||||
#define GCC_USB3_PHY_BCR 21
|
||||
#define GCC_USB3PHY_PHY_BCR 22
|
||||
#define GCC_USB_PHY_CFG_AHB2PHY_BCR 23
|
||||
#define GCC_EMAC0_RGMII_CLK_ARES 24
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2023, Linaro Limited
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8350_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8350_H
|
||||
|
||||
/* Clocks */
|
||||
#define VIDEO_CC_AHB_CLK_SRC 0
|
||||
#define VIDEO_CC_MVS0_CLK 1
|
||||
#define VIDEO_CC_MVS0_CLK_SRC 2
|
||||
#define VIDEO_CC_MVS0_DIV_CLK_SRC 3
|
||||
#define VIDEO_CC_MVS0C_CLK 4
|
||||
#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 5
|
||||
#define VIDEO_CC_MVS1_CLK 6
|
||||
#define VIDEO_CC_MVS1_CLK_SRC 7
|
||||
#define VIDEO_CC_MVS1_DIV2_CLK 8
|
||||
#define VIDEO_CC_MVS1_DIV_CLK_SRC 9
|
||||
#define VIDEO_CC_MVS1C_CLK 10
|
||||
#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 11
|
||||
#define VIDEO_CC_SLEEP_CLK 12
|
||||
#define VIDEO_CC_SLEEP_CLK_SRC 13
|
||||
#define VIDEO_CC_XO_CLK_SRC 14
|
||||
#define VIDEO_PLL0 15
|
||||
#define VIDEO_PLL1 16
|
||||
|
||||
/* GDSCs */
|
||||
#define MVS0C_GDSC 0
|
||||
#define MVS1C_GDSC 1
|
||||
#define MVS0_GDSC 2
|
||||
#define MVS1_GDSC 3
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2023, Linaro Limited
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8450_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8450_H
|
||||
|
||||
/* Clocks */
|
||||
#define GPU_CC_AHB_CLK 0
|
||||
#define GPU_CC_CRC_AHB_CLK 1
|
||||
#define GPU_CC_CX_APB_CLK 2
|
||||
#define GPU_CC_CX_FF_CLK 3
|
||||
#define GPU_CC_CX_GMU_CLK 4
|
||||
#define GPU_CC_CX_SNOC_DVM_CLK 5
|
||||
#define GPU_CC_CXO_AON_CLK 6
|
||||
#define GPU_CC_CXO_CLK 7
|
||||
#define GPU_CC_DEMET_CLK 8
|
||||
#define GPU_CC_DEMET_DIV_CLK_SRC 9
|
||||
#define GPU_CC_FF_CLK_SRC 10
|
||||
#define GPU_CC_FREQ_MEASURE_CLK 11
|
||||
#define GPU_CC_GMU_CLK_SRC 12
|
||||
#define GPU_CC_GX_FF_CLK 13
|
||||
#define GPU_CC_GX_GFX3D_CLK 14
|
||||
#define GPU_CC_GX_GFX3D_RDVM_CLK 15
|
||||
#define GPU_CC_GX_GMU_CLK 16
|
||||
#define GPU_CC_GX_VSENSE_CLK 17
|
||||
#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 18
|
||||
#define GPU_CC_HUB_AHB_DIV_CLK_SRC 19
|
||||
#define GPU_CC_HUB_AON_CLK 20
|
||||
#define GPU_CC_HUB_CLK_SRC 21
|
||||
#define GPU_CC_HUB_CX_INT_CLK 22
|
||||
#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 23
|
||||
#define GPU_CC_MEMNOC_GFX_CLK 24
|
||||
#define GPU_CC_MND1X_0_GFX3D_CLK 25
|
||||
#define GPU_CC_MND1X_1_GFX3D_CLK 26
|
||||
#define GPU_CC_PLL0 27
|
||||
#define GPU_CC_PLL1 28
|
||||
#define GPU_CC_SLEEP_CLK 29
|
||||
#define GPU_CC_XO_CLK_SRC 30
|
||||
#define GPU_CC_XO_DIV_CLK_SRC 31
|
||||
|
||||
/* GDSCs */
|
||||
#define GPU_GX_GDSC 0
|
||||
#define GPU_CX_GDSC 1
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8450_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8450_H
|
||||
|
||||
/* VIDEO_CC clocks */
|
||||
#define VIDEO_CC_MVS0_CLK 0
|
||||
#define VIDEO_CC_MVS0_CLK_SRC 1
|
||||
#define VIDEO_CC_MVS0_DIV_CLK_SRC 2
|
||||
#define VIDEO_CC_MVS0C_CLK 3
|
||||
#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 4
|
||||
#define VIDEO_CC_MVS1_CLK 5
|
||||
#define VIDEO_CC_MVS1_CLK_SRC 6
|
||||
#define VIDEO_CC_MVS1_DIV_CLK_SRC 7
|
||||
#define VIDEO_CC_MVS1C_CLK 8
|
||||
#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 9
|
||||
#define VIDEO_CC_PLL0 10
|
||||
#define VIDEO_CC_PLL1 11
|
||||
|
||||
/* VIDEO_CC power domains */
|
||||
#define VIDEO_CC_MVS0C_GDSC 0
|
||||
#define VIDEO_CC_MVS0_GDSC 1
|
||||
#define VIDEO_CC_MVS1C_GDSC 2
|
||||
#define VIDEO_CC_MVS1_GDSC 3
|
||||
|
||||
/* VIDEO_CC resets */
|
||||
#define CVP_VIDEO_CC_INTERFACE_BCR 0
|
||||
#define CVP_VIDEO_CC_MVS0_BCR 1
|
||||
#define CVP_VIDEO_CC_MVS0C_BCR 2
|
||||
#define CVP_VIDEO_CC_MVS1_BCR 3
|
||||
#define CVP_VIDEO_CC_MVS1C_BCR 4
|
||||
#define VIDEO_CC_MVS0C_CLK_ARES 5
|
||||
#define VIDEO_CC_MVS1C_CLK_ARES 6
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8550_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8550_H
|
||||
|
||||
/* GPU_CC clocks */
|
||||
#define GPU_CC_AHB_CLK 0
|
||||
#define GPU_CC_CRC_AHB_CLK 1
|
||||
#define GPU_CC_CX_FF_CLK 2
|
||||
#define GPU_CC_CX_GMU_CLK 3
|
||||
#define GPU_CC_CXO_AON_CLK 4
|
||||
#define GPU_CC_CXO_CLK 5
|
||||
#define GPU_CC_DEMET_CLK 6
|
||||
#define GPU_CC_DEMET_DIV_CLK_SRC 7
|
||||
#define GPU_CC_FF_CLK_SRC 8
|
||||
#define GPU_CC_FREQ_MEASURE_CLK 9
|
||||
#define GPU_CC_GMU_CLK_SRC 10
|
||||
#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 11
|
||||
#define GPU_CC_HUB_AON_CLK 12
|
||||
#define GPU_CC_HUB_CLK_SRC 13
|
||||
#define GPU_CC_HUB_CX_INT_CLK 14
|
||||
#define GPU_CC_MEMNOC_GFX_CLK 15
|
||||
#define GPU_CC_MND1X_0_GFX3D_CLK 16
|
||||
#define GPU_CC_MND1X_1_GFX3D_CLK 17
|
||||
#define GPU_CC_PLL0 18
|
||||
#define GPU_CC_PLL1 19
|
||||
#define GPU_CC_SLEEP_CLK 20
|
||||
#define GPU_CC_XO_CLK_SRC 21
|
||||
#define GPU_CC_XO_DIV_CLK_SRC 22
|
||||
|
||||
/* GPU_CC power domains */
|
||||
#define GPU_CC_CX_GDSC 0
|
||||
#define GPU_CC_GX_GDSC 1
|
||||
|
||||
/* GPU_CC resets */
|
||||
#define GPUCC_GPU_CC_ACD_BCR 0
|
||||
#define GPUCC_GPU_CC_CX_BCR 1
|
||||
#define GPUCC_GPU_CC_FAST_HUB_BCR 2
|
||||
#define GPUCC_GPU_CC_FF_BCR 3
|
||||
#define GPUCC_GPU_CC_GFX3D_AON_BCR 4
|
||||
#define GPUCC_GPU_CC_GMU_BCR 5
|
||||
#define GPUCC_GPU_CC_GX_BCR 6
|
||||
#define GPUCC_GPU_CC_XO_BCR 7
|
||||
|
||||
#endif
|
||||
|
|
@ -160,5 +160,6 @@
|
|||
#define GCC_WCSS_Q6_BCR 151
|
||||
#define GCC_WCSS_Q6_TBU_BCR 152
|
||||
#define GCC_TCSR_BCR 153
|
||||
#define GCC_CRYPTO_BCR 154
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1,18 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2023, Linaro Limited
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_RESET_QCOM_VIDEO_CC_SM8350_H
|
||||
#define _DT_BINDINGS_RESET_QCOM_VIDEO_CC_SM8350_H
|
||||
|
||||
#define VIDEO_CC_CVP_INTERFACE_BCR 0
|
||||
#define VIDEO_CC_CVP_MVS0_BCR 1
|
||||
#define VIDEO_CC_MVS0C_CLK_ARES 2
|
||||
#define VIDEO_CC_CVP_MVS0C_BCR 3
|
||||
#define VIDEO_CC_CVP_MVS1_BCR 4
|
||||
#define VIDEO_CC_MVS1C_CLK_ARES 5
|
||||
#define VIDEO_CC_CVP_MVS1C_BCR 6
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2023, Linaro Limited
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_RESET_QCOM_GPU_CC_SM8450_H
|
||||
#define _DT_BINDINGS_RESET_QCOM_GPU_CC_SM8450_H
|
||||
|
||||
#define GPUCC_GPU_CC_ACD_BCR 0
|
||||
#define GPUCC_GPU_CC_CX_BCR 1
|
||||
#define GPUCC_GPU_CC_FAST_HUB_BCR 2
|
||||
#define GPUCC_GPU_CC_FF_BCR 3
|
||||
#define GPUCC_GPU_CC_GFX3D_AON_BCR 4
|
||||
#define GPUCC_GPU_CC_GMU_BCR 5
|
||||
#define GPUCC_GPU_CC_GX_BCR 6
|
||||
#define GPUCC_GPU_CC_XO_BCR 7
|
||||
#define GPUCC_GPU_CC_GX_ACD_IROOT_BCR 8
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue