drm/amd/pm: update SMU 13.0.0 driver_if header
To fit the latest 78.53 PMFW. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -24,12 +24,8 @@
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#ifndef SMU13_DRIVER_IF_V13_0_0_H
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#define SMU13_DRIVER_IF_V13_0_0_H
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// *** IMPORTANT ***
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// PMFW TEAM: Always increment the interface version on any change to this file
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#define SMU13_DRIVER_IF_VERSION 0x23
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//Increment this version if SkuTable_t or BoardTable_t change
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#define PPTABLE_VERSION 0x1D
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#define PPTABLE_VERSION 0x22
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#define NUM_GFXCLK_DPM_LEVELS 16
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#define NUM_SOCCLK_DPM_LEVELS 8
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@ -1193,8 +1189,17 @@ typedef struct {
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// SECTION: Advanced Options
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uint32_t DebugOverrides;
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// Section: Total Board Power idle vs active coefficients
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uint8_t TotalBoardPowerSupport;
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uint8_t TotalBoardPowerPadding[3];
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int16_t TotalIdleBoardPowerM;
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int16_t TotalIdleBoardPowerB;
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int16_t TotalBoardPowerM;
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int16_t TotalBoardPowerB;
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// SECTION: Sku Reserved
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uint32_t Spare[64];
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uint32_t Spare[61];
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// Padding for MMHUB - do not modify this
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uint32_t MmHubPadding[8];
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@ -1259,7 +1264,8 @@ typedef struct {
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// SECTION: Clock Spread Spectrum
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// UCLK Spread Spectrum
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uint16_t UclkSpreadPadding;
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uint8_t UclkTrainingModeSpreadPercent;
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uint8_t UclkSpreadPadding;
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uint16_t UclkSpreadFreq; // kHz
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// UCLK Spread Spectrum
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@ -1272,11 +1278,7 @@ typedef struct {
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// Section: Memory Config
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uint8_t DramWidth; // Width of interface to the channel for each DRAM module. See DRAM_BIT_WIDTH_TYPE_e
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uint8_t PaddingMem1[3];
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// Section: Total Board Power
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uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power
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uint16_t BoardPowerPadding;
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uint8_t PaddingMem1[7];
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// SECTION: UMC feature flags
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uint8_t HsrEnabled;
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@ -1375,8 +1377,11 @@ typedef struct {
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uint16_t Vcn1ActivityPercentage ;
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uint32_t EnergyAccumulator;
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uint16_t AverageSocketPower ;
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uint16_t AverageSocketPower;
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uint16_t AverageTotalBoardPower;
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uint16_t AvgTemperature[TEMP_COUNT];
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uint16_t TempPadding;
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uint8_t PcieRate ;
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uint8_t PcieWidth ;
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@ -30,7 +30,7 @@
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#define SMU13_DRIVER_IF_VERSION_ALDE 0x08
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#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_4 0x05
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#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_5 0x04
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#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_0 0x2C
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#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_0 0x2E
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#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_7 0x2C
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#define SMU13_MODE1_RESET_WAIT_TIME_IN_MS 500 //500ms
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