Documentation: Add debugfs doc for hisi_zip
Add debugfs descriptions for HiSilicon ZIP and QM driver. Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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What: /sys/kernel/debug/hisi_zip/<bdf>/comp_core[01]/regs
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Date: Nov 2018
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Contact: linux-crypto@vger.kernel.org
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Description: Dump of compression cores related debug registers.
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Only available for PF.
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What: /sys/kernel/debug/hisi_zip/<bdf>/decomp_core[0-5]/regs
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Date: Nov 2018
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Contact: linux-crypto@vger.kernel.org
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Description: Dump of decompression cores related debug registers.
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Only available for PF.
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What: /sys/kernel/debug/hisi_zip/<bdf>/clear_enable
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Date: Nov 2018
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Contact: linux-crypto@vger.kernel.org
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Description: Compression/decompression core debug registers read clear
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control. 1 means enable register read clear, otherwise 0.
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Writing to this file has no functional effect, only enable or
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disable counters clear after reading of these registers.
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Only available for PF.
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What: /sys/kernel/debug/hisi_zip/<bdf>/current_qm
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Date: Nov 2018
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Contact: linux-crypto@vger.kernel.org
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Description: One ZIP controller has one PF and multiple VFs, each function
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has a QM. Select the QM which below qm refers to.
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Only available for PF.
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What: /sys/kernel/debug/hisi_zip/<bdf>/qm/qm_regs
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Date: Nov 2018
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Contact: linux-crypto@vger.kernel.org
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Description: Dump of QM related debug registers.
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Available for PF and VF in host. VF in guest currently only
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has one debug register.
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What: /sys/kernel/debug/hisi_zip/<bdf>/qm/current_q
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Date: Nov 2018
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Contact: linux-crypto@vger.kernel.org
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Description: One QM may contain multiple queues. Select specific queue to
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show its debug registers in above qm_regs.
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Only available for PF.
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What: /sys/kernel/debug/hisi_zip/<bdf>/qm/clear_enable
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Date: Nov 2018
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Contact: linux-crypto@vger.kernel.org
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Description: QM debug registers(qm_regs) read clear control. 1 means enable
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register read clear, otherwise 0.
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Writing to this file has no functional effect, only enable or
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disable counters clear after reading of these registers.
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Only available for PF.
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