clk: meson: switch gxbb ao_clk to clk_regmap
Drop the gxbb ao specific regmap based clock and use the meson clk_regmap based clock instead. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
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@ -20,6 +20,7 @@ config COMMON_CLK_GXBB
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bool
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depends on COMMON_CLK_AMLOGIC
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select RESET_CONTROLLER
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select COMMON_CLK_REGMAP_MESON
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help
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Support for the clock controller on AmLogic S905 devices, aka gxbb.
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Say Y if you want peripherals and CPU frequency scaling to work.
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@ -4,6 +4,6 @@
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obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o clk-audio-divider.o
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obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
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obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-regmap.o gxbb-aoclk-32k.o
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obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
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obj-$(CONFIG_COMMON_CLK_AXG) += axg.o
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obj-$(CONFIG_COMMON_CLK_REGMAP_MESON) += clk-regmap.o
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@ -62,10 +62,9 @@
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#include <linux/delay.h>
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#include <dt-bindings/clock/gxbb-aoclkc.h>
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#include <dt-bindings/reset/gxbb-aoclkc.h>
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#include "clk-regmap.h"
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#include "gxbb-aoclk.h"
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static DEFINE_SPINLOCK(gxbb_aoclk_lock);
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struct gxbb_aoclk_reset_controller {
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struct reset_controller_dev reset;
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unsigned int *data;
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@ -87,12 +86,14 @@ static const struct reset_control_ops gxbb_aoclk_reset_ops = {
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};
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#define GXBB_AO_GATE(_name, _bit) \
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static struct aoclk_gate_regmap _name##_ao = { \
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static struct clk_regmap _name##_ao = { \
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.data = &(struct clk_regmap_gate_data) { \
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.offset = AO_RTI_GEN_CNTL_REG0, \
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.bit_idx = (_bit), \
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.lock = &gxbb_aoclk_lock, \
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}, \
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.hw.init = &(struct clk_init_data) { \
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.name = #_name "_ao", \
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.ops = &meson_aoclk_gate_regmap_ops, \
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.ops = &clk_regmap_gate_ops, \
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.parent_names = (const char *[]){ "clk81" }, \
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.num_parents = 1, \
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.flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \
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@ -107,7 +108,6 @@ GXBB_AO_GATE(uart2, 5);
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GXBB_AO_GATE(ir_blaster, 6);
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static struct aoclk_cec_32k cec_32k_ao = {
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.lock = &gxbb_aoclk_lock,
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.hw.init = &(struct clk_init_data) {
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.name = "cec_32k_ao",
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.ops = &meson_aoclk_cec_32k_ops,
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@ -126,7 +126,7 @@ static unsigned int gxbb_aoclk_reset[] = {
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[RESET_AO_IR_BLASTER] = 23,
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};
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static struct aoclk_gate_regmap *gxbb_aoclk_gate[] = {
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static struct clk_regmap *gxbb_aoclk_gate[] = {
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[CLKID_AO_REMOTE] = &remote_ao,
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[CLKID_AO_I2C_MASTER] = &i2c_master_ao,
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[CLKID_AO_I2C_SLAVE] = &i2c_slave_ao,
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@ -177,7 +177,7 @@ static int gxbb_aoclkc_probe(struct platform_device *pdev)
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* Populate regmap and register all clks
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*/
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for (clkid = 0; clkid < ARRAY_SIZE(gxbb_aoclk_gate); clkid++) {
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gxbb_aoclk_gate[clkid]->regmap = regmap;
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gxbb_aoclk_gate[clkid]->map = regmap;
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ret = devm_clk_hw_register(dev,
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gxbb_aoclk_onecell_data.hws[clkid]);
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@ -32,7 +32,6 @@ extern const struct clk_ops meson_aoclk_gate_regmap_ops;
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struct aoclk_cec_32k {
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struct clk_hw hw;
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struct regmap *regmap;
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spinlock_t *lock;
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};
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#define to_aoclk_cec_32k(_hw) container_of(_hw, struct aoclk_cec_32k, hw)
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