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OMAP2PLUS: DSS2: FEATURES: Function to Provide the max fck supported 

The maximum supported frequency for DSS has increased from 173 to 186 Mhz on
OMAP4.

Introduce a dss feature function to get the max_fck to replace DISPC_MAX_FCK
macro.

Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
This commit is contained in:
Archit Taneja 2011-03-01 11:54:00 +05:30 committed by Tomi Valkeinen
parent 87a7484b6a
commit 819d807c59
5 changed files with 23 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
drivers/video/omap2/dss/dsi.c
View File

@ -38,6 +38,7 @@
#include <plat/clock.h>
#include "dss.h"
#include "dss_features.h"
/*#define VERBOSE_IRQ*/
#define DSI_CATCH_MISSING_TE
@ -856,10 +857,12 @@ int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck,
struct dispc_clock_info best_dispc;
int min_fck_per_pck;
int match = 0;
unsigned long dss_clk_fck2;
unsigned long dss_clk_fck2, max_dss_fck;
dss_clk_fck2 = dss_clk_get_rate(DSS_CLK_SYSCK);
max_dss_fck = dss_feat_get_max_dss_fck();
if (req_pck == dsi.cache_req_pck &&
dsi.cache_cinfo.clkin == dss_clk_fck2) {
DSSDBG("DSI clock info found from cache\n");
@ -872,7 +875,7 @@ int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck,
min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
if (min_fck_per_pck &&
req_pck * min_fck_per_pck > DISPC_MAX_FCK) {
req_pck * min_fck_per_pck > max_dss_fck) {
DSSERR("Requested pixel clock not possible with the current "
"OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
"the constraint off.\n");
@ -925,7 +928,7 @@ retry:
if (cur.dsi1_pll_fclk < req_pck)
break;
if (cur.dsi1_pll_fclk > DISPC_MAX_FCK)
if (cur.dsi1_pll_fclk > max_dss_fck)
continue;
if (min_fck_per_pck &&

8
drivers/video/omap2/dss/dss.c
View File

@ -387,7 +387,7 @@ int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
struct dss_clock_info best_dss;
struct dispc_clock_info best_dispc;
unsigned long fck;
unsigned long fck, max_dss_fck;
u16 fck_div;
@ -396,6 +396,8 @@ int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
prate = dss_get_dpll4_rate();
max_dss_fck = dss_feat_get_max_dss_fck();
fck = dss_clk_get_rate(DSS_CLK_FCK);
if (req_pck == dss.cache_req_pck &&
((cpu_is_omap34xx() && prate == dss.cache_prate) ||
@ -409,7 +411,7 @@ int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
if (min_fck_per_pck &&
req_pck * min_fck_per_pck > DISPC_MAX_FCK) {
req_pck * min_fck_per_pck > max_dss_fck) {
DSSERR("Requested pixel clock not possible with the current "
"OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
"the constraint off.\n");
@ -445,7 +447,7 @@ retry:
else
fck = prate / fck_div * 2;
if (fck > DISPC_MAX_FCK)
if (fck > max_dss_fck)
continue;
if (min_fck_per_pck &&

2
drivers/video/omap2/dss/dss.h
View File

@ -97,8 +97,6 @@ extern unsigned int dss_debug;
#define FLD_MOD(orig, val, start, end) \
(((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
#define DISPC_MAX_FCK 173000000
enum omap_burst_size {
OMAP_DSS_BURST_4x32 = 0,
OMAP_DSS_BURST_8x32 = 1,

11
drivers/video/omap2/dss/dss_features.c
View File

@ -41,6 +41,7 @@ struct omap_dss_features {
const int num_mgrs;
const int num_ovls;
const unsigned long max_dss_fck;
const enum omap_display_type *supported_displays;
const enum omap_color_mode *supported_color_modes;
};
@ -168,6 +169,7 @@ static struct omap_dss_features omap2_dss_features = {
.num_mgrs = 2,
.num_ovls = 3,
.max_dss_fck = 173000000,
.supported_displays = omap2_dss_supported_displays,
.supported_color_modes = omap2_dss_supported_color_modes,
};
@ -185,6 +187,7 @@ static struct omap_dss_features omap3430_dss_features = {
.num_mgrs = 2,
.num_ovls = 3,
.max_dss_fck = 173000000,
.supported_displays = omap3430_dss_supported_displays,
.supported_color_modes = omap3_dss_supported_color_modes,
};
@ -202,6 +205,7 @@ static struct omap_dss_features omap3630_dss_features = {
.num_mgrs = 2,
.num_ovls = 3,
.max_dss_fck = 173000000,
.supported_displays = omap3630_dss_supported_displays,
.supported_color_modes = omap3_dss_supported_color_modes,
};
@ -217,6 +221,7 @@ static struct omap_dss_features omap4_dss_features = {
.num_mgrs = 3,
.num_ovls = 3,
.max_dss_fck = 186000000,
.supported_displays = omap4_dss_supported_displays,
.supported_color_modes = omap3_dss_supported_color_modes,
};
@ -232,6 +237,12 @@ int dss_feat_get_num_ovls(void)
return omap_current_dss_features->num_ovls;
}
/* Max supported DSS FCK in Hz */
unsigned long dss_feat_get_max_dss_fck(void)
{
return omap_current_dss_features->max_dss_fck;
}
enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel)
{
return omap_current_dss_features->supported_displays[channel];

1
drivers/video/omap2/dss/dss_features.h
View File

@ -52,6 +52,7 @@ enum dss_feat_reg_field {
/* DSS Feature Functions */
int dss_feat_get_num_mgrs(void);
int dss_feat_get_num_ovls(void);
unsigned long dss_feat_get_max_dss_fck(void);
enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel);
enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane);
bool dss_feat_color_mode_supported(enum omap_plane plane,