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drm/amdgpu: Add APU support in vi_set_uvd_clocks 

fix the issue set uvd clock failed on CZ/ST
which lead 1s delay when boot up.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Shirish S <shirish.s@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
This commit is contained in:
Rex Zhu 2018-04-10 17:17:22 +08:00 committed by Alex Deucher
parent 29ae1118d8
commit 819a23f83e
1 changed files with 35 additions and 11 deletions
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28
drivers/gpu/drm/amd/amdgpu/vi.c
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@ -728,26 +728,49 @@ static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
return r; return r;
tmp = RREG32_SMC(cntl_reg); tmp = RREG32_SMC(cntl_reg);
if (adev->flags & AMD_IS_APU)
tmp &= ~CG_DCLK_CNTL__DCLK_DIVIDER_MASK;
else
tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK | tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK |
CG_DCLK_CNTL__DCLK_DIVIDER_MASK); CG_DCLK_CNTL__DCLK_DIVIDER_MASK);
tmp |= dividers.post_divider; tmp |= dividers.post_divider;
WREG32_SMC(cntl_reg, tmp); WREG32_SMC(cntl_reg, tmp);
for (i = 0; i < 100; i++) { for (i = 0; i < 100; i++) {
if (RREG32_SMC(status_reg) & CG_DCLK_STATUS__DCLK_STATUS_MASK) tmp = RREG32_SMC(status_reg);
if (adev->flags & AMD_IS_APU) {
if (tmp & 0x10000)
break; break;
} else {
if (tmp & CG_DCLK_STATUS__DCLK_STATUS_MASK)
break;
}
mdelay(10); mdelay(10);
} }
if (i == 100) if (i == 100)
return -ETIMEDOUT; return -ETIMEDOUT;
return 0; return 0;
} }
#define ixGNB_CLK1_DFS_CNTL 0xD82200F0
#define ixGNB_CLK1_STATUS 0xD822010C
#define ixGNB_CLK2_DFS_CNTL 0xD8220110
#define ixGNB_CLK2_STATUS 0xD822012C
static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
{ {
int r; int r;
if (adev->flags & AMD_IS_APU) {
r = vi_set_uvd_clock(adev, vclk, ixGNB_CLK2_DFS_CNTL, ixGNB_CLK2_STATUS);
if (r)
return r;
r = vi_set_uvd_clock(adev, dclk, ixGNB_CLK1_DFS_CNTL, ixGNB_CLK1_STATUS);
if (r)
return r;
} else {
r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
if (r) if (r)
return r; return r;
@ -755,6 +778,7 @@ static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
if (r) if (r)
return r; return r;
}
return 0; return 0;
} }